KR101781617B1 - System on chip including unified input/output memory management unit - Google Patents

Abstract

The present invention relates to a system on chip (SoC) including an integrated input / output memory management unit (IOMMU). A system on chip according to an embodiment of the present invention includes a plurality of IP blocks for generating a transaction having a memory, a bus, a field value for distinguishing a virtual address and a physical address and transmitting the transaction to the bus, And an integrated input / output memory management unit for determining whether or not address conversion is to be performed on the transaction transferred from the bus according to the field value. According to the system-on-chip according to the embodiment of the present invention, the number of input / output memory management units is reduced, and the complexity and power consumption can be reduced in design.

Description

SYSTEM ON CHIP INCLUDING UNIFIED INPUT / OUTPUT MEMORY MANAGEMENT UNIT < RTI ID = 0.0 >

The present invention relates to a system on chip (SoC), and more particularly, to a system on chip including an input / output memory management unit (IOMMU).

System on Chip (hereinafter referred to as SoC) is a technology for integrating complex systems having various functions into a single semiconductor chip. The demand for application specific ICs (ASICs) and application specific standard products (ASSPs) has been shifting to SoCs due to the convergence tendency of integrating computers, communications, and broadcasting. In addition, miniaturization and light weight of IT (Information Technology) devices are promoting SoC related industries.

SoCs include Intellectual Property (IP). The IPs perform specific functions within the SoC, respectively. Typically, these IPs are connected via a bus. An Advanced Microcontroller Bus Architecture (AMBA) of Advanced RISC Machine (ARM) is applied as an exemplary standard bus standard for connection and management of IPs in a SoC. AMBA bus types include Advanced High-Performance Bus (AHB), Advanced Peripheral Bus (APB), and Advanced Extensible Interface (AXI). Of these, AXI is an interface protocol between IPs, including a multiple outstanding address function and a data interleaving function.

Due to the multi-out standing address function, when information is provided via address lines and data lines of the bus, an address for the next data transfer can be transmitted before the data transfer is completed. And, due to the data interleaving function, data intermixing at the receiving end is supported during data transmission between IPs. Therefore, the bandwidth of the bus can be used more efficiently. And it is advantageous in terms of latency.

An object of the present invention is to provide a system on chip (SoC) that integrates a plurality of input / output memory management units (IOMMU) into one input / output memory management unit and controls the same .

A system on chip according to an embodiment of the present invention includes a plurality of IP blocks for generating a transaction having a memory, a bus, a field value for distinguishing a virtual address and a physical address and transmitting the transaction to the bus, And an integrated input / output memory management unit for determining whether or not address conversion is to be performed on the transaction transferred from the bus according to the field value.

In addition, the system-on-chip may further include a controller for generating an address conversion signal for setting the field value.

In the embodiment, the field value is set to a value indicating that the address of the transaction is a physical address as a default value. The field value is set to a value indicating that the address of the transaction is a logical address in response to the address translation signal.

In the embodiment, the integrated input / output memory management unit converts the address of the transaction into a physical address if the field value is set to a value indicating that the address of the transaction is a logical address. On the other hand, the integrated input / output memory management unit bypasses the transaction if the field value is set to a value indicating that the address of the transaction is a physical address.

In an embodiment, the integrated input / output memory management unit determines whether the address conversion for the next transaction is to be performed during the address conversion for the transaction. And the integrated input / output memory management unit bypasses the next transaction during address conversion for the transaction if the field value is set to a value indicating that the address of the next transaction is a physical address.

In an embodiment, the bus uses the Advanced Extensible Interface (AXI) protocol.

A system-on-chip according to another embodiment of the present invention includes a plurality of IP blocks for generating a memory, a bus, and a transaction to transmit to the bus, a plurality of IP blocks connected between the memory and the bus, An integrated input / output memory management unit that performs address conversion, and a controller that provides transaction state information indicating whether the address of the transaction is a virtual address or a physical address to the integrated input / output memory management unit. The transaction has an IP ID field value for identifying the plurality of IP blocks.

In the embodiment, the integrated input / output memory management unit determines whether to convert the address for the transaction by referring to the transaction state information corresponding to the IP ID field value.

In an embodiment, the integrated input / output memory management unit converts an address of the transaction into a physical address when the address of the transaction is confirmed to be a virtual address through transaction state information corresponding to the IP ID field value. On the other hand, the integrated input / output memory management unit bypasses the transaction when the address of the transaction is determined to be a physical address through the transaction state information corresponding to the IP ID field value.

In an embodiment, the IP ID field value is defined by a topology between the plurality of IP blocks and the bus.

In an embodiment, the integrated input / output memory management unit includes a TLB (Translation Look-aside Buffer) for storing an address conversion table. The integrated input / output memory management unit performs address conversion for the transaction with reference to the address conversion table.

In addition, if the address translation table is not stored in the TLB, the integrated input / output memory management unit reads the address translation table from the memory, and then proceeds to address translation for the transaction.

According to the system on chip (SoC) according to the embodiment of the present invention, the number of input / output memory management units (IOMMU) is reduced, thereby reducing the design complexity and power consumption.

1 is a block diagram showing an SoC according to a first embodiment of the present invention.
2 is a flowchart illustrating an operation of the SoC according to the first embodiment of the present invention.
3 is a block diagram illustrating an SoC according to a second embodiment of the present invention.
4 is a table illustrating an IP ID field value used in the SoC according to the second embodiment of the present invention.
5 is a flowchart illustrating an operation of the SoC according to the second embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings, so that those skilled in the art can easily carry out the technical idea of the present invention.

A system on chip (hereinafter referred to as SoC) according to an embodiment of the present invention includes an Input / Output Memory Management Unit (hereinafter referred to as " IPCU ") located in an intellectual property (Hereinafter referred to as " IOMMU "), and integrates the IOMMU at the memory end. This can reduce the redundancy of the logic used to convert the virtual address to the physical address.

Since the integrated IOMMU is implemented at the memory end, virtual addresses and physical addresses are mixed as the addresses of transactions on the bus. Therefore, the integrated IOMMU converts the address of the transaction into a physical address only when the address of the transaction is a virtual address. On the other hand, the integrated IOMMU bypasses the transaction without address translation if the address of the transaction is a physical address.

1 is a block diagram showing an SoC according to a first embodiment of the present invention. 1, an SoC 100 according to a first embodiment of the present invention includes first to sixth IP blocks 111 to 116, first and second local buses 121 and 122, A system bus 123, an integrated IOMMU 130, an IOMMU controller 140, a CPU 150 and a memory 160.

The first to third IP blocks 111 to 113 transfer the transaction to the integrated IOMMU 130 through the first local bus 121 and the system bus 123. The fourth to sixth IP blocks 114 to 116 transfer the transaction to the integrated IOMMU 130 via the second local bus 122 and the system bus 123.

Here, it is assumed that the interface protocol applied to the first and second local buses 121 and 122 and the system bus 123 is AXI (Advanced Extensible Interface). Accordingly, the SoC 100 supports a multiple outstanding address function and a data interleaving function due to AXI. In particular, due to the multi-out standing address function, when a transaction for address information (hereinafter referred to as an address transaction) and a transaction for data information (hereinafter referred to as a data transaction) are provided, An address transaction for the transmission of the next data transaction may be sent.

The transaction transmitted from each of the IP blocks 111 to 116 includes a field value indicating whether the address is a virtual address or a physical address. The field value for distinguishing the virtual address and the physical address may be referred to differently depending on the type of the transaction. For example, a field value included in a transaction for write address information (hereinafter referred to as a write address transaction) is referred to as AWUSER. The field value included in the transaction for the read address information (hereinafter referred to as a read address transaction) is referred to as ARUSER.

AWUSER and ARUSER are set to 0 as default values, which assume that the address of the transaction is a physical address. On the other hand, if AWUSER and ARUSER are set to 1, it is assumed that the address of the transaction is a virtual address.

The integrated IOMMU 130 converts the virtual addresses used in the first to sixth IP blocks 111 to 116 into physical addresses. That is, the integrated IOMMU 130 maps the fragmented physical memory areas to consecutive virtual addresses. This allows effective memory space utilization even if physical memory areas are not designated as consecutive physical addresses. Thus, a wider memory space can be allocated to each IP block. For reference, a virtual address may be referred to as a device address or an I / O address.

Transactions of the first to third IP blocks 111 to 113 are transferred to the integrated IOMMU 130 via the first local bus 121 and the system bus 123. Transactions of the fourth to sixth IP blocks 114 to 116 are transferred to the integrated IOMMU 130 via the second local bus 122 and the system bus 123. Thereafter, the integrated IOMMU 130 performs address translation for the transactions transmitted through the buses 121 to 123 of the SoC 100. [ This means that the virtual address and the physical address can be mixed as the addresses of the transactions on the first and second local buses 121 and 122 and the system bus 123. [

Here, the integrated IOMMU 130 determines whether or not to perform address conversion according to AWUSER or ARUSER. The integrated IOMMU 130 converts the transaction address into a physical address when AWUSER or ARUSER indicates a virtual address (AWUSER / ARUSER = 1). Thereafter, the addressed transaction is transferred to the memory 160. On the other hand, the integrated IOMMU 130 bypasses the transaction when AWUSER or ARUSER indicates that it is a physical address (AWUSER / ARUSER = 0).

The integrated IOMMU 130 refers to an address translation table stored in a Translation Look-aside Buffer (TLB) for address translation. If the address translation table is not loaded in the TLB, the address translation table is read from the memory 160 before the address translation is performed.

The integrated IOMMU 130 can determine whether the next transaction is address-converted during the address conversion. If the integrated IOMMU 130 indicates that AWUSER or ARUSER for the next transaction is a physical address (AWUSER / ARUSER = 0), then the next transaction can be bypassed even during address translation for the previous transaction.

The IOMMU controller 140 generates an address conversion signal (ATS) for setting AWUSER or ARUSER in the transaction according to whether the address of the transactions transmitted from each of the IP blocks 111 to 116 is a virtual address or a physical address. At this time, AWUSER or ARUSER is set from 0 to 1 in response to the address conversion signal (ATS). As described above, since the AWUSER or ARUSER is set to 0 as a default value, the IOMMU controller 140 generates the address translation signal (ATS) only when the addresses of the transactions are logical addresses.

The IOMMU controller 140 may include a register 141 for storing transaction state information indicating whether an address of a transaction output from each of the IP blocks 111 to 116 is a virtual address or a physical address. Here, the transaction status information for each of the IP blocks 111 to 116 is provided from the CPU 150. [ Accordingly, the IOMMU controller 140 can determine whether to generate the address conversion signal (ATS) by referring to the transaction state information stored in the register 141.

The CPU 150 is connected to the system bus 123 and controls the overall operation of the SoC 100. The CPU 150 may include a register, a memory management unit (MMU), and the like, although not shown, as is well known. Here, the CPU 150 may be implemented based on an ARM (Advanced RISC Machine) core.

The memory 160 stores data to be processed in the SoC 100. The memory 160 may include volatile memories such as static random access memory (SRAM), dynamic random access memory (DRAM), and synchronous dynamic random access memory (SDRAM). The memory 160 may be implemented as a ROM (Read Only Memory), a PROM (Programmable ROM), an EPROM (Electrically Programmable ROM), an EEPROM (Electrically Erasable and Programmable ROM), a flash memory, a PRAM RAM), RRAM (Resistive RAM), FRAM (Ferroelectric RAM), and the like.

Each area in the memory 160 is designated by a physical address. Accordingly, in order for the IP blocks using the virtual address to access the memory 160, the addresses of the IP blocks must be converted to physical addresses. In this regard, the virtual address used in the CPU 150 is address-converted by the MMU. On the other hand, the virtual addresses used in the first to sixth IP blocks 111 to 116 are address-converted by the integrated IOMMU 130. [

2 is a flowchart illustrating an operation of the SoC according to the first embodiment of the present invention. Referring to FIG. 2, a transaction is output from an IP block (step S110). At this time, the IOMMU controller 140 (see FIG. 1) determines whether or not the address conversion signal ATS is generated according to whether the transaction address is a virtual address or a physical address (step S120). The IOMMU controller 140 generates an address conversion signal (ATS) when the address of the transaction is a virtual address. On the other hand, the IOMMU controller 140 does not generate the address conversion signal (ATS) when the address of the transaction is a physical address.

As described above, it is assumed that AWUSER or ARUSER is set to 0 as a default value. AWUSER or ARUSER in the transaction is set from 0 to 1 in response to the address translation signal (ATS). This means that if no address translation signal (ATS) is generated, AWUSER or ARUSER is held at zero.

Thereafter, the transaction is transferred to the integrated IOMMU 130 (see FIG. 1) via the local and system buses. The integrated IOMMU 130 determines whether AWUSER or ARUSER is 0 or 1. If AWUSER or ARUSER is 1, the integrated IOMMU 130 converts the address of the transaction from the virtual address to the physical address (step S150). On the other hand, if the AWUSER or ARUSER is 0, the integrated IOMMU 130 bypasses the transaction (step S160).

As described above, the SoC according to the embodiment of the present invention implements the integrated IOMMU at the memory end, thereby reducing redundancy of logic used for address conversion. Also, the complexity and power consumption of the SoC can be reduced by design.

Since the integrated IOMMU is implemented at the memory end, the virtual and physical addresses are mixed as the addresses of the transactions on the bus. AWUSER or ARUSER defined by the AXI protocol is used as information indicating whether the addresses of the transactions are virtual addresses or physical addresses. The IOMMU controller generates an address translation signal to set the AWUSER or ARUSER in the transaction depending on whether the address of the transactions is a virtual address or a physical address. Then, the integrated IOMMU determines whether the address is converted by referring to AWUSER or ARUSER.

3 is a block diagram illustrating an SoC according to a second embodiment of the present invention. Referring to FIG. 3, the SoC 200 according to the second embodiment of the present invention includes first to sixth IP blocks 211 to 216, first and second local buses 221 and 222, A system bus 223, an integrated IOMMU 230, an IOMMU controller 240, a CPU 250 and a memory 260.

The first to third IP blocks 211 to 213 transfer the transaction to the integrated IOMMU 230 through the first local bus 221 and the system bus 223. The fourth to sixth IP blocks 214 to 216 transfer the transaction to the integrated IOMMU 230 via the second local bus 222 and the system bus 223. The first to sixth IP blocks 211 to 216, the first and second local buses 221 and 222, and the system bus 223 have already been described with reference to FIG. Therefore, a duplicate description thereof will be omitted below.

The integrated IOMMU 230 converts the virtual addresses used in the first to sixth IP blocks 211 to 216 into physical addresses. That is, the integrated IOMMU 230 performs address conversion for the transactions transmitted through the buses 221 to 223 of the SoC 200. [ This means that the virtual address and the physical address can be mixed as the addresses of the transactions on the first and second local buses 221 and 222 and the system bus 223.

The integrated IOMMU 230 determines whether to convert the addresses for transactions by referring to the IP ID field value (IP_ID) in the transactions and the transaction state information (SI) provided from the IOMMU controller 240.

4 is a table illustrating an IP ID field value used in the SoC according to the second embodiment of the present invention. Referring to FIGS. 3 and 4, the IP ID field value IP_ID has a different value for distinguishing the first to sixth IP blocks 211 to 216. That is, referring to the IP ID field value (IP_ID), it is possible to know from which IP the transactions are transferred. For reference, the IP ID field value (IP_ID) can be defined by the AXI protocol.

The IP ID field value IP_ID may be defined by a topology between the IP blocks 211 to 216 and the buses 221 to 223. For example, the first and second bits of the IP ID field value (IP_ID) may be defined by a topology for the system bus 223. The first bit of the IP ID field value IP_ID is set to 1 to indicate the IP block carrying the transactions through the first node SN1 of the system bus 223. [ The second bit of the IP ID field value IP_ID is set to 1 to indicate the IP block carrying the transactions through the second node SN2 of the system bus 223. [

The third to fifth bits of the IP ID field value IP_ID may be defined by the topology for the local buses 221 and 222. [ The third bit of the IP ID field value IP_ID is set to 1 to indicate the IP block carrying the transactions through the first node L1_N1 of the first local bus 221. [ The fourth bit of the IP ID field value IP_ID is set to 1 to indicate the IP block carrying the transactions through the second node L1_N2 of the first local bus 221. [ The fifth bit of the IP ID field value IP_ID is set to 1 to indicate the IP block carrying the transactions through the third node L1_N3 of the first local bus 221. [

In this way, the third bit of the IP ID field value (IP_ID) is set to 1 to indicate the IP block carrying the transactions through the first node (L2_N1) of the second local bus 222. The fourth bit of the IP ID field value IP_ID is set to 1 to indicate the IP block carrying the transactions through the second node L2_N2 of the second local bus 222. [ The fifth bit of the IP ID field value IP_ID is set to 1 to indicate the IP block carrying the transactions through the third node L2_N3 of the second local bus 222. [

Referring back to FIG. 3, the integrated IOMMU 230 determines whether the address of the corresponding transaction is a virtual address or a physical address through the transaction state information (SI) corresponding to the IP ID field value (IP_ID) in the transferred transaction . The integrated IOMMU 230 performs address translation if the address of the transaction is a virtual address. On the other hand, the integrated IOMMU 230 bypasses the transaction if the address of the transaction is a physical address.

The integrated IOMMU 230 refers to the address translation table stored in the TLB for address translation. If the address translation table is not loaded in the TLB, the address translation table is read from the memory 260 before the address translation is performed.

The IOMMU controller 240 may include a register 241 for storing transaction state information SI indicating whether the address of the transactions output from each of the IP blocks 211 to 216 is a virtual address or a physical address . Here, the transaction state information SI for each of the IP blocks 211 to 216 is provided from the CPU 250. IOMMU controller 240 provides transaction state information (SI) corresponding to the IP ID field value (IP_ID) to integrated IOMMU 230.

The CPU 250 and the memory 260 have already been described with reference to Fig. Therefore, a duplicate description thereof will be omitted below.

5 is a flowchart illustrating an operation of the SoC according to the second embodiment of the present invention. Referring to FIG. 5, a transaction is output from an IP block (step S210). At this time, the integrated IOMMU 230 (see FIG. 1) confirms the transaction state information SI corresponding to the IP ID field value (IP_ID) in the transaction (step S220). As mentioned above, the transaction state information SI is provided from the IOMMU controller 240 (see FIG. 1).

The integrated IOMMU 230 determines whether the address of the corresponding transaction is a virtual address or a physical address through the transaction state information SI (step S230). Thereafter, the integrated IOMMU 230 performs address translation if the address of the transaction is a virtual address (step S240). On the other hand, the integrated IOMMU 130 bypasses the transaction if the address of the transaction is a physical address (step S250).

As described above, the SoC according to the embodiment of the present invention implements the integrated IOMMU at the memory end, thereby reducing redundancy of logic used for address conversion. Also, the complexity and power consumption of the SoC can be reduced by design.

Since the integrated IOMMU is implemented at the memory end, the virtual and physical addresses are mixed as the addresses of the transactions on the bus. The integrated IOMMU determines whether to convert the address by referring to the IP ID field value (IP_ID) and the corresponding transaction state information.

It will be apparent to those skilled in the art that the structure of the present invention can be variously modified or changed without departing from the scope or spirit of the present invention. In view of the foregoing, it is intended that the present invention cover the modifications and variations of this invention provided they fall within the scope of the following claims and equivalents.

100: System on Chip (SoC) 111: IP block
121, 122: local bus 123: system bus
130: Integrated IOMMU 140: IOMMU controller
150: CPU 160: Memory

Claims (20)

A central processing unit;
Memory;
A system bus including first and second buses;
And a second bus connected to the first bus or the second bus for generating a transaction including a field value for distinguishing an IP ID field value and a virtual address from a physical address and transmitting the transaction to the first bus or the second bus IP blocks;
An integrated input / output memory management unit coupled between the memory and the system bus, the integrated input / output memory management unit determining whether address conversion is to be performed on the transaction transferred from the system bus in accordance with the field value; And
And a controller for generating an address conversion signal for setting the field value based on the transaction state information provided from the central processing unit,
Wherein the IP ID field value indicates whether the transaction was transmitted via the first bus or the second bus,
Wherein the transaction state information indicates whether the address of the transaction is a virtual address or a physical address. The method according to claim 1,
Wherein the integrated input / output memory management unit discontinuously maps the physical memory areas of the memory to a plurality of virtual addresses. The method according to claim 1,
And the integrated input / output memory management unit converts the address of the transaction into a physical address if the field value is set to a value indicating that the address of the transaction is a virtual address. The method according to claim 1,
And the integrated input / output memory management unit bypasses the transaction if the field value is set to a value indicating that the address of the transaction is a physical address. The method according to claim 1,
Wherein the integrated input / output memory management unit determines whether address conversion is to be performed for the next transaction during address conversion for the transaction. 6. The method of claim 5,
The integrated input / output memory management unit bypasses the next transaction during address translation for the transaction if the field value is set to a value indicating that the address of the next transaction is a physical address. The method according to claim 1,
Wherein the field value is set to a value indicating that the address of the transaction is a physical address as a default value. 8. The method of claim 7,
Wherein the field value is set to a value indicating that the address of the transaction is a virtual address based on the address translation signal. The method according to claim 1,
Further comprising a central processing unit for providing transaction state information,
Wherein the controller determines whether to generate the address translation signal based on the transaction state information, and includes a register for storing the transaction state information. The method according to claim 1,
Wherein the memory access of the plurality of IP blocks is managed by the integrated input / output memory management unit, and the memory access of the central processing unit is managed by a memory management unit included in the central processing unit. A central processing unit;
Memory;
A system bus including first and second buses;
A plurality of IP blocks connected to the first bus or the second bus, the plurality of IP blocks generating and transmitting a transaction to the first bus or the second bus;
An integrated input / output memory management unit, connected between the memory and the system bus, for performing address translation for the transaction transferred from the system bus; And
And a controller for providing the integrated IO memory management unit with transaction state information indicating whether the address of the transaction is a virtual address or a physical address,
Wherein the transaction comprises an IP ID field value indicating whether the transaction was sent via the first bus or the second bus,
Wherein the transaction state information is provided from the central processing unit and stored in the controller. 12. The method of claim 11,
Wherein the integrated input / output memory management unit determines whether an address conversion is to be performed on the transaction by referring to the transaction state information corresponding to the IP ID field value. 12. The method of claim 11,
Wherein the integrated input / output memory management unit converts an address of the transaction into a physical address when the address of the transaction is determined to be a virtual address through transaction state information corresponding to the IP ID field value. 12. The method of claim 11,
Wherein the integrated input / output memory management unit bypasses the transaction when the address of the transaction is determined to be a physical address through the transaction state information corresponding to the IP ID field value. 12. The method of claim 11,
Wherein the IP ID field value is defined by a topology between the plurality of IP blocks and the system bus. 12. The method of claim 11,
Wherein the integrated input / output memory management unit includes a Translation Look-aside Buffer (TLB) for storing an address translation table. 17. The method of claim 16,
And the integrated input / output memory management unit performs address conversion for the transaction with reference to the address conversion table. 17. The method of claim 16,
And the integrated input / output memory management unit reads the address translation table from the memory if the address translation table is not stored in the TLB, and then proceeds to address translation for the transaction. A system-on-chip transaction management method comprising a memory and a plurality of IP blocks, the method comprising:
Outputting a transaction via the first bus or the second bus from one of the plurality of IP blocks connected to a first bus or a second bus;
An IP ID field value indicating whether the transaction was transmitted via the first bus or the second bus and a field value indicating whether the address of the transaction is a virtual address or a physical address, A step provided together;
Providing an address translation signal for setting the field value based on transaction state information provided from a central processing unit;
Setting the field value to a first value or a second value based on the address conversion signal;
Receiving the transaction, the IP ID field value, and the field value through an integrated IO memory management unit connected to an input end of the memory; And
And determining whether to switch the address according to the field value by the integrated input / output memory management unit,
The integrated input / output memory management unit switches the address of the transaction when the field value is the first value, and bypasses the address of the transaction when the field value is the second value,
Wherein the transaction state information indicates whether the address of the transaction is a virtual address or a physical address. 20. The method of claim 19,
Wherein the first value indicates that the address of the transaction is a virtual address and the second value indicates that the address of the transaction is a physical address.

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