KR101770740B1 - Seeker and method for compensating range walk - Google Patents

Abstract

Disclosed are a seeker capable of compensating for a range walk and a range walk compensation method thereof. The seeker according to the present invention includes a receiver for outputting an intermediate frequency signal by downwardly converting a received signal applied through an antenna and a signal processor for receiving a system clock of a preset frequency, dividing the system clock, generating a plurality of clock signals by delay of a preset time interval, selecting one of the generated clock signals as an ADC clock signal according to a moving speed, sampling the intermediate frequency signal in response to the selected ADC clock signal to be converted into a digital signal, integrating the digital signal, and determining the location of a target by analyzing the integrated digital signal. Accordingly, the present invention can prevent the range walk.

Description

TECHNICAL FIELD [0001] The present invention relates to an explorer capable of compensating for a range work,

Field of the Invention [0002] The present invention relates to a searcher, and more particularly, to a searcher capable of compensating a range work and a range work compensation method thereof.

The simplest way for a seeker to detect a target by detecting a received signal reflected by the target is to detect a target with a low target or a target with a low radar cross section (RCS) Thereby increasing the strength of the transmitted signal. However, increasing the transmit signal strength of the searcher requires a very large amount of power in a hardware manner. In addition, since the internal components of the searcher must be stably maintained in a high-output transmission signal, large-sized high-priced equipment is required. Therefore, in order to extend the target detection distance of the searcher provided in the moving object, a method different from the method of increasing the intensity of the transmitted signal is needed.

A software approach has been proposed that does not require high power and improves the signal processing method to detect distant or low RCS targets. The software-in method increases the signal-to-noise ratio by integrating the received signal so that the target can be detected even in a weak signal component in the received signal. Therefore, even if the intensity of the transmitted signal is not increased, It can detect.

FIG. 1 is a diagram for explaining a concept of a method for improving detection performance using a received signal integration method.

FIG. 1 shows a received signal when the searcher detects a target moving at a fixed position. As the target moves, the time t at which the received signal reaches the searcher gradually becomes shorter. Since the seeker computes the distance from the target based on the time from when the transmitted signal is emitted until the received signal is received, the distance R can be seen to be shortened. In FIG. 1, a plurality of received signals are clearly distinguished for the sake of understanding. However, in case of a real target or a target having a low RCS, the intensity of the received signal is very weak. Therefore, it is difficult to detect a target with only an individual received signal.

As shown in FIG. 1, a software method repeatedly radiates a transmission signal of a pulse waveform, receives and reflects a plurality of reception signals reflected on a target, and increases a signal-to-noise ratio. By integrating a plurality of received signals, the signal component in the received signal is increased by an integer multiple, while the noise is increased by the square root to obtain the same effect as increasing the signal intensity.

Equation 1 is a simplified formula for calculating the intensity of the integrated received signal.

Where P _avg is the average transmit power, G is the antenna gain, σ is the target RCS, A _e is the effective antenna area, t _int is the integration time, and R is the distance.

As shown in Equation (1), as the integration time increases, that is, as the number of integrated received signals increases, the intensity of the integrated received signal increases.

2 is a view for explaining a range work.

When at least one of the searcher or the target moves, and the relative speed between the searcher and the target is fast, the peak of the received signal integrated in the range bin or range cell, which distinguishes the distance to the target, And a range walk is generated that moves to a different range bin.

Referring to FIG. 2, individual received signals are distributed over 4 to 5 range bins, while signals obtained by integrating a plurality of received signals are distributed over 8 or more range bins. And the exact current position of the target can be ascertained in the range bin where the peak of the last received signal in the top figure is present. Nevertheless, as shown in the lower diagram, a peak in a received signal in which a plurality of received signals are integrated exists in a range bin different from the peak of the last received signal.

Therefore, a distance information error occurs in which the distances to the actual target and the distances obtained by analyzing the integrated received signal are different from each other, as well as a loss to the signal-to-noise ratio occurs. Range work must be compensated because the search performance of the explorer is greatly degraded. Currently, searchers check all received signals in order to solve the range work problem and process it by software so that the range bin of the integrated received signal changes when the peak of the received signal goes to another range bin.

However, it is very difficult to detect the peaks of the individual reception signals in a manner that the integration method itself uses weak individual received signals. That is, there is a limit to a method of detecting a peak of a received signal to solve a range work problem.

Korean Patent Laid-Open No. 10-2016-0127372 (published Nov. 11, 2016)

An object of the present invention is to provide a searcher capable of compensating for a range work.

Another object of the present invention is to provide a range work compensation method of a searcher for achieving the above object.

According to an aspect of the present invention, there is provided a searcher capable of compensating a range work, comprising: a receiver for frequency downconverting a received signal applied through an antenna and outputting an intermediate frequency signal; And generating a plurality of clock signals by delaying at predetermined time intervals and selecting one of the plurality of generated clock signals as an ADC clock signal according to the moving speed, A signal processor for sampling the intermediate frequency signal in response to the ADC clock signal, converting the sampled intermediate frequency signal into a digital signal and integrating the digital signal, and analyzing the integrated digital signal to determine a position of the target; .

Wherein the signal processor divides and delays the system clock to generate the plurality of clock signals and outputs a predetermined one of the plurality of clock signals as a fixed clock signal, A clock shifter for selecting one of the clock signals as the ADC clock signal and outputting the selected clock signal; An AD converter for receiving and sampling the intermediate frequency signal in response to the ADC clock signal and outputting the digital signal; An integrator for latching the digital signal output from the AD converter, integrating the latched digital signal, re-converting the latched digital signal into a digital signal of a type specified by the signal processor, and transmitting the integrated digital signal to the signal processor; And a controller for receiving the movement speed information from the system in which the searcher is mounted to discriminate the movement speed of the searcher, generate the clock selection signal in response to the determined movement speed, analyze the integrated digital signal, A signal processing unit for determining a position of a target; And a control unit.

Wherein the signal processor is operable to generate the clock selection signal based on the moving speed of the searcher if the target is not detected and to generate the clock selection signal based on the relative speed between the searcher and the target when the target is detected, .

Wherein the clock shifter receives the system clock and divides the system clock to generate a reference clock signal having a frequency lower than the system clock; A clock delayer for receiving the reference clock signal and generating a plurality of clock signals by a predetermined time unit; And outputting a predetermined one of the plurality of clock signals as a fixed clock signal and outputting an ADC clock signal for selecting and outputting one of the plurality of clock signals as the ADC clock signal in response to the clock selection signal, Selector; And a control unit.

Wherein the integrator comprises: a first latch unit responsive to the fixed clock signal applied from the ADC clock selector for latching the digital signal output from the AD converter; A second latch unit responsive to the ADC clock signal applied from the ADC clock selector for receiving and latching the digital signal latched in the first latch unit; And a digital-to-digital converter for receiving the digital signal latched in the second latch unit and performing digital-to-digital conversion to generate the integrated digital signal; And a control unit.

Wherein the integrator receives the integrated digital signal and removes noise generated in the digital conversion process and transmits the noise to the signal processor; And further comprising:

Wherein the signal processor is configured to generate and output the clock selection signal before a start of a next reception interval after the end of a reception interval in which the searcher receives the reception signal to prevent jittering from occurring .

Wherein the searcher comprises: a transmitter that emits a signal of a predetermined PRF waveform under the control of the signal processor; And further comprising:

According to another aspect of the present invention, there is provided a method of compensating a range work of a searcher, the method comprising: receiving a system clock of a predetermined frequency, dividing the frequency of the system clock, and generating a plurality of clock signals by a predetermined time interval; ; The signal processor generating a clock selection signal based on the moving speed of the searcher and selecting one of the plurality of clock signals as an ADC clock signal in response to the clock selection signal; The signal processor frequency-downconverts the received signal applied through the antenna in response to the ADC clock signal, converts the received intermediate frequency signal into a digital signal; Integrating the digital signal to generate an integral digital signal; Analyzing the integrated digital signal to determine a position of the target; And varying the clock selection signal based on a relative speed between the searcher and the target; .

Therefore, the searcher capable of compensating the range work of the present invention and its range work compensation method are based on the speed of movement of the searcher until the target is detected, and when the target is searched, By varying the clock signal driving the AD converter performing the digital conversion, the AD converter can sample almost the same position in the waveform of the plurality of received signals even when the distance from the target is changed, have.

FIG. 1 is a diagram for explaining a concept of a method for improving detection performance using a received signal integration method.
2 is a view for explaining a range work.
3 is a diagram illustrating a configuration of a searcher according to an embodiment of the present invention.
FIG. 4 is a detailed block diagram of the signal processor of FIG. 3. FIG.
5 is a diagram for explaining a difference in a method of sampling an intermediate frequency signal by an AD converter in the present invention and an existing searcher.
6 illustrates a range work compensation method of a searcher according to an embodiment of the present invention.

In order to fully understand the present invention, operational advantages of the present invention, and objects achieved by the practice of the present invention, reference should be made to the accompanying drawings and the accompanying drawings which illustrate preferred embodiments of the present invention.

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, the present invention will be described in detail with reference to the preferred embodiments of the present invention with reference to the accompanying drawings. However, the present invention can be implemented in various different forms, and is not limited to the embodiments described. In order to clearly describe the present invention, parts that are not related to the description are omitted, and the same reference numerals in the drawings denote the same members.

Throughout the specification, when an element is referred to as "including" an element, it does not exclude other elements unless specifically stated to the contrary. The terms "part", "unit", "module", "block", and the like described in the specification mean units for processing at least one function or operation, And a combination of software.

3 is a diagram illustrating a configuration of a searcher according to an embodiment of the present invention.

Referring to FIG. 3, the searcher of the present invention includes a signal processor 100 and a receiver 200.

The receiver 200 converts a received signal applied through an antenna (not shown) into a signal that can be interpreted by the signal processor 100. The receiver 200 frequency downconverts the received signal, converts it into an intermediate frequency signal of a predetermined frequency band, and transmits the intermediate frequency signal to the signal processor 100. At this time, when the antenna has a plurality of reception paths such as a monopulse radar, the receiver 200 generates a sum channel signal? And a difference channel signal? By combining the reception signals according to the arrangement form of each reception path , And then to the signal processor (100). The difference channel signal Δ can be separately applied to the high angle channel signal ΔEL and the azimuth difference channel signal ΔAZ. That is, the receiver 200 down-converts at least one received signal according to the type of the searcher, and converts the at least one received signal into a predetermined method to transmit at least one intermediate frequency signal to the signal processor 100.

The signal processor 100 includes an oscillator 110, an AD converter 130, an integrator 140 and a signal processor 150 to convert at least one intermediate frequency signal applied from the receiver 200 into a digital signal (SNR) is improved by integration (accumulation), and the position of the target is determined by analyzing the signal with improved SNR. Since the existing signal processor also converts the intermediate frequency signal into a digital signal and integrates it to determine the position of the target, the basic operation of the signal processor 100 of the present invention is also the same as that of the existing signal processor.

However, the signal processor 100 of the present invention generates a plurality of clock signals delayed in phase with different time phases by providing a clock shifter 120 between the oscillator 110 and the AD converter 130, 130 are generated by sampling the intermediate frequency signal using a plurality of generated clock signals, and converting and integrating the digital signal to compensate the range work.

Referring to FIG. 3, the operation of the signal processor 100 will be described. First, the oscillator 110 generates and outputs a system clock CLK_sys having a preset frequency (for example, 200 MHz). The clock shifter 120 receives a system clock CLK_sys and generates a plurality of clock signals (for example, 20 clock signals) having frequencies lower than the frequency of the system clock CLK_sys CLK). The clock signal to be transmitted to the AD converter 130 and the clock signal to be transmitted to the integrator 140 are separately selected and transmitted from the plurality of clock signals CLK to the AD converter 130 under the control of the signal processing unit 150.

The clock signal CLK transmitted to the AD converter 130 by the clock shifter 120 is referred to as an ADC clock signal CLK_adc and the ADC clock signal CLK_adc transmitted to the AD converter 130 may be varied have. On the other hand, the clock signal CLK to be transmitted to the integrator 140 is always applied with one clock signal CLK selected, which is referred to as a fixed clock signal CLK_fix. The fixed clock signal CLK_fix may be a clock signal whose phase is the most advanced among the plurality of clock signals CLK generated by the clock shifter 120, that is, the clock signal with the shortest delay time may be selected as the fixed clock signal CLK_fix have.

The clock shifter 120 selects one of the plurality of clock signals CLK delayed with different delay times and transmits the clock signal to the AD converter 130 as the ADC clock signal CLK_adc, When the ADC clock signal CLK_adc is varied in accordance with a change in distance from the target, the AD converter 130 samples the applied at least one intermediate frequency signal at a similar waveform position and performs digital conversion can do.

The integrator 140 integrates the ADC clock signal CLK_adc and the fixed clock signal CLK_adc applied to the AD converter so that the AD converter 130 can compensate for the error caused by the operation of the delayed clock signal CLK in response to the variable clock signal CLK CLK_fix) and integrates them.

The integrator 140 transmits the integrated signal to the signal processing unit 150, and the signal processing unit 150 detects the target from the integrated signal and determines the position of the target.

In FIG. 3, the searcher includes the signal processor 100 and the receiver 200 because it is assumed that the searcher is applied to the semi-active guidance system. However, the searcher of the present invention may be applied to an active guidance system. In this case, a transmitter (not shown) may be further provided to radiate a transmission signal under the control of the signal processor 100.

In the above description, the signal processor 100 includes the oscillator 110 to generate the system clock CLK_sys. However, in some cases, the system clock CLK_sys may be received from other components of the system in which the searcher is installed It is possible. In this case, the oscillator 11 may be omitted.

FIG. 4 is a detailed block diagram of the signal processor of FIG. 3. FIG.

In FIG. 4, for convenience of explanation, the oscillator 110 is omitted, assuming that the searcher receives the system clock CLK_sys in a system having a searcher.

Referring to FIG. 4, the clock shifter 120 includes a divider DV, a clock delay DLY, and an ADC clock selector ADCC.

The frequency divider DV receives and distributes the system clock CLK_sys and generates a reference clock signal CLK_ref having a lower frequency than the system clock CLK_sys. The clock delayer DLY receives the reference clock signal CLK_ref from the divider DV and delays the applied reference clock signal CLK_ref by a different time delay in response to the system clock CLK_sys to generate a plurality of clock signals CLK). It is assumed that the reference clock signal CLK_ref having a clock delay DLY of 50 MHz is delayed by 5 ns in response to a system clock CLK_sys having a frequency of 200 MHz to output 20 clock signals CLK do.

The ADC clock selector ADCC selects one of the plurality of clock signals CLK applied from the clock delay DLY in response to the clock selection signal SEL applied from the signal processor 150, ADC clock signal CLK_adc to the AD converter 130 and the integrator 140 while transmitting the fixed clock signal CLK_fix to the integrator 140. [

In response to the ADC clock signal CLK_adc, the AD converter 130 samples at least one intermediate frequency signal applied from the receiver 200, converts the sampled intermediate frequency signal into a digital signal, and outputs the converted at least one digital signal to the integrator 140. [ .

The integrator 140 includes a first latch portion 141, a second latch portion 142, a digital-to-digital converter 143 and a filter portion 144.

The first latch 141 receives the same ADC clock signal CLK_adc as that applied from the ADC clock selector ADCC to the AD converter 130 and receives the ADC clock signal CLK_adc from the AD converter 130 in response to the ADC clock signal CLK_adc Latches at least one digital signal applied thereto. Receiving the ADC clock signal CLK_adc by the first latch unit 141 operates with the same clock signal as that of the AD converter 130 to stably accumulate at least one digital signal output from the AD converter 130 .

However, the integrator 140 and the signal processing unit 150 can not operate in response to the basically variable ADC clock signal CLK_adc. That is, the integrator 140 and the signal processor 150 must be configured to operate in response to the fixed clock signal CLK_fix, and thus it is difficult to stably utilize the digital signal latched in the first latch 141.

The present invention further includes a second latch unit 142 so that the second latch unit 142 latches the digital data latched in the first latch unit 141 again in response to the fixed clock signal CLK_fix The integrator 140, and the signal processor 150 can use the digital signal stably.

The DD converter 143 receives the digital signal latched in the second latch unit 142, integrates the signal, and converts the integrated signal into an integral digital signal that is easy to process in the signal processing unit 140.

The filter unit 144 receives the integral digital signal, removes noise generated in the digital conversion process, and transmits the noise to the signal processing unit 150. In some cases, the filter unit 144 may be omitted.

The signal processing unit 150 analyzes the integrated digital signal applied by the integrator 140 to detect the target and locates the target when the target is detected. The manner in which the signal processor 150 analyzes the integrated digital signal to determine the position of the target is a well-known technique and will not be described in detail here.

In the present invention, the signal processing unit 150 generates a clock selection signal SEL corresponding to the moving speed of the searcher and transmits it to the ADC clock selector (ADCC) until the search unit detects the target. When the target is detected, Generates a clock selection signal SEL corresponding to the relative speed between the target and the searcher, and transmits the clock selection signal SEL to the ADC clock selector ADCC.

Since the signal processing unit 150 can select the clock signal CLK to be applied to the AD converter 130 based on the relative speed with respect to the target, the AD converter 130 can generate a plurality of intermediate frequency signals It becomes possible to sample at almost the same waveform position. That is, the peak timing in the plurality of intermediate frequency signals continuously varies in proportion to the distance from the target, but the AD converter 130 can always sample nearly the same position in the waveform of the intermediate frequency signal. Therefore, since the integrated digital signals are superimposed and concentrated in a range similar to the case where one intermediate frequency signal is sampled, the range work is not widely distributed to a plurality of range bins, and the range work can be eliminated.

5 is a diagram for explaining a difference in a method of sampling an intermediate frequency signal by an AD converter in the present invention and an existing searcher.

In FIG. 5, (a) shows the manner in which the AD converter of the conventional searcher samples the intermediate frequency signal, and (b) shows the manner in which the AD converter 130 of the searcher according to the present invention samples the intermediate frequency signal.

As can be seen in (a), the AD converter of the conventional searcher receives a constant fixed clock signal and samples the intermediate frequency signal. Therefore, when at least one of the searcher or the target moves and the relative distance changes, the positions sampled in the intermediate frequency signal waveform are different from each other. (a), sampling is performed at the peak of the intermediate frequency signal, while sampling at the peak of the intermediate frequency signal is shown at the right side. Therefore, the distribution of the waveform in the range bin is enlarged.

On the other hand, in the case of the AD converter 130 of the present invention, the clock signal for determining the sampling timing of the AD converter 130 is applied to the ADC clock signal CLK_adc which varies according to the moving speed of the searcher or the relative speed with respect to the target . Therefore, as shown in the right figure, if the intermediate frequency signal is sampled using the ADC clock signal (CLK_adc2) at the present sampling time rather than the ADC clock signal (CLK_adc1) at the previous sampling time, It is possible to sample the same position in the waveform of the intermediate frequency signal, thereby preventing the waveform from spreading in the range bin. That is, the range work can be removed.

However, if the ADC clock signal CLK_adc is varied while the searcher is receiving the reception signal, a jittering phenomenon occurs. Therefore, the signal processor 150 preferably outputs a clock selection signal SEL for varying the ADC clock signal CLK_adc before the previous reception interval is completed and the next reception interval starts.

As described above, the frequency of the system clock (CLK_sys) is 200 MHz, and the clock shifter 120 generates a plurality of clocks having a time difference of 5 ns at a frequency of 50 MHz Assuming that the signal CLK is generated, a distance R corresponding to a time difference of 5 ns between the plurality of clock signals CLK is calculated as shown in Equation (2).

Referring to Equation (2), it can be seen that the target distance corresponding to an adjacent clock signal in which a 5 ns time difference occurs among a plurality of clock signals (CLK) is 0.75 m. Accordingly, the signal processor 150 calculates a distance change from the target in units of 0.75 m, and selects a clock signal CLK_adc different from the previously selected ADC clock signal CLK_adc in the plurality of clock signals CLK It is necessary to output the signal SEL.

The counter value N for the amount of change of the clock selection signal SEL to select the ADC clock signal CLK_adc may be calculated according to Equation (3).

However, shifting the ADC clock signal (CLK_adc) in a transmission period during which the target signal is not received means that the shift of the ADC clock signal (CLK_adc) is synchronized with PRF. However, the calculation result in Equation (3) may not be derived as an integer value. For example, the counter value N according to Equation (3) may be calculated to be 7.5.

The signal processing unit 150 may store the residual value after the decimal point in consideration of the case where the counter value N is not calculated as an integer, and add it to the next calculated counter value N to reflect it. For example, if the counter value N is continuously calculated to 7.5, the clock signal CLK after 7 counts is selected as the ADC clock signal CLK_adc after the transmission signal of the PRF type is radiated, The clock signal CLK after 8 counts can be selected as the ADC clock signal CLK_adc. The signal processing unit 150 can determine whether to change the range bin for the received signal corresponding to the count value N. [

6 illustrates a range work compensation method of a searcher according to an embodiment of the present invention.

6, the clock shifter 120 of the signal processor 100 of the searcher 100 receives the system clock CLK_sys and divides the frequency of the system clock CLK_sys, (For example, 5 ns) to generate a plurality of clock signals CLK having different phase differences at frequencies lower than the frequency of the system clock CLK_sys.

Meanwhile, the signal processing unit 150 determines the speed of the searcher (S20). The signal processing unit 150 can receive the moving speed information from a control unit (not shown) included in the device equipped with the searcher, and can determine the speed of the searcher. Based on the determined speed of the searcher, a clock selection signal SEL is generated (S30).

When the clock shifter 120 selects the ADC clock signal CLK_adc to be transmitted to the AD converter 130 among the plurality of clock signals CLK in response to the clock selection signal SEL, The signal is driven in response to the signal CLK_adc to frequency downconvert the received signal in the receiver 200, sample the transmitted intermediate frequency signal, and convert it into a digital signal (S40).

The integrator 140 receives and integrates the digital signal (S50). The integrator 140 first latches the digital signal converted by the AD converter 130 in response to the ADC clock signal CLK_adc and then outputs the fixed clock signal CLK_fix of the plurality of clock signals CLK And latches the first latched digital signal in response to the second latched digital data. The second latched digital data is digitally converted into a signal that is easy to process in the signal processor 150, and is output.

The signal processing unit 150 analyzes the digital signal output from the integrator 140 to determine whether a target is detected (S60). If the target is detected, the signal processor 150 analyzes the position and movement speed of the target and determines the relative speed with the searcher (S70).

The signal processor 150 generates the clock selection signal SEL again based on the determined relative speed and transmits the clock selection signal SEL to the clock shifter 120 so that the clock shifter 120 selects the AD The ADC clock signal CLK_adc to be transmitted to the converter 130 can be varied and selected.

The method according to the present invention can be implemented as a computer program stored in a medium for execution in a computer. Where the computer-readable medium can be any available media that can be accessed by a computer, and can also include both computer storage media. Computer storage media includes both volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data, ROM (Read Only Memory), ROM (Read Only Memory), RAM (Random Access Memory), CD (Compact Disk) -ROM, DVD (Digital Video Disk) -ROM, magnetic tape, floppy disk,

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is evident that many alternatives, modifications and variations will be apparent to those skilled in the art.

Accordingly, the true scope of the present invention should be determined by the technical idea of the appended claims.

Claims (12)

A receiver for frequency downconverting a received signal applied through an antenna and outputting an intermediate frequency signal; And
And generates a plurality of clock signals by delaying the clock signal at a predetermined time interval and outputs one of the generated plurality of clock signals in response to a clock selection signal varying in accordance with the movement speed, A signal processor for sampling the intermediate frequency signal in response to the selected ADC clock signal and converting the sampled intermediate frequency signal into a digital signal and integrating the digital signal and analyzing the integrated digital signal to determine the position of the target; Lt; / RTI >
A signal processor for determining the movement speed, generating a clock selection signal in response to the determined movement speed, analyzing and analyzing the integrated digital signal to determine a position of the target; Further comprising:
Wherein the signal processing unit generates the clock selection signal based on a relative speed with the target when the target is detected and generates the clock selection signal based on the moving speed if the target is not detected A navigator that can compensate for the range work. The apparatus of claim 1, wherein the signal processor
A plurality of clock signals, one of the plurality of clock signals is output as a fixed clock signal, and one of the plurality of clock signals is output in response to a clock selection signal, A clock shifter for selecting and outputting the clock signal of the ADC as the ADC clock signal;
An AD converter for receiving and sampling the intermediate frequency signal in response to the ADC clock signal and outputting the digital signal; And
An integrator for latching the digital signal output from the AD converter, integrating the latched digital signal, re-converting the latched digital signal into a digital signal of a type specified by the signal processor, and transmitting the integrated digital signal to the signal processor; Further comprising:
And analyzing the integral digital signal to determine the position of the target. delete The method of claim 2, wherein the clock shifter
A frequency divider for receiving and frequency dividing the system clock to generate a reference clock signal having a frequency lower than the system clock;
A clock delayer for receiving the reference clock signal and generating a plurality of clock signals by a predetermined time unit; And
An ADC clock selector for selecting one of the plurality of clock signals as the ADC clock signal in response to the clock selection signal and outputting the clock signal as the ADC clock signal in response to the clock selection signal, ; Wherein the range finder is capable of compensating for the range work. 5. The apparatus of claim 4, wherein the integrator
A first latch for latching the digital signal output from the AD converter in response to the fixed clock signal applied from the ADC clock selector;
A second latch unit responsive to the ADC clock signal applied from the ADC clock selector for receiving and latching the digital signal latched in the first latch unit; And
A digital-to-digital converter that receives the digital signal latched in the second latch unit and performs digital-to-digital conversion to generate the integrated digital signal; Wherein the range finder is capable of compensating for the range work. 6. The apparatus of claim 5, wherein the integrator
A filter unit which receives the integrated digital signal and removes noise generated in a digital conversion process and transmits the noise to the signal processing unit; Wherein the range finder is operable to compensate for the range walk. 3. The apparatus of claim 2, wherein the signal processing unit
Wherein the searcher generates and outputs the clock selection signal before the searcher starts the next reception interval after the end of the reception interval in which the searcher receives the reception signal to prevent jittering from occurring. A navigator that can do that. The apparatus of claim 1, wherein the searcher
A transmitter that emits a signal of a predetermined PRF waveform under the control of the signal processor; Wherein the range finder is operable to compensate for the range walk. A method of compensating a range work of a searcher,
Generating a plurality of clock signals by receiving a system clock of a predetermined frequency and dividing the signal clock by a predetermined time interval;
The signal processor generating a clock selection signal based on the moving speed of the searcher and selecting one of the plurality of clock signals as an ADC clock signal in response to the clock selection signal;
The signal processor frequency-downconverts the received signal applied through the antenna in response to the ADC clock signal, converts the received intermediate frequency signal into a digital signal;
Integrating the digital signal to generate an integral digital signal;
Analyzing the integrated digital signal to determine a position of the target; And
Varying the clock selection signal based on a relative speed between the searcher and the target; Wherein the range walks the search range. 10. The method of claim 9, wherein selecting the ADC clock signal comprises:
The signal processor generating the clock selection signal based on a moving speed of the searcher;
Outputting a predetermined one of the plurality of clock signals as a fixed clock signal; and
And selecting and outputting one of the plurality of clock signals as the ADC clock signal in response to the clock selection signal. 11. The method of claim 10, wherein generating the integral digital signal comprises:
First latching the digital signal in response to the fixed clock signal;
Secondarily latching the first latched digital signal in response to the ADC clock signal; And
And integrating the second latched digital signal and converting the digital signal into an integrated digital signal of a designated type. 11. The method of claim 10, wherein generating the plurality of clock signals comprises:
Generating a reference clock signal having a frequency lower than the system clock by applying the system clock and dividing the system clock; And
Generating the plurality of clock signals by delaying the reference clock signal by a predetermined time unit; And compensating the range work of the search range.

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