KR101731119B1 - Stereoscopic image display and driving method thereof - Google Patents

Abstract

A stereoscopic image display device includes a display panel for writing the left eye image data to pixels of the display panel during a data addressing time of an n-th (n is a positive integer) frame period, The light emission control pulse is input to the pixels during the light emission addressing time of the frame period. Wherein the stereoscopic image display apparatus writes the right-eye image data to pixels of the display panel during a data addressing time of an (n + 1) -th frame period, To the pixels. The pixels sequentially emit light in block units including a plurality of display lines so that the light emitting addressing time is smaller than the data addressing time within one frame period.

Description

TECHNICAL FIELD [0001] The present invention relates to a stereoscopic image display device,

The present invention relates to a stereoscopic image display device for sequentially emitting light and a driving method thereof.

The stereoscopic display is divided into a stereoscopic technique and an autostereoscopic technique.

The binocular parallax method uses parallax images of left and right eyes with large stereoscopic effects, and is divided into a glasses system and a non-glasses system. In the spectacle method, stereoscopic images are implemented using polarized glasses or shutter glasses by changing polarizing directions of right and left parallax images in a direct view type display device or a projector or displaying them in a time division manner. In the non-eyeglass system, stereoscopic images are realized by separating the optical axes of left and right parallax images using optical plates such as parallax barriers and lenticular lenses.

1 and 2 show an example of a spectacled stereoscopic image display apparatus and a driving method thereof.

Referring to FIGS. 1 and 2, the stereoscopic image display apparatus includes a display device 10 for displaying a left-eye image and a right-eye image in a time-division manner, and a shutter glasses 20. The shutter glasses 20 include a left-eye shutter and a right-eye shutter which are alternately opened and closed. The left and right eye shutters of the shutter glasses 20 are electrically controlled in the birefringence state of the liquid crystal.

In the case where the display device 10 is implemented as an organic light emitting display device such as an Organic Light Emitting Diode Display, the display device 10 can be driven in the same manner as in FIG. During the data addressing time, the data of the left eye image or the right eye image is sequentially written into the display element 10 in the form of a line by line. The data addressing time is allocated to the first half period of one frame period. Then, all the pixels of the display element simultaneously emit light with the brightness corresponding to the gradation value of the previously stored data voltage. The light emission period of the pixels is the second half period of one frame period.

The left eye shutter of the shutter eyeglasses 20 is opened when the left eye image data is emitted to the display element 10 and the right eye shutter of the shutter eyeglasses 20 is opened when the right eye image data is displayed on the display element 10. [ Therefore, the user wearing the shutter glasses 20 can see the left eye image and the right eye image alternately in a time-division manner through the shutter glasses, so that he / she can feel the binocular parallax and enjoy the stereoscopic image.

In the stereoscopic image display device as shown in FIGS. 1 and 2, since all the pixels of the display device emit light at the same time, the peak current of the display panel in which the pixels are formed increases rapidly. The surge in peak currents can lead to system malfunction, power supply line damage to power components and display panels, and electromagnetic interference (EMI).

In the conventional stereoscopic image display apparatus, the light emission time is a half or less of one frame period. The light emission time is fixed irrespective of the response delay time of the shutter glasses 20. In order to solve the problem of small light emission time, when the current density of the pixels is increased for luminance compensation, the lifetime of the display panel is shortened due to deterioration of the pixel element.

The present invention provides a stereoscopic image display device and a method of driving the same, which can prevent a surge in peak current due to the simultaneous emission of pixels, secure sufficient emission time, and extend the service life.

The stereoscopic image display device of the present invention includes scan lines of a first scan group supplied with a scan pulse synchronized with the data voltage, scan lines of a second scan group supplied with a light emission control pulse, And pixels for charging the data in response to the scan pulses and emitting light in response to the emission control pulses, thereby displaying the left eye image data and the right eye image data in a time division manner, and the pixels are divided into blocks each including a plurality of display lines A display panel sequentially emitting light; And shutter glasses including a left-eye shutter and a right-eye shutter which are electronically controlled and alternately opened and closed.

The method of driving the stereoscopic image display apparatus includes the steps of writing the left eye image data to pixels of the display panel during a data addressing time of an n-th (n is a positive integer) frame period; Inputting the emission control pulses to the pixels on a block-by-block basis during an emission addressing time of the n-th frame period; Writing the right eye image data to pixels of the display panel during a data addressing time of an (n + 1) -th frame period; And inputting the emission control pulses inputted during the emission addressing time of the (n + 1) th frame period to the pixels in units of blocks, wherein the emission addressing time is shorter than the data addressing time small.

The present invention can sequentially emit pixels on a line-by-line basis or block-by-block basis, thereby preventing a surge in a peak current due to the simultaneous emission of pixels, and securing a sufficiently long emission time of each pixel. Furthermore, according to the present invention, the peak current can be minimized to prolong the lifetime of the display panel, and the brightness of the display image can be increased and the luminance uniformity can be increased over the entire display screen.

1 is a diagram showing an example of a stereoscopic image display apparatus of a spectacles type.
2 is a waveform diagram illustrating a driving method of the stereoscopic image display apparatus shown in FIG.
3 is a view illustrating a stereoscopic image display apparatus according to an embodiment of the present invention.
4 is a waveform diagram illustrating a method of driving a display panel according to a first embodiment of the present invention.
5 is a timing diagram illustrating an example of 240 Hz frame frequency driving of the stereoscopic image display apparatus according to the first embodiment of the present invention.
6 is a timing chart showing an example of driving a frame frequency of 120 Hz in the stereoscopic image display device according to the first embodiment of the present invention.
7 is an equivalent circuit diagram showing an example of a pixel of the display panel shown in Fig.
8 is a waveform diagram showing driving signals of the pixel shown in FIG.
9 is a waveform diagram showing an example of a scan pulse and a light emission control pulse.
10 is a diagram showing an example in which the screen of the display panel is divided into ten blocks.
11 is a waveform diagram showing an example of a scan pulse and a light emission control pulse of a display panel divided into a plurality of blocks as shown in FIG.
12 is a waveform diagram showing a method of driving a display panel according to a second embodiment of the present invention.
FIG. 13 is a timing chart illustrating an example of 240 Hz frame frequency driving of the stereoscopic image display device according to the second embodiment of the present invention.
14 is a timing chart showing an example of driving a frame frequency of 120 Hz in the stereoscopic image display device according to the second embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Like reference numerals throughout the specification denote substantially identical components. In the following description, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

The component name used in the following description may be selected in consideration of easiness of specification, and may be different from the actual product name.

Referring to FIG. 3, the stereoscopic image display apparatus according to the embodiment of the present invention includes a display element and shutter glasses 120.

The shutter glasses 120 include an electronically controlled left eye shutter ST _L and a right eye shutter ST _R. Each of the left eye shutter ST _L and the right eye shutter ST _R includes a first transparent substrate, a first transparent electrode formed on the first transparent substrate, a second transparent substrate, a second transparent electrode formed on the second transparent substrate, 1 and a liquid crystal layer sandwiched on the second transparent substrate, and the like. A reference voltage is supplied to the first transparent electrode and an ON / OFF voltage is supplied to the second transparent electrode. Each of the left eye shutter ST _L and the right eye shutter ST _R passes light incident from the display panel 100 when the ON voltage is supplied to the second transparent electrode while an OFF voltage is supplied to the second transparent electrode The display panel 100 is turned off.

The display element includes a display panel 100, a display panel drive circuit, and a control circuit. Hereinafter, the display panel 100 may be embodied as an organic light emitting diode display panel. The display panel 100 includes data lines DL, scan lines SL intersecting the data lines DL and pixel regions SL defined by the data lines DL and the scan lines SL. Lt; RTI ID = 0.0 > a < / RTI > The display panel 100 may further include a power supply line PL for supplying a power supply voltage to the pixels, as shown in FIG.

The display panel driving circuit includes a data driver 102 and a scan driver 104 for driving the data lines DL and the scan lines SL for data addressing and light addressing of the display panel 100. The control circuit includes a timing controller 106 and a host system 108.

The data driver 102 converts the digital video data RGB into data voltages Data as shown in FIGS. 7 and 8 under the control of the timing controller 106 and supplies the data voltages to the data lines DL. The scan driver 104 sequentially supplies the scan pulses Scan and the emission control pulses Em as shown in FIGS. 7 and 8 to the scan lines SL under the control of the timing controller 106. The scan lines SL are divided into scan lines in a first scan group in which scan pulses are sequentially supplied and scan lines in a second scan group in which emission control pulses Em are sequentially supplied. The scan driver 104 includes a first shift register for sequentially supplying a scan pulse synchronized with the data voltage Data to the scan lines of the first scan group and a second shift register for sequentially supplying the emission control pulse Em to the second scan And a second shift register for sequentially supplying the scan lines to the scan lines of the group. The first shift register starts generating a scan pulse (scan) in response to the first start pulse from the timing controller 106. The second shift register starts generating the light emission control pulse Em in response to the second start pulse from the timing controller 106. [

The timing controller 106 supplies digital video data (RGB) to the data driver 102. The timing controller 106 controls the data driver 102 and the data driver 104 based on the timing signals inputted from the host system 108 such as the vertical / horizontal synchronizing signals Vsync and Hsync, the clock signal CLK and the data enable signal DE. And generates timing control signals for controlling the operation timing of the scan driver 104. [ The timing controller 106 can multiply the frame frequency by N (N is a positive integer of 2 or more) of the input frame frequency and control the display panel driving circuit on the basis of the multiplied frame frequency. The input frame frequency is 50 Hz in the PAL (Phase Alternate Line) method and 60 Hz in the NTSC (National Television Standards Committee) method.

The host system 108 performs graphic processing on data of an input image input from an external device (not shown) or a broadcast signal receiving circuit, and outputs the image data Converts the resolution. In addition, the host system 108 transmits the timing signals to the timing controller 106 along with the digital video data output from the scaler. The host system 108 may transmit a mode signal for distinguishing the 2D mode and the 3D mode to the timing controller 106. [

The host system 108 is connected to the user input device 110 and the shutter control signal transmitter 112. The user can select the 2D mode and the 3D mode through the user input device 110. The user input device 110 includes a touch screen, an on screen display (OSD), a keyboard, a mouse, a remote controller, and the like, which are mounted on or embedded on the display panel 100. The host system 108 may switch the current operation mode to the 2D mode or the 3D mode in response to the user data input through the user input device 110 or switch the operation mode based on the analysis result of the input image .

Shutter control signal transmitting unit 112 is a shutter the shutter control signal for opening and closing a left eye shutter (ST _L) and the right eye shutter (ST _R) of the shutter glasses 120 under the control of the host system 108 through a wired / wireless interface And transmits it to the control signal receiving unit 114. The shutter control signal receiving unit 114 is incorporated in the shutter glasses 120. The shutter control signal receiving unit 114 receives the shutter control signal through the wired / wireless interface and transmits the shutter control signal to the shutter glasses 120 in synchronization with the left eye image and the right eye image displayed on the display panel 100 in response to the shutter control signal. It opens and closes a left-eye shutter _(L ST) and the right-eye shutter alternately (ST _R).

4 is a waveform diagram showing a driving method of the display panel 100 according to the first embodiment of the present invention.

In Fig. 4, P4 represents one frame period.

And P1 is an on / off switching time (on / off switching time) of the shutter glasses 120. The ON / OFF switching time of the shutter glasses 120 is controlled by the liquid crystal response delay time so that the crosstalk between the left eye image and the right eye image does not occur due to the liquid crystal response delay time of the left eye shutter ST _L and the right eye shutter ST _R Time. The on / off switching time of the shutter glasses 120 includes an on switching time and an off switching time. The on-switching time of the shutter glasses 120 is the rising response delay time of the liquid crystal in which the transmittance rises with the liquid crystal molecules of the shutter glasses 120 rising. The off- is the falling response time of the liquid crystal in which the transmittance is lowered. Generally, the on-switching time of the shutter glasses 120 is approximately 3 ms, and the off-switching time of the shutter glasses 120 is approximately 1 ms.

The ON / OFF switching time of the shutter glasses 120 is switched between the end of light emission of the last display line of the n-th frame period Fn and the initial first display line light emission start point of the (n + 1) exist.

P2 is an emission addressing time required for applying the emission control pulse to all the pixels. During the light emitting addressing time, the emission control pulses are applied to the scan lines of the second scan group from the first display line LN1 to the last display line LNL of the display panel in a line by line form, Are sequentially applied in a block by block form.

P3 is a data addressing time required for data to be written to pixels of all the display lines LN1 to LNL of the display panel 100. [ During the data addressing time, the data voltages are applied to the data lines. During the data addressing time, the scan pulses are sequentially applied to the scan lines of the first scan group in a line-by-line manner from the first display line LN1 to the last display line LNL of the display panel in synchronization with the data voltage do.

The time between the pixel data writing point and the light emission start point differs depending on the positions of the pixels. For example, due to the difference between the data addressing speed and the light emission addressing speed, the time between the data write-in time and the light emission start time in the first display line LN1 located at the top of the display panel 100 is the last display parameter LNL). ≪ / RTI > In addition, the time between the light emission end time of the pixel and the data writing time differs depending on the positions of the pixels. For example, due to the difference between the data addressing speed and the light emitting addressing speed, the time between the light emission end time and the data write-in time in the first display line LN1 located at the top of the display panel 100 is the last display parameter LNL). ≪ / RTI >

The time period between the data write-in time and the light emission start time of the pixel and the time between the light emission end time and the data write-in time vary depending on the pixel position, Are substantially the same at all positions of the < RTI ID = 0.0 >

The light emitting addressing time P2 is smaller than the data addressing time P3. Thus, the rate at which all pixels start emitting light is faster than the rate at which data is written to all the pixels. The pixels start emitting light when the emission control pulse is input, and maintain the emission until the data voltage and the scan pulse are input at the data addressing time of the next frame. Therefore, the emission duration of the pixels is controlled such that the data voltage and the scan pulse are input in the (n + 1) th frame period (Fn + 1) from when the emission control pulse is input in the nth It is the time until it becomes.

All the pixels of the display panel 100 display the black gradation until the emission control pulse is inputted after the data voltage is written and the data voltage stored in the storage capacitor is maintained.

The light emitting addressing time can be further increased in each of the display lines of the display panel 100 by dividing all of the display lines LN1 to LNL of the display panel 100 into a plurality of blocks. In the display panel 100 including 1080 display lines, in order to supply the pixels with the emission control pulses in a line-by-line form during the emission addressing time, emission control pulses are applied to the pixels Groups. When the display panel 100 is divided into 10 blocks including 108 display lines in which one block is simultaneously emitted, the driving frequency for supplying the light emission control pulses to the pixels in the block-by-block form during the light emitting addressing time is 1/10 to 180 KHz and the emission duration of each of the pixels can be increased. A Block Emission Addressing Frequency (BEAF) of the block emission addressing time for dividing the display panel 100 into a plurality of blocks to emit the pixels in a block-bi-block form is expressed by the following equation (1) (LEAF) of the line emission addressing time for light emission of the light emitting unit is divided by the number of blocks (N and N are positive integers of 2 or more).

In the stereoscopic image display apparatus of the present invention, the emission sustained ratio (hereinafter referred to as "emission sustained ratio") of the pixels with respect to one frame period is expressed by Equation (2).

Where EMDUTY is the emission sustained rate. One frame period P4 is 20 ms in the PAL system and approximately 16.7 ms in the NTSC system.

5 is a timing diagram illustrating an example of 240 Hz frame frequency driving of the stereoscopic image display apparatus according to the first embodiment of the present invention.

Assuming that the stereoscopic image display device is driven at a frame frequency of 240 Hz and the on / off switching time P1 of the shutter glasses 120 is 3 ms, the emission sustaining ratio of pixels EMDUTY) and the luminance of the stereoscopic image (hereinafter referred to as "3D luminance") are calculated as EMDUTY = 58% and 3D luminance = EMDUTY × transmittance of the shutter glasses = 58% × 70% = 41%. On the other hand, in the case of simultaneous light emission as shown in FIG. 2, the 3D luminance is about 35%.

The driving frequency (LEAF) of the line emission addressing time is 1.8 MHz, and the driving frequency (BEAF) of the block emission addressing time when the display panel 100 is divided into 10 blocks is 180 KHz.

6 is a timing diagram illustrating an example of driving a frame frequency of 120 Hz in a stereoscopic image display apparatus according to an exemplary embodiment of the present invention.

Assuming that the stereoscopic image display device is driven at a frame frequency of 120 Hz and the on / off switching time P1 of the shutter glasses 120 is 3 ms in the same manner as in FIG. 4, EMDUTY) and 3D luminance are calculated as EMDUTY = 33% and 3D luminance = EMDUTY × transmittance of the shutter glasses = 58% × 70% = 23%. On the other hand, in the case of simultaneous light emission as shown in FIG. 2, the 3D luminance is about 35%.

The driving frequency (LEAF) of the line emission addressing time is 400 MHz and the driving frequency (BEAF) of the block emission addressing time when the display panel 100 is divided into 10 blocks is 40 KHz to be.

Table 1 shows the emission sustaining ratio EMDUTY of one frame period, the emission duration T _EM of the pixels within one frame period, , And the theoretical value of the 3D luminance. In Table 1, "F _frame " is the driving frequency of the data addressing time, "F _Data " is the driving frequency of the data addressing time, and "F _EM " is the driving frequency of the light addressing time. The 3D luminance is a value calculated by "3D luminance = EMDUTY × transmittance of the shutter glasses (assuming 70%)". The ON / OFF switching time of the shutter glasses 120 is 3 msec. In Table 1, "N" is the number of blocks.

F _frame F _Data F _EM EMDUTY T _EM 3D Luminance Simultaneous light emission 240Hz 259KHz The same time 50% 4.2msec 35% Sequential light emission
(line by line) 120Hz 130KHz 400KHz 33% 2.7msec 23% Sequential light emission
(line by line) 150Hz 162KHz 583KHz 41% 3.4msec 29% Sequential light emission
(line by line) 240Hz 259KHz 1.8MHz 58% 4.8msec 41% Sequential light emission
(block by block) 120Hz 130KHz 400KHz / N 33% 2.7msec 23% Sequential light emission
(block by block) 150Hz 162KHz 583KHz / N 41% 3.4msec 29% Sequential light emission
(block by block) 240Hz 259KHz 1.8 MHz / N 58% 4.8msec 41%

7 is an equivalent circuit diagram showing the pixel circuit of the display panel 100. In Fig. 8 is a waveform diagram showing driving signals of the pixel shown in FIG.

7 and 8, each of the pixels includes an organic light emitting diode OLED, a first switch TFT T1, a second switch TFT T2, a drive TFT DT, a storage capacitor Cstg, and the like do. Driving voltages such as a high-potential power supply voltage (VDD), a low-voltage (or low-potential power supply voltage, GND) are commonly supplied to the pixels. The TFTs T1, T2, and DT may be implemented as a p-type MOS TFT (Metal Oxide Semiconductor TFT) or an n-type MOS TFT. Also, the TFTs T1, T2, and DT may be implemented by a combination of a p-type MOS TFT and an n-type MOS TFT using a CMOS (Complementary Metal Oxide Semiconductor) process. 7 shows an example of TFTs implemented with a p-type MOS TFT, and it should be noted that the TFTs of the present invention are not limited to p-type MOS TFTs.

The first switch TFT T1 is connected to the gate electrode of the driving TFT DT connected to the first node n1 in response to the scan pulse S1 to Sn supplied to the scan line SL1 of the first scan group, (Cst). The drain electrode of the first switch TFT (T1) is connected to the first node (n1), and the source electrode thereof is connected to the data line DL1. The gate electrode of the first switch TFT (T1) is connected to the scan line (SL1) of the first scan group. During the data addressing time (P3), a scan pulse (Scan) synchronized with the data voltage (Data) is sequentially supplied to the scan lines of the first scan group.

The second switch TFT T2 is turned on in response to the emission control pulse Em supplied to the scan line SL2 of the second scan group and is turned on between the cathode electrode of the organic light emitting diode OLED and the ground voltage source GND Thereby forming a current path. The drain electrode of the second switch TFT (T2) is connected to the ground voltage source (GND), and its source electrode is connected to the cathode electrode of the organic light emitting diode (OLED). And the gate electrode of the second switch TFT T2 is connected to the scan line SL2 of the second scan group. The organic light emitting diode (OLED) emits light by forming a current path between the cathode electrode and the ground voltage source (GND) while the emission control pulse (Em) maintains a logic low. During the light emitting addressing time (P2), the emission control pulses are sequentially supplied to the scan lines of the second scan group on a line-by-line or block-by-block basis.

The driving TFT DT adjusts the amount of current flowing between the power supply line PL and the organic light emitting diode OLED according to the voltage (or gate node voltage) of the first node n1. The source electrode of the driving TFT DT is connected to the power supply line PL to which the high potential power supply voltage is supplied, and the drain electrode thereof is connected to the source electrode of the second switch TFT T2. The gate electrode of the driving TFT DT is connected to the first node n1.

The storage capacitor Cstg is connected between the first node n1 and the power line PL. The storage capacitor Cstg stores the threshold voltage of the driving TFT DT and stores the compensated data voltage by the threshold voltage of the driving TFT DT.

A multilayer organic compound layer is formed between the anode electrode and the cathode electrode of the organic light emitting diode (OLED). The organic compound layer includes a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), and an electron injection layer EIL). The organic light emitting diode OLED emits light with a brightness proportional to the current supplied through the driving TFT DT and the second switch TFT T2. The anode electrode of the organic light emitting diode (OLED) is connected to the drain electrode of the driving TFT (DT), and the cathode electrode thereof is connected to the source electrode of the second switch TFT (T2).

In Fig. 8, "Tblack" is a black display period in which light is not emitted until the emission control pulse Em is inputted after the data voltage Data is charged in each of the pixels. The pixels maintain the data voltage stored in the storage capacitor Cst while maintaining the non-emission state after charging the data voltage in response to the scan pulse, and start emitting light in response to the emission control pulse.

9 is a waveform diagram showing an example of a scan pulse and a light emission control pulse. 10 is a diagram showing an example in which the screen of the display panel is divided into ten blocks. 11 is a waveform diagram showing an example of a scan pulse and a light emission control pulse of a display panel divided into a plurality of blocks as shown in FIG.

When the display panel 100 is scanned line by line for the data addressing time P3 and the light emitting addressing time P2, the scan pulses S1 to Sn are sequentially supplied to the scan lines of the first scan group do.

The display panel 100 is divided into ten blocks BL1 to BL10 as shown in Fig. 10, the display panel 100 is scanned line by line for the data addressing time P3, Can be scanned. In this case, the emission duration can be made longer in each of the display lines of the display panel 100, so that the 3D luminance can be further increased. The light emission control pulse is applied to the pixels present in the block at the same time and there is a time difference between the blocks.

12 is a waveform diagram showing a driving method of the display panel 100 according to the second embodiment of the present invention.

In Fig. 12, P4 represents one frame period (Frame time).

P1a is the off-switching time of the shutter glasses 120, and P1b is the on-switching time of the shutter glasses 120. [ The start time of the off-switching time P1a of the shutter glasses 120 is substantially equal to the start time of the on-switching time P1b of the shutter glasses 120. [ The on-switching time P1b of the shutter glasses 120 is approximately 3 ms and the off-switching time P1a of the shutter glasses 120 is approximately 1 ms. Therefore, the end point of the off-switching time P1a of the shutter glasses 120 is earlier than the end of the on-switching time of the shutter glasses 120. [

The off-switching time Pl1a of the shutter glasses 120 is set to a period between the end of light emission of the last display line of the n-th frame period Fn and the initial first display line light emission start point of the (n + 1) Lt; / RTI > The first display line LN1 starts emitting within the on-switching time P1b of the shutter glasses 120 after the end of the off-switching time P1a of the shutter glasses 120. [

P2 is the light emission addressing time required for the emission control pulses to be applied to all the pixels. During the light emitting addressing time P2, the light emission control pulse is applied to the scan lines of the second scan group from the first display line LN1 to the last display line LNL of the display panel in a line-by-line form, Respectively.

P3 is a data addressing time required for data to be written to pixels of all the display lines LN1 to LNL of the display panel 100. [ During the data addressing time, the data voltages are applied to the data lines. During the data addressing time, the scan pulses are sequentially applied to the scan lines of the first scan group in a line-by-line manner from the first display line LN1 to the last display line LNL of the display panel in synchronization with the data voltage do.

The light emitting addressing time P2 is smaller than the data addressing time P3. Thus, the light emitting addressing speed is faster than the data addressing speed. The pixels start emitting light when the emission control pulse is input, and maintain the emission until the data voltage and the scan pulse are input in the next frame. The emission duration of the pixels is the time from when the emission control pulse is input in the n-th frame period Fn to when the data voltage and the scan pulse are input in the (n + 1) -th frame period Fn + 1.

The time between the pixel data writing point and the light emission start point differs depending on the positions of the pixels. For example, due to the difference between the data addressing speed and the light emission addressing speed, the time between the data write-in time and the light emission start time in the first display line LN1 located at the top of the display panel 100 is the last display parameter LNL). ≪ / RTI > In addition, the time between the light emission end time of the pixel and the data writing time differs depending on the positions of the pixels. For example, due to the difference between the data addressing speed and the light emitting addressing speed, the time between the light emission end time and the data write-in time in the first display line LN1 located at the top of the display panel 100 is the last display parameter LNL). ≪ / RTI >

Pixels whose emission start timings are fast in the display panel 100 are longer in light emission duration than pixels in which the light emission start timing is late. For example, the emission duration of the first display line LN1 is the longest and the emission duration of the last display line LNL is the shortest. Voltage leakage of the storage capacitor Cst in the pixel is less than that of a pixel having a large temporal distance from the data addressing timing to the light emission start timing when the pixels have the same light emission duration and the light emission start timings are different from each other The luminance of the pixel in which data is firstly addressed relatively can be lowered. As shown in FIGS. 12 to 14, when the emission duration of the pixels whose light emission start timings are relatively fast in the display panel 100 in each of the frame periods is lengthened, the luminance of the pixels can be increased, 100 can be brighter and more uniform.

All the pixels of the display panel 100 display the black gradation until the emission control pulse is inputted after the data voltage is written and the data voltage stored in the storage capacitor is maintained.

The light emitting addressing time can be further increased in each of the display lines of the display panel 100 by dividing all of the display lines LN1 to LNL of the display panel 100 into a plurality of blocks. In the display panel 100 including 1080 display lines, in order to supply the pixels with the emission control pulses in a line-by-line form during the emission addressing time, emission control pulses are applied to the pixels Groups. When the display panel 100 is divided into 10 blocks including 108 display lines in which one block is simultaneously emitted, the display panel 100 is divided into blocks for supplying emission control pulses to the pixels in block- The driving frequency is lowered to 1/10 and becomes 180 KHz and the emission duration of each of the pixels can be increased.

In the second embodiment of the present invention, the emission sustaining ratio (EPDUTY (%)) of the pixels with respect to one frame period is expressed by Equation (3).

As shown in Equation (3), since the second embodiment of the present invention emits pixels from immediately after the off-switching time P1a of the shutter glasses 120, the emission duration can be longer than that of the first embodiment.

FIG. 13 is a timing chart illustrating an example of 240 Hz frame frequency driving of the stereoscopic image display device according to the second embodiment of the present invention.

Assuming that the stereoscopic image display device is driven at a frame frequency of 240 Hz, the off-switching time P1a of the shutter glasses 120 is 1 ms, and the on-switching time P1b is 3 ms, The emission sustained rate (EMDUTY) of the pixels is calculated as EMDUTY = 69%,. When the shutter glasses 120 are turned off and start emitting light, it is assumed that the shutter is in a 70% ON state since the shutter is not 100% ON for 2 ms until the shutter glasses 120 are turned on. (3D brightness) of the stereoscopic image is calculated, the 3D brightness is expressed by {P1b-P1a) / P2 x EMDUTY x shutter glasses 70% on + P2- (P1b-P1a) / P2MTime x EMDUTY} Is calculated as the transmittance. Therefore, in the case of driving the stereoscopic image display device at 240 Hz in the second embodiment of the present invention, its 3D luminance = (2 / 5.74 × 69 × 0.7 + 3.74 × 69) × 0.7 = 43%.

14 is a timing chart showing an example of driving a frame frequency of 120 Hz in the stereoscopic image display device according to the second embodiment of the present invention.

Table 2 shows the 3D luminance at 120 Hz in the same manner as in the calculation of the 3D luminance at the 240 Hz driving described above.

Table 2 shows the emission sustaining ratio (EMDUTY) of the stereoscopic image display device according to the second embodiment of the present invention, the emission duration (T _EM ) of pixels within one frame period, and the theoretical value of 3D luminance.

F _frame EMDUTY T _EM 3D Luminance 120Hz 44% 3.6msec 25% 150Hz 54% 4.5msec 33% 240Hz 69% 5.74msec 43%

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the present invention should not be limited to the details described in the detailed description, but should be defined by the claims.

100: display panel 120: shutter glasses

Claims (14)

A scan line of a first scan group to which a scan pulse synchronized with the data voltage is supplied, a scan line of a second scan group to which a light emission control pulse is supplied, A display panel for displaying the left eye image data and the right eye image data in a time-division manner by including pixels for charging data and emitting light in response to the light emission control pulse, the pixels sequentially emitting light in block units including a plurality of display lines; And
And shutter glasses including a left-eye shutter and a right-eye shutter which are electrically controlled and alternately opened and closed,
Wherein the control circuit writes the left eye image data to pixels of the display panel during a data addressing time of a n-th (n is a positive integer) frame period, and writes the light emission control pulse in the block unit Inputting to the pixels,
Wherein the control circuit writes the right eye image data to the pixels of the display panel during a data addressing time of an (n + 1) -th frame period, and outputs the light emission control pulse, which is input during an emission addressing time of the Pixels,
The light emitting addressing time is smaller than the data addressing time within one frame period,
And the light emission duration time of pixels having a faster light emission start timing is longer than other pixels. The method according to claim 1,
The pixels of the display panel may include:
And the data is held in a non-light emitting state until the light emission control pulse is input after writing the data. The method according to claim 1,
The emission sustaining ratio EMDUTY of the pixels is expressed by:

Wherein the DAP is the data addressing time and the SGST is an ON / OFF switching time of the shutter glasses. The method according to claim 1,
The emission sustaining ratio EMDUTY of the pixels is expressed by:

Wherein the DAP is the data addressing time and the SGST is an off-switching time of the shutter glasses. 5. The method of claim 4,
Pixels belonging to the first display line of the display panel start emitting light immediately after the off-switching time of the shutter glasses,
Wherein the first display line includes pixels to which the data voltage is firstly addressed among display lines of the display panel. 6. The method according to any one of claims 1 to 5,
The light emission duration of the pixels on the first display line of the display panel is longer than that of the pixels belonging to the last display line of the display panel,
Wherein the last display line includes pixels whose data voltage is least recently addressed among the display lines of the display panel. 6. The method according to any one of claims 1 to 5,
Wherein the light emission control pulse is simultaneously applied to the pixels existing in the block, and a time difference occurs between the blocks. A scan line of a first scan group to which a scan pulse synchronized with the data voltage is supplied, a scan line of a second scan group to which a light emission control pulse is supplied, A display panel for displaying the left eye image data and the right eye image data by time division including pixels for charging data and emitting light in response to the light emission control pulse, the pixels sequentially emitting light in block units including a plurality of display lines; And a shutter eyeglass including a left eye shutter and a right eye shutter which are electronically controlled and alternately opened and closed, the method comprising:
Writing the left eye image data to pixels of the display panel during a data addressing time of an n-th (n is a positive integer) frame period;
Inputting the emission control pulses to the pixels on a block-by-block basis during an emission addressing time of the n-th frame period;
Writing the right eye image data to pixels of the display panel during a data addressing time of an (n + 1) -th frame period; And
And inputting the emission control pulses inputted during the emission addressing time of the (n + 1) -th frame period to the pixels in units of blocks,
The light emitting addressing time is smaller than the data addressing time within one frame period,
And the light emission duration time of pixels having a faster light emission start timing is longer than that of other pixels. 9. The method of claim 8,
Further comprising the step of maintaining the data in the pixels of the display panel in a non-emission state until the emission control pulse is input after writing the data to the pixels. Way. 9. The method of claim 8,
The emission sustaining ratio EMDUTY of the pixels is expressed by:

Wherein the DAP is the data addressing time and the SGST is an on / off switching time of the shutter glasses. 9. The method of claim 8,
The emission sustaining ratio EMDUTY of the pixels is expressed by:

Wherein the DAP is the data addressing time and the SGST is the off-switching time of the shutter glasses. 12. The method of claim 11,
Pixels belonging to the first display line of the display panel start emitting light immediately after the off-switching time of the shutter glasses,
Wherein the first display line includes pixels to which the data voltage is firstly addressed among display lines of the display panel. 13. The method according to any one of claims 8 to 12,
The light emission duration of the pixels on the first display line of the display panel is longer than that of the pixels belonging to the last display line of the display panel,
Wherein the last display line includes pixels whose data voltage is least recently addressed among the display lines of the display panel. 13. The method according to any one of claims 8 to 12,
Wherein the emission control pulse is simultaneously applied to the pixels existing in the block, and a time difference occurs between the blocks.

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