KR101710773B1 - Apparatus for controlling analog-to-digital converter and method thereof - Google Patents

Abstract

The present invention relates to an analog-to-digital conversion control apparatus. The analog-to-digital conversion control apparatus includes: a bit setting unit for setting an input signal as an upper bit region and a lower bit region; A controller for controlling the analog-to-digital converter to perform sampling once for the upper bit region and to perform sampling for N (N is a natural number greater than 2) for the lower bit region; And an output generating unit for generating an output value by using a sampling result for the upper bit region and a sampling result for the lower bit region. As described above, according to the present invention, the number of clock counts can be reduced and the conversion speed can be increased more than the conventional multiple sampling method.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an analog-to-

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an analog-to-digital conversion control apparatus and a control method thereof, and more particularly, to an analog-to-digital conversion control apparatus using a partial conversion type multiple sampling method and a control method thereof.

An analog-to-digital converter (ADC) is an electronic circuit that converts an analog electrical signal to a digital electrical signal. Since analog signals are more difficult to store and manipulate than digital signals, digitization is now more common than in early electronics. When a signal is transmitted, generally, when the analog signal is converted into a digital signal, some distortion occurs. However, it is advantageous to the noise of the signal. For signal transmission, the analog signal is converted to digital, and the digital signal is again converted to analog via a digital-to-analog converter circuit.

An analog-to-digital converter (ADC) is used in lead-out circuits for various sensors such as image sensors, touch sensors, and ultrasound imaging devices. In particular, analog-to-digital converters (ADCs) employing multiple sampling methods to reduce noise in the input and readout circuits are commonly used in applications requiring low-noise, high-speed analog-to-digital conversion.

The multiple sampling method is a method of sampling the input repeatedly several times in order to reduce the noise. In this case, the operation of performing the analog-to-digital conversion is repeated by the number of times of sampling. Then, the sampled total values are averaged to obtain the final analog-to-digital conversion value.

In this conventional multiple sampling method, the number of clock counts required for analog-to-digital conversion increases in proportion to the number of samples. Therefore, if the number of sampling times increases to reduce the noise, the analog-to-digital conversion speed decreases. Also, since the internal operation clock speed must be increased to maintain the same conversion speed, power consumption increases.

SUMMARY OF THE INVENTION An object of the present invention is to provide an analog-to-digital conversion control apparatus and a control method thereof using a multiple sampling method of a partial conversion scheme.

According to an aspect of the present invention, there is provided an analog-to-digital conversion control apparatus for controlling an analog-to-digital converter (ADC) A bit setting unit for setting an input signal of the analog-to-digital converter as an upper bit region and a lower bit region; A controller for controlling the analog-to-digital converter to perform sampling once for the upper bit region and to perform sampling for N (N is a natural number greater than 2) for the lower bit region; And an output generating unit for generating an output value by using a sampling result for the upper bit region and a sampling result for the lower bit region.

Here, the bit setting unit may set the upper bit and the lower bit to be the same in a pseudo-multiple sampling method.

Here, the bit setting unit may increase the specific gravity of the upper bits and decrease the specific gravity of the lower bits as the sampling number increases in a correlated multiple sampling method.

Here, the bit setting unit may adaptively set an upper bit region and a lower bit region according to a magnitude of noise of the input signal.

Here, the bit setting unit may set the lower bit region so that the lower bit region includes the change region of the noise.

Here, the controller may perform sampling on a lower bit region using different sampling signals.

Here, the output generator may use an average value for the N times sampling as a sampling result for the lower bit region.

According to an embodiment of the present invention, an analog-to-digital conversion method performed in an analog-to-digital conversion control apparatus for controlling an analog-to-digital converter includes the steps of: ) Into an upper bit region and a lower bit region; Performing one sampling on the upper bit region and controlling the analog-to-digital converter to perform N sampling (N is a natural number greater than 2) for the lower bit region; And generating an output value using the sampling result for the upper bit region and the sampling result for the lower bit region.

Here, the bit setting step may set the upper bit and the lower bit to be the same in a pseudo-multiple sampling method.

Here, the bit setting step may increase the specific gravity of the upper bits and decrease the specific gravity of the lower bits as the sampling number increases in the correlated multiple sampling method.

Here, the bit setting step may adaptively set the upper bit region and the lower bit region according to the magnitude of the noise of the input signal.

Here, the bit setting step may set the lower bit region so that the lower bit region includes the change region of the noise.

Here, the controlling step may perform sampling on a lower bit region using different sampling signals.

Here, the generating of the output value may use an average value for the N times sampling as a sampling result for the lower bit region.

According to the analog-digital conversion control apparatus and the control method therefor of the present invention, it is possible to increase the conversion speed by reducing the number of clock counts compared with the conventional multiple sampling method. Also, when the same time conversion is performed, the power consumption can be reduced as compared with the conventional method.

1 is a block diagram of an analog-to-digital conversion control apparatus according to an embodiment of the present invention.
2 is a flowchart of an analog-to-digital conversion method according to an embodiment of the present invention.
3 is a block diagram of a two-step single-slope analog-to-digital converter.
Figure 4 is a ramp signal waveform and timing diagram of the two-step single-slope analog-to-digital converter of Figure 3;
FIG. 5 is a timing diagram of a ramp signal of a two-stage single-slope analog-to-digital converter to which a partial correlated multiple sampling (PCMS) method of correlation multiple sampling according to the first embodiment of the present invention is applied.
6 is a ramp signal waveform and timing diagram of a two-stage single slant analog-to-digital converter to which a partial pseudo-multiple sampling (PPMS) method of pseudo-multiple sampling according to a second embodiment of the present invention is applied.
Fig. 7 is a block diagram of a two-stage approximation type analog-to-digital converter.
FIG. 8 is a waveform diagram of two input signals of a comparator of the double-ended approximation type analog-to-digital converter of FIG. 7 to which the partial multiple sampling method according to the third embodiment of the present invention is applied.
9 is a block diagram of a series-approximation-single slope analog-to-digital converter.
FIG. 10 is a waveform of two input signals of a comparator of the approximate-single-slope analog-to-digital converter of FIG. 9 to which the partial multiplexing method according to the fourth embodiment of the present invention is applied.

While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It is to be understood, however, that the invention is not to be limited to the specific embodiments, but includes all modifications, equivalents, and alternatives falling within the spirit and scope of the invention. Like reference numerals are used for like elements in describing each drawing.

The terms first, second, A, B, etc. may be used to describe various elements, but the elements should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as a second component, and similarly, the second component may also be referred to as a first component. And / or < / RTI > includes any combination of a plurality of related listed items or any of a plurality of related listed items.

It is to be understood that when an element is referred to as being "connected" or "connected" to another element, it may be directly connected or connected to the other element, . On the other hand, when an element is referred to as being "directly connected" or "directly connected" to another element, it should be understood that there are no other elements in between.

The terminology used in this application is used only to describe a specific embodiment and is not intended to limit the invention. The singular expressions include plural expressions unless the context clearly dictates otherwise. In the present application, the terms "comprises" or "having" and the like are used to specify that there is a feature, a number, a step, an operation, an element, a component or a combination thereof described in the specification, But do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or combinations thereof.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in commonly used dictionaries are to be interpreted as having a meaning consistent with the contextual meaning of the related art and are to be interpreted as either ideal or overly formal in the sense of the present application Do not.

Hereinafter, preferred embodiments according to the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram of an analog-to-digital conversion control apparatus according to an embodiment of the present invention.

Referring to FIG. 1, an analog-digital conversion control apparatus 100 according to an embodiment of the present invention may include a bit setting unit 110, a control unit 120, and an output generation unit 130.

The bit setting unit 110 may set an upper bit region and a lower bit region for an input signal. At this time, the bit setting unit 110 can set the upper bit region and the lower bit region in consideration of the noise of the input signal.

An analog-to-digital converter (ADC) is a device that converts an analog signal to a digital value. The concept of sampling in digital conversion refers to floating analog signals at regular intervals. In other words, sampling refers to the operation of converting the characteristics of an analog signal into a digital signal. Here, the quality of the digital signal is determined according to the sampling frequency and the sampling rate. The sampling frequency is about how often to sample, and the sampling rate is how many bits are used to represent analog values as digital values.

The control unit 120 controls the analog-to-digital converter (ADC) to perform one sampling for the upper bit region and N times for the lower bit region. Here, a multiple sampling method using a partial transform scheme can be applied by performing one sampling for the upper bit region and N times sampling for the lower bit region. Where N is a natural number greater than 2.

The output generating unit 130 generates an output value using an upper bit value in the upper bit region and an average value of lower bit values in the lower bit region. That is, for the lower bit region, the mean value of the result according to the multiple sampling is used to improve the accuracy.

Hereinafter, an analog-digital conversion method according to an embodiment of the present invention will be described in detail with reference to the drawings.

2 is a flowchart of an analog-to-digital conversion method according to an embodiment of the present invention.

Referring to FIG. 2, an input signal may be set as an upper bit region and a lower bit region prior to sampling (S310). That is, in order to apply the partial multiplexing method according to the present invention to an analog-to-digital converter (ADC), the bit setting unit 110 divides an output value into an upper bit region and a lower bit region.

According to an embodiment of the present invention, when a partial correlated multiple sampling method of correlated multiple samples is applied to a two-step single-slope analog-to-digital converter (ADC) 110) can be divided into an upper bit region and a lower bit region divided by the case where all bits are 2N-1 and 2N (where N is a natural number greater than 2) as shown in Table 1 below. In addition, the bit setting unit 110 may adaptively set the size of the lower bit region according to the noise of the input signal. For example, when the noise is relatively large, the bit setting unit 110 sets the lower bit region to be larger, and conversely, when the noise is relatively smaller, the lower bit region can be set smaller.

Next, the control unit 120 controls the analog-to-digital converter (ADC) to perform sampling once on the divided upper bit region through the control of the ramp signal (S320) .

3 is a block diagram of a two-step single-slope (TSSS) analog-to-digital converter (ADC).

3, a two-stage single-slope (TSSS) analog-to-digital converter (ADC) includes a sampling unit 210, a comparator 220 and a counter 230. The controller 120 controls the sampling unit 210, the comparator 220, and the counter 230 to allow the analog-to-digital converter (ADC) to perform sampling.

Figure 4 is a ramp signal waveform and timing diagram of a two-step single-slope (TSSS) analog-to-digital converter (ADC)

Referring to FIG. 4, when an upper bit is converted, the S _U signal becomes 'High' and the S _H becomes 'High', and the ramp signal is transmitted to the comparator through the V _COMP node. When the voltage of the V _COMP node becomes lower than the voltage of the V _IN voltage, the instant S _H becomes 'Low' at the moment when the output V _O of the comparator 220 becomes 'High', and the lamp voltage V _H at this time is stored in the C _H. Also, when V _O becomes 'High', the V _{U_CNT_EN} signal becomes 'Low', and the upper bit counting in the counter 230 stops, and the upper bit value of the two-stage analog-to-digital converter (ADC) is determined.

Next, the control unit 120 controls the analog-to-digital converter (ADC) to perform N times of sampling for the divided lower bit region through the control of the ramp signal (S330). In this case, the controller 120 may cause the different ramp signals to be input to the analog-to-digital converter (ADC) for each sampling.

Referring to FIG. 4, as the S _L signal becomes 'High' at the lower bit conversion, the ramp signal is reduced by V _H stored in C _H and transferred to the comparator 220 via the V _COMP node. S _H has a value of 'Low' when converting lower bits. When the voltage of the V _COMP node becomes lower than the voltage of the V _IN even in the conversion of the lower bit, the V _{L_CNT_EN} signal becomes 'Low' when the output V _O of the comparator 220 becomes 'High' The lower bit value of the two-stage analog-to-digital converter (ADC) is determined.

Finally, the output generating unit 130 generates an output value using the upper bit value in the upper bit region and the lower bit value in the lower bit region (S340). In this case, the output generating unit 130 may use an average value obtained through multisampling for the lower bit value.

Hereinafter, various embodiments in which the partial multiplexing method of the present invention is applied to an analog-to-digital converter (ADC) will be described.

FIG. 5 is a timing diagram of a ramp signal waveform of a two-stage single-slope (TSSS) analog-to-digital converter (ADC) using a partial correlated multiple sampling (PCMS) method of correlation multiple sampling according to a first embodiment of the present invention. to be.

In this embodiment, the same noise reduction effect as common correlated multiple sampling (CMS) occurs. That is, the noise reduction effect increases in proportion to the sampling number. Also, since the CMS scheme is used at the lower bit conversion, the clock count increases as the number of multiple samplings increases. However, the clock count increase rate is greatly reduced compared to the general CMS scheme due to a two-step architecture.

Referring to FIG. 5, a general two-stage single-slope analog-digital conversion scheme is used as the analog-digital conversion scheme for the first sample. After the second sample from the first to the last analog sample-while maintaining the high-order bit and the voltage V _H obtained by the digital conversion repeated but the low-order bit conversion, and the low-order bit value is generated. The output generating unit 130 outputs the final digital value using the upper bit value obtained from the first sample and the average value of the lower bit values from the first sample to the last sample.

6 is a ramp signal waveform and timing diagram of a two-stage single-slope analog-to-digital converter (ADC) with a partial pseudo-multiple sampling (PPMS) method of pseudo-multiple sampling according to a second embodiment of the present invention.

According to the present embodiment, a pseudo-multiple sampling (PMS) scheme is used in the lower bit conversion, and a clock count is determined by the resolution of the analog-to-digital converter irrespective of the number of multiple samples . In addition, when the input noise is small, the effect of noise reduction is small.

Referring to FIG. 6, in the analog-to-digital conversion for the first sample, a general two-stage single-slope analog-to-digital conversion scheme is used for high-order bit conversion. The pseudo-multiple sampling method is then used for the lower bit conversion. The output generating unit 130 generates a final digital output value using the upper bit value obtained from the first sample and the lower bit value obtained through the pseudo-multiple sampling.

FIG. 7 is a block diagram of a two-end approximation type analog-to-digital converter (ADC).

Referring to FIG. 7, a two-stage approximation analog-to-digital converter (ADC) is used to reduce the size of a capacitor digital-to-analog converter The lower bit conversion is performed using the reference voltage in the range.

FIG. 8 is a waveform diagram of two input signals of a comparator of the double-ended approximation type analog-to-digital converter of FIG. 7 to which the partial multiple sampling method according to the third embodiment of the present invention is applied.

Referring to FIG. 8, the operation of the general-approximation-type analog-to-digital converter is performed using the reference voltages V _{REF_TOP} and V _{REF_BOT} during the high bit conversion. When the low bit conversion is performed, the S _L signal becomes 'High', and the V _COMP signal is lowered by 1/2 of the LSB of the upper bit. In addition to V _{REF_TOP} and V _{REF_BOT} , the reference voltages V _R / 2 ^{N + 1} + V _{REF_TOP} and V _R / 2 ^{N + 1} + V _{REF_BOT} are used. By performing the operation of the generalized approximation analog-to-digital converter on the basis of the reference voltage of the changed range, the lower bit value of one sample can be obtained and the multiple sampling effect can be obtained by repeating the lower bit conversion by the desired number of samples .

9 is a block diagram of a series-approximation-single slope analog-to-digital converter.

Referring to FIG. 9, the ramp signal is connected to the lower end of the dummy capacitor of the approximate-single-slope analog-to-digital converter of FIG. The approximate analog-to-digital conversion operation is performed for the higher bit conversion, and then the single slope analog-to-digital conversion operation is performed by changing the ramp signal for lower bit conversion.

FIG. 10 is a waveform of two input signals of a comparator of the approximate-single-slope analog-to-digital converter of FIG. 9 to which the partial multiplexing method according to the fourth embodiment of the present invention is applied.

Referring to FIG. 10, the operation of the general-approximation-type analog-to-digital converter is performed using the reference voltages V _{REF_TOP} and V _{REF_BOT} during high bit conversion. When the lower bit conversion is performed, the S _L signal becomes 'High', and the V _COMP signal is lowered by 1/2 of the LSB of the upper bit. Then, the change amount of the V _RAMP value is compared with the total capacitor value of the capacitor digital- And is reflected in V _COMP . The operation of the general single-slope analog-to-digital converter is performed using the V _COMP value to generate a lower-bit value of one sample, and the lower-bit conversion is repeated as many times as the desired number of samples.

In the case of a conventional conversion in which a correlated-multiple sampling (CMS) scheme is applied to a two-step single-slope analog-to-digital converter, the resolution of the analog- The clock count determined by the sampling clock count increases in proportion to the sampling number.

On the other hand, according to the embodiment of the present invention, when the number of bits is 12 bits and sampling of 16 times is performed, the clock counts are reduced by 99.7% and 98.8% by PPMS and PCMS.

As described above, according to the analog-digital conversion control apparatus and the control method thereof according to the embodiment of the present invention, the number of clock counts can be reduced and the conversion speed can be increased more than the conventional multiple sampling method. Also, if the same time conversion is performed, the power consumption can be reduced as compared with the conventional method.

The present invention has been described above with reference to the embodiments. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. Therefore, the disclosed embodiments should be considered in an illustrative rather than a restrictive sense. Therefore, the scope of the present invention is not limited to the above-described embodiments, but should be construed to include various embodiments within the scope of the claims and equivalents thereof.

100: analog-to-digital conversion control device,
110: bit setting unit, 120: control unit,
130: output generating unit, 200: analog-to-digital converter,
210: sampling unit, 220: comparator,
230: Counter

Claims (14)

An analog-to-digital conversion controller for controlling an analog-to-digital converter,
A bit setting unit for setting an input signal of the analog-to-digital converter as an upper bit region and a lower bit region;
A controller for controlling the analog-to-digital converter to perform sampling once for the upper bit region and to perform sampling for N (N is a natural number greater than 2) for the lower bit region; And
And an output generating unit for generating an output value using a sampling result of the upper bit region and a sampling result of the lower bit region,
Wherein the controller performs sampling on a lower bit region using different sampling signals. The method according to claim 1,
Wherein the bit setting unit comprises:
Wherein the upper bit and the lower bit are set the same in a pseudo-multiple sampling method. The method according to claim 1,
Wherein the bit setting unit comprises:
An analog-to-digital conversion control apparatus for increasing the specific gravity of upper bits and decreasing the specific gravity of lower bits as the number of samples increases in a correlated multiple sampling method. The method according to claim 1,
Wherein the bit setting unit comprises:
And an upper bit region and a lower bit region are adaptively set according to a magnitude of noise of the input signal. The method of claim 4,
Wherein the bit setting unit comprises:
And sets the lower bit region so that the lower bit region includes the change region of the noise. delete The method according to claim 1,
Wherein the output generating unit comprises:
And uses an average value for the N times sampling as a sampling result for the lower bit region. An analog-to-digital conversion method performed in an analog-to-digital conversion control apparatus for controlling an analog-to-digital converter,
Setting an input signal of the analog-to-digital converter as an upper bit region and a lower bit region;
Performing one sampling on the upper bit region and controlling the analog-to-digital converter to perform N sampling (N is a natural number greater than 2) for the lower bit region; And
Generating an output value by using a sampling result for the upper bit region and a sampling result for the lower bit region,
Wherein the controlling step performs sampling on a lower bit region using different sampling signals. The method of claim 8,
Wherein the setting of the upper bit region and the lower bit region comprises:
Wherein the upper bit and the lower bit are the same in a pseudo-multiple sampling method. The method of claim 8,
Wherein the setting of the upper bit region and the lower bit region comprises:
A method of analog-to-digital conversion control for increasing the specific gravity of upper bits and decreasing the specific gravity of lower bits as the number of samples increases in a correlated multiple sampling method. The method of claim 8,
Wherein the setting of the upper bit region and the lower bit region comprises:
And an upper bit region and a lower bit region are adaptively set according to a magnitude of noise of the input signal. The method of claim 11,
Wherein the setting of the upper bit region and the lower bit region comprises:
And setting the lower bit region so that the lower bit region includes the change region of the noise. delete The method of claim 8,
Wherein the generating the output value comprises:
And using an average value for the N-times sampling as a sampling result for the lower bit region.

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