KR101696347B1 - Polyimide film for semiconductor package reflow process and method of manufacturing the same - Google Patents

Polyimide film for semiconductor package reflow process and method of manufacturing the same Download PDF

Info

Publication number
KR101696347B1
KR101696347B1 KR1020160110930A KR20160110930A KR101696347B1 KR 101696347 B1 KR101696347 B1 KR 101696347B1 KR 1020160110930 A KR1020160110930 A KR 1020160110930A KR 20160110930 A KR20160110930 A KR 20160110930A KR 101696347 B1 KR101696347 B1 KR 101696347B1
Authority
KR
South Korea
Prior art keywords
thermoplastic polyimide
polyimide layer
reflow process
layer
group
Prior art date
Application number
KR1020160110930A
Other languages
Korean (ko)
Inventor
이계웅
박호영
이태석
Original Assignee
(주)아이피아이테크
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by (주)아이피아이테크 filed Critical (주)아이피아이테크
Priority to KR1020160110930A priority Critical patent/KR101696347B1/en
Application granted granted Critical
Publication of KR101696347B1 publication Critical patent/KR101696347B1/en
Priority to JP2019532901A priority patent/JP6816286B2/en
Priority to PCT/KR2017/006871 priority patent/WO2018043897A1/en
Priority to CN201780052747.3A priority patent/CN109661719B/en
Priority to US16/329,394 priority patent/US11015089B2/en

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4846Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • CCHEMISTRY; METALLURGY
    • C09DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
    • C09JADHESIVES; NON-MECHANICAL ASPECTS OF ADHESIVE PROCESSES IN GENERAL; ADHESIVE PROCESSES NOT PROVIDED FOR ELSEWHERE; USE OF MATERIALS AS ADHESIVES
    • C09J7/00Adhesives in the form of films or foils
    • C09J7/20Adhesives in the form of films or foils characterised by their carriers
    • C09J7/29Laminated material
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B32LAYERED PRODUCTS
    • B32BLAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B27/00Layered products comprising a layer of synthetic resin
    • B32B27/06Layered products comprising a layer of synthetic resin as the main or only constituent of a layer, which is next to another layer of the same or of a different material
    • B32B27/08Layered products comprising a layer of synthetic resin as the main or only constituent of a layer, which is next to another layer of the same or of a different material of synthetic resin
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B32LAYERED PRODUCTS
    • B32BLAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B27/00Layered products comprising a layer of synthetic resin
    • B32B27/28Layered products comprising a layer of synthetic resin comprising synthetic resins not wholly covered by any one of the sub-groups B32B27/30 - B32B27/42
    • B32B27/281Layered products comprising a layer of synthetic resin comprising synthetic resins not wholly covered by any one of the sub-groups B32B27/30 - B32B27/42 comprising polyimides
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B32LAYERED PRODUCTS
    • B32BLAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B7/00Layered products characterised by the relation between layers; Layered products characterised by the relative orientation of features between layers, or by the relative values of a measurable parameter between layers, i.e. products comprising layers having different physical, chemical or physicochemical properties; Layered products characterised by the interconnection of layers
    • B32B7/04Interconnection of layers
    • B32B7/12Interconnection of layers using interposed adhesives or interposed materials with bonding properties
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02118Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer carbon based polymeric organic or inorganic material, e.g. polyimides, poly cyclobutene or PVC
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836Wafer tapes, e.g. grinding or dicing support tapes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838Geometry or layout
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/50Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B32LAYERED PRODUCTS
    • B32BLAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B2250/00Layers arrangement
    • B32B2250/022 layers
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B32LAYERED PRODUCTS
    • B32BLAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B2250/00Layers arrangement
    • B32B2250/24All layers being polymeric
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B32LAYERED PRODUCTS
    • B32BLAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B2307/00Properties of the layers or laminate
    • B32B2307/30Properties of the layers or laminate having particular thermal properties
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B32LAYERED PRODUCTS
    • B32BLAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B2307/00Properties of the layers or laminate
    • B32B2307/70Other properties
    • B32B2307/748Releasability
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B32LAYERED PRODUCTS
    • B32BLAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B2457/00Electrical equipment
    • B32B2457/14Semiconductor wafers
    • CCHEMISTRY; METALLURGY
    • C09DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
    • C09JADHESIVES; NON-MECHANICAL ASPECTS OF ADHESIVE PROCESSES IN GENERAL; ADHESIVE PROCESSES NOT PROVIDED FOR ELSEWHERE; USE OF MATERIALS AS ADHESIVES
    • C09J2203/00Applications of adhesives in processes or use of adhesives in the form of films or foils
    • C09J2203/326Applications of adhesives in processes or use of adhesives in the form of films or foils for bonding electronic components such as wafers, chips or semiconductors
    • CCHEMISTRY; METALLURGY
    • C09DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
    • C09JADHESIVES; NON-MECHANICAL ASPECTS OF ADHESIVE PROCESSES IN GENERAL; ADHESIVE PROCESSES NOT PROVIDED FOR ELSEWHERE; USE OF MATERIALS AS ADHESIVES
    • C09J2301/00Additional features of adhesives in the form of films or foils
    • C09J2301/10Additional features of adhesives in the form of films or foils characterized by the structural features of the adhesive tape or sheet
    • C09J2301/12Additional features of adhesives in the form of films or foils characterized by the structural features of the adhesive tape or sheet by the arrangement of layers
    • C09J2301/122Additional features of adhesives in the form of films or foils characterized by the structural features of the adhesive tape or sheet by the arrangement of layers the adhesive layer being present only on one side of the carrier, e.g. single-sided adhesive tape
    • CCHEMISTRY; METALLURGY
    • C09DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
    • C09JADHESIVES; NON-MECHANICAL ASPECTS OF ADHESIVE PROCESSES IN GENERAL; ADHESIVE PROCESSES NOT PROVIDED FOR ELSEWHERE; USE OF MATERIALS AS ADHESIVES
    • C09J2301/00Additional features of adhesives in the form of films or foils
    • C09J2301/10Additional features of adhesives in the form of films or foils characterized by the structural features of the adhesive tape or sheet
    • C09J2301/16Additional features of adhesives in the form of films or foils characterized by the structural features of the adhesive tape or sheet by the structure of the carrier layer
    • C09J2301/162Additional features of adhesives in the form of films or foils characterized by the structural features of the adhesive tape or sheet by the structure of the carrier layer the carrier being a laminate constituted by plastic layers only
    • CCHEMISTRY; METALLURGY
    • C09DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
    • C09JADHESIVES; NON-MECHANICAL ASPECTS OF ADHESIVE PROCESSES IN GENERAL; ADHESIVE PROCESSES NOT PROVIDED FOR ELSEWHERE; USE OF MATERIALS AS ADHESIVES
    • C09J2479/00Presence of polyamine or polyimide
    • C09J2479/08Presence of polyamine or polyimide polyimide
    • C09J2479/086Presence of polyamine or polyimide polyimide in the substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/6834Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to protect an active side of a device or wafer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68377Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support with parts of the auxiliary support remaining in the finished device
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81001Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/81005Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818Bonding techniques
    • H01L2224/81801Soldering or alloying
    • H01L2224/81815Reflow soldering
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06Polymers
    • H01L2924/07Polyamine or polyimide
    • H01L2924/07025Polyimide
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00Stock material or miscellaneous articles
    • Y10T428/28Web or sheet containing structurally defined element or component and having an adhesive outermost layer
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00Stock material or miscellaneous articles
    • Y10T428/28Web or sheet containing structurally defined element or component and having an adhesive outermost layer
    • Y10T428/2848Three or more layers

Abstract

Disclosed are a polyimide film for a semiconductor package reflow process, which can secure ease of detachment and attachment of a semiconductor chip after completion of a reflow process by applying a thermoplastic polyimide layer having a glass transition temperature lower than a reflow process temperature, and a method for manufacturing the same. The polyimide film for a semiconductor package reflow process according to the present invention comprises a non-thermoplastic polyimide layer; a thermoplastic polyimide layer laminated on the non-thermoplastic polyimide layer and having a glass transition temperature lower than a reflow process temperature; and an adhesive layer attached onto the thermoplastic polyimide layer. The surface of the thermoplastic polyimide layer is modified with a carboxyl group.

Description

반도체 패키지 리플로우 공정용 폴리이미드 필름 및 그 제조 방법{POLYIMIDE FILM FOR SEMICONDUCTOR PACKAGE REFLOW PROCESS AND METHOD OF MANUFACTURING THE SAME}TECHNICAL FIELD [0001] The present invention relates to a polyimide film for a semiconductor package reflow process, and a method of manufacturing the same. BACKGROUND ART < RTI ID = 0.0 >

본 발명은 폴리이미드 필름 및 그 제조 방법에 관한 것으로, 보다 상세하게는 리플로우 공정 온도 이하의 유리전이온도를 갖는 열가소성 폴리이미드층의 적용으로 리플로우 공정 완료 후 반도체 칩의 탈부착에 대한 용이성을 확보할 수 있는 반도체 패키지 리플로우 공정용 폴리이미드 필름 및 그 제조 방법에 관한 것이다.
The present invention relates to a polyimide film and a method of manufacturing the same, and more particularly, to a polyimide film which is easy to detach and attach to a semiconductor chip after completion of a reflow process by applying a thermoplastic polyimide layer having a glass transition temperature not higher than the reflow process temperature To a polyimide film for a semiconductor package reflow process and a manufacturing method thereof.

폴리이미드 필름은 기계적 및 열적 치수 안정성이 우수하고, 화학적 안정성을 갖는 특성으로 인해 전기, 전자 재료, 우주, 항공 및 전기통신 분야에 넓게 이용되고 있다. 이러한 폴리이미드 필름은 부품의 경박단소화로 인해 미세한 패턴을 가진 연성 회로기판 재료, 일예로 TAB(Tape Automated Bonding)나 COF(Chip On Film) 등의 베이스 필름으로 많이 사용되고 있다.Polyimide films are widely used in the fields of electricity, electronic materials, space, aviation and telecommunications due to their excellent mechanical and thermal dimensional stability and their chemical stability properties. Such a polyimide film is often used as a flexible circuit substrate material having a minute pattern due to the thinning and shortening of parts, for example, a base film such as TAB (Tape Automated Bonding) or COF (Chip On Film).

TAB 또는 COF 기술은 IC 칩이나 LSI 칩을 밀봉하는 기술의 일종으로, 구체적으로는 연성 테이프 위에 전도성 패턴을 만들고 위에 칩을 실장하여 밀봉하는 기술로, 패키지화된 밀봉소자의 크기가 작고 가요성을 가지고 있어 제품의 경박단소화에 유리하다.TAB or COF technology is a technique for sealing an IC chip or an LSI chip, specifically, a technique of forming a conductive pattern on a flexible tape and mounting a chip thereon to seal the flexible tape. The size of the packaged sealing element is small and flexible It is advantageous for simple and light weight of product.

폴리이미드 필름을 TAB이나 COF용 베이스 필름으로 이용하기 위해서는 높은 치수 안정성이 요구된다.In order to use a polyimide film as a base film for TAB or COF, high dimensional stability is required.

특히, 반도체 패키지의 제조시 반도체 칩을 기판과 전기적으로 연결하기 위해 납땜 리플로우(Reflow) 공정을 반드시 거치게 되는데, 이 경우 폴리이미드 필름이 리플로우 공정 온도인 대략 260℃ 부근에 노출된다.Particularly, in manufacturing a semiconductor package, a solder reflow process must be performed in order to electrically connect the semiconductor chip to the substrate. In this case, the polyimide film is exposed to a reflow process temperature of about 260 ° C.

이때, 종래의 폴리이미드 필름은 기재 필름 상에 열가소성 폴리이미드층 및 점착층이 차례로 적층되는 구조를 갖는다. 일반적으로, 종래의 폴리이미드 필름은 기재 필름과 점착층 사이에 개재되는 열가소성 폴리이미드층으로 리플로우 공정 온도 이상, 대략 300℃ 이상의 유리전이온도를 갖는 것을 이용하고 있는데, 이 경우 리플로우 공정 완료 후 반도체 칩에 대한 탈부착이 용이하지 못하다는 문제가 있었다.At this time, the conventional polyimide film has a structure in which a thermoplastic polyimide layer and an adhesive layer are sequentially laminated on a base film. In general, a conventional polyimide film uses a thermoplastic polyimide layer interposed between a base film and a pressure-sensitive adhesive layer and having a glass transition temperature of at least 300 캜 above the reflow process temperature. In this case, after the completion of the reflow process There is a problem in that detachment and attachment to the semiconductor chip is not easy.

관련 선행문헌으로는 대한민국 공개특허공보 제10-2014-0084095호(2014.07.04. 공개)가 있으며, 상기 문헌에는 리플로우 필름, 땜납 범프 형성 방법, 땜납 접합의 형성 방법 및 반도체 장치가 기재되어 있다.
A related prior art is Korean Patent Laid-Open Publication No. 10-2014-0084095 (published on Apr. 04, 2014), which describes a reflow film, a method of forming a solder bump, a method of forming a solder joint, and a semiconductor device .

본 발명의 목적은 리플로우 공정 온도 이하의 유리전이온도를 갖는 열가소성 폴리이미드층의 적용으로 리플로우 공정 완료 후 반도체 칩의 탈부착에 대한 용이성을 확보할 수 있는 반도체 패키지 리플로우 공정용 폴리이미드 필름 및 그 제조 방법을 제공하는 것이다.
An object of the present invention is to provide a polyimide film for a semiconductor package reflow process which can secure ease of detachment and attachment of a semiconductor chip after completion of a reflow process by applying a thermoplastic polyimide layer having a glass transition temperature not higher than a reflow process temperature And a manufacturing method thereof.

상기 목적을 달성하기 위한 본 발명의 실시예에 따른 반도체 패키지 리플로우 공정용 폴리이미드 필름은 비열가소성 폴리이미드층; 상기 비열가소성 폴리이미드층 상에 적층되며, 리플로우 공정 온도 이하의 유리전이온도를 갖는 열가소성 폴리이미드층; 및 상기 열가소성 폴리이미드층 상에 부착된 점착층;을 포함하며, 상기 열가소성 폴리이미드층의 표면은 카르복실기로 개질 처리된 것을 특징으로 한다.
According to an aspect of the present invention, there is provided a polyimide film for a semiconductor package reflow process, comprising: a non-thermoplastic polyimide layer; A thermoplastic polyimide layer laminated on the non-thermoplastic polyimide layer, the thermoplastic polyimide layer having a glass transition temperature lower than the reflow process temperature; And an adhesive layer adhered on the thermoplastic polyimide layer, wherein the surface of the thermoplastic polyimide layer is modified with a carboxyl group.

상기 목적을 달성하기 위한 본 발명의 실시예에 따른 반도체 패키지 리플로우 공정용 폴리이미드 필름 제조 방법은 (a) 비열가소성 폴리이미드층을 마련하는 단계; (b) 상기 비열가소성 폴리이미드층 상에 리플로우 공정 온도 이하의 유리전이온도를 가지며, 표면이 카르복실기로 개질 처리된 열가소성 폴리이미드층을 부착하는 단계; 및 (c) 상기 열가소성 폴리이미드층 상에 점착층을 부착하는 단계;를 포함하는 것을 특징으로 한다.
According to an aspect of the present invention, there is provided a method of manufacturing a polyimide film for a semiconductor package reflow process, the method comprising: (a) providing a non-thermoplastic polyimide layer; (b) attaching a thermoplastic polyimide layer having a glass transition temperature lower than the reflow process temperature on the non-thermoplastic polyimide layer and having a surface modified with a carboxyl group; And (c) attaching an adhesive layer on the thermoplastic polyimide layer.

본 발명에 따른 반도체 패키지 리플로우 공정용 폴리이미드 필름 및 그 제조 방법은 열가소성 폴리이미드층으로 에테르기, 케톤기 및 메틸기 중 어느 하나가 있는 방향족 디아민과 에테르기, 케톤기 및 메틸기 중 어느 하나가 있는 방향족 디안하이드리드(aromatic dianhydride)를 유기 용매에 합성하여 제조된 폴리아믹산을 이용함으로써, 열가소성 폴리이미드층이 260℃ 이하의 낮은 유리전이온도를 가질 수 있게 된다.The polyimide film for a semiconductor package reflow process and the method for producing the same according to the present invention are characterized in that the thermoplastic polyimide layer contains any one of an aromatic diamine having an ether group, a ketone group and a methyl group, and an ether group, a ketone group and a methyl group By using a polyamic acid prepared by synthesizing an aromatic dianhydride in an organic solvent, the thermoplastic polyimide layer can have a low glass transition temperature of 260 캜 or less.

이 결과, 본 발명에 따른 반도체 패키지 리플로우 공정용 폴리이미드 필름 및 그 제조 방법은 260℃ 이하의 유리전이온도를 갖는 열가소성 폴리이미드층을 적용함으로써, 리플로우 공정을 완료한 후 이형성 확보로 반도체 칩과의 탈부착이 용이해질 수 있다.As a result, the polyimide film for the semiconductor package reflow process and the method of manufacturing the same according to the present invention can be manufactured by applying the thermoplastic polyimide layer having a glass transition temperature of 260 캜 or less, Can be easily detached and attached.

또한, 본 발명의 실시예에 따른 반도체 패키지 리플로우 공정용 폴리이미드 필름 및 그 제조 방법은 표면이 카르복실기로 개질 처리된 열가소성 폴리이미드층을 적용하는 것에 의해, 표면 개질을 통한 활성화로 카르복실기에 의해 열가소성 폴리이미드층과 점착층 간의 접착력 향상으로 우수한 접합 신뢰성을 확보할 수 있다.
The polyimide film for the semiconductor package reflow process and the method of manufacturing the same according to the embodiment of the present invention can be manufactured by applying a thermoplastic polyimide layer whose surface is modified with a carboxyl group, The bonding strength between the polyimide layer and the pressure-sensitive adhesive layer can be improved and excellent bonding reliability can be ensured.

도 1은 본 발명의 실시예에 따른 반도체 패키지 리플로우 공정용 폴리이미드 필름을 나타낸 단면도.
도 2는 본 발명의 실시예에 따른 반도체 패키지 리플로우 공정용 폴리이미드 필름 제조 방법을 나타낸 공정 순서도.
1 is a cross-sectional view of a polyimide film for a semiconductor package reflow process according to an embodiment of the present invention.
2 is a process flow diagram illustrating a method of manufacturing a polyimide film for a semiconductor package reflow process according to an embodiment of the present invention.

본 발명의 이점 및 특징, 그리고 그것들을 달성하는 방법은 첨부되는 도면과 함께 상세하게 후술되어 있는 실시예를 참조하면 명확해질 것이다. 그러나, 본 발명은 이하에서 개시되는 실시예에 한정되는 것이 아니라 서로 다른 다양한 형태로 구현될 것이며, 단지 본 실시예는 본 발명의 개시가 완전하도록 하며, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 발명의 범주를 완전하게 알려주기 위해 제공되는 것이며, 본 발명은 청구항의 범주에 의해 정의될 뿐이다. 명세서 전체에 걸쳐 동일 참조 부호는 동일 구성요소를 지칭한다.BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention, and how to accomplish them, will become apparent by reference to the embodiments described in detail below with reference to the accompanying drawings. It should be understood, however, that the invention is not limited to the disclosed embodiments, but may be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Is provided to fully convey the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims. Like reference numerals refer to like elements throughout the specification.

이하 첨부된 도면을 참조하여 본 발명의 바람직한 실시예에 따른 반도체 패키지 리플로우 공정용 폴리이미드 필름 및 그 제조 방법에 관하여 상세히 설명하면 다음과 같다.
Hereinafter, a polyimide film for reflowing a semiconductor package according to a preferred embodiment of the present invention and a method of manufacturing the same will be described in detail with reference to the accompanying drawings.

도 1은 본 발명의 실시예에 따른 반도체 패키지 리플로우 공정용 폴리이미드 필름을 나타낸 단면도이다.1 is a cross-sectional view illustrating a polyimide film for a semiconductor package reflow process according to an embodiment of the present invention.

도 1을 참조하면, 본 발명의 실시예에 따른 반도체 패키지 리플로우 공정용 폴리이미드 필름(100)은 비열가소성 폴리이미드층(120), 열가소성 폴리이미드층(140) 및 점착층(160)을 포함한다.
Referring to FIG. 1, a polyimide film 100 for a semiconductor package reflow process according to an embodiment of the present invention includes a non-thermoplastic polyimide layer 120, a thermoplastic polyimide layer 140, and an adhesive layer 160 do.

비열가소성 폴리이미드층(120)은 폴리이미드 필름(100)의 최 하부에 배치된다. 이때, 비열가소성 폴리이미드층(120)은 반도체 패키지 리플로우 공정 온도인 대략 260℃ 이상의 온도를 견디기 위해 사용되며, 열경화성 폴리이미드일 수 있으나, 이에 제한되는 것은 아니다.
The non-thermoplastic polyimide layer 120 is disposed at the bottom of the polyimide film 100. At this time, the non-thermoplastic polyimide layer 120 is used to withstand a temperature of about 260 ° C or more, which is a semiconductor package reflow process temperature, and may be a thermosetting polyimide, but is not limited thereto.

열가소성 폴리이미드층(140)은 비열가소성 폴리이미드층(120) 상에 적층되며, 리플로우 공정 온도 이하의 유리전이온도를 갖는다. 이때, 열가소성 폴리이미드층(140)의 표면은 카르복실기(carboxyl group)로 개질 처리된다.The thermoplastic polyimide layer 140 is laminated on the non-thermoplastic polyimide layer 120 and has a glass transition temperature below the reflow process temperature. At this time, the surface of the thermoplastic polyimide layer 140 is reformed into a carboxyl group.

이때, 열가소성 폴리이미드층(140)은 리플로우 공정 온도 이하, 보다 바람직하게는 260℃ 이하의 유리전이온도를 갖는 것이 좋다.At this time, it is preferable that the thermoplastic polyimide layer 140 has a glass transition temperature of not more than the reflow process temperature, more preferably not more than 260 deg.

이와 같이, 열가소성 폴리이미드층(140)으로 260℃ 이하의 유리전이온도를 갖는 것을 이용하게 되면, 리플로우 공정시에는 열가소성 폴리이미드층(140)이 녹아 고무처럼 유연한 성질을 가짐에 따라 점착층(160)과의 접착력을 향상시킬 수 있게 되고, 리플로우 공정을 완료한 후에는 딱딱한 상태를 유지하게 되므로, 이형성이 향상되어 반도체 칩(미도시)과의 탈부착이 용이해질 수 있게 된다.If the thermoplastic polyimide layer 140 having a glass transition temperature of 260 DEG C or less is used, the thermoplastic polyimide layer 140 melts to be flexible as a rubber in the reflow process, 160 can be improved and the rigidity can be maintained after the reflow process is completed. Therefore, the releasability can be improved, and detachment and attachment with the semiconductor chip (not shown) can be facilitated.

이를 위해, 열가소성 폴리이미드층(140)은 에테르기, 케톤기 및 메틸기 중 어느 하나가 있는 방향족 디아민과 에테르기, 케톤기 및 메틸기 중 어느 하나가 있는 방향족 디안하이드리드(aromatic dianhydride)를 유기 용매에 합성하여 제조된 폴리아믹산을 이용하는 것이 바람직하다.To this end, the thermoplastic polyimide layer 140 is formed by mixing an aromatic dianhydride having any one of an ether group, a ketone group and a methyl group and an aromatic dianhydride having an ether group, a ketone group and a methyl group in an organic solvent It is preferable to use a polyamic acid prepared by synthesis.

이때, 방향족 디아민은 하기의 화학식 1로 표기되는 3,3'-디메틸-[1,1'-비페닐]-4,4'-디아민을 포함한다.
At this time, the aromatic diamine includes 3,3'-dimethyl- [1,1'-biphenyl] -4,4'-diamine represented by the following formula (1).

[화학식 1][Chemical Formula 1]

Figure 112016084519389-pat00001

Figure 112016084519389-pat00001

또한, 방향족 디안하이드리드는 하기 화학식 2로 표기되는 3,3', 4,4'-벤조페논테트라카르복실디안하이드리드(3,3', 4,4'-benzophenontetracarbolxylic dianhydride)을 포함한다.
Further, the aromatic dianhydride includes 3,3 ', 4,4'-benzophenonetetracarboxylic dianhydride represented by the following formula (2).

[화학식 2](2)

Figure 112016084519389-pat00002

Figure 112016084519389-pat00002

그리고, 유기 용매는 NMP(N-메틸-2-피롤리돈), 톨루엔, 디메틸 설폭사이드(Dimethyl Sulfoxide : DMSO), 에틸 락테이트(Ethyl Lactate ; EL) 등에서 선택된 1종 이상이 이용될 수 있으나, 이에 제한되는 것은 아니다.
The organic solvent may be at least one selected from NMP (N-methyl-2-pyrrolidone), toluene, dimethyl sulfoxide (DMSO), and ethyl lactate (EL) But is not limited thereto.

전술한 바와 같이, 본 발명에서는 열가소성 폴리이미드층(140)으로 에테르기, 케톤기 및 메틸기 중 어느 하나가 있는 방향족 디아민과 에테르기, 케톤기 및 메틸기 중 어느 하나가 있는 방향족 디안하이드리드(aromatic dianhydride)를 유기 용매에 합성하여 제조된 폴리아믹산을 이용함으로써, 열가소성 폴리이미드층(140)이 260℃ 이하의 낮은 유리전이온도를 가질 수 있게 된다.As described above, in the present invention, an aromatic dianhydride having any one of an ether group, a ketone group, and a methyl group, and an aromatic dianhydride having an ether group, a ketone group, and a methyl group as the thermoplastic polyimide layer 140 ) To an organic solvent, the thermoplastic polyimide layer 140 can have a low glass transition temperature of 260 ° C or less.

또한, 본 발명에서와 같이, 열가소성 폴리이미드층(140)으로 표면이 카르복실기로 개질 처리된 것을 이용하게 되면, 카르복실기에 의해 열가소성 폴리이미드층(140)과 점착층(160) 간의 접착력을 향상시킬 수 있게 된다.If the surface of the thermoplastic polyimide layer 140 modified with a carboxyl group is used as in the present invention, adhesion between the thermoplastic polyimide layer 140 and the adhesive layer 160 can be improved by a carboxyl group .

이러한 열가소성 폴리이미드층(140)은 폴리아믹산에 소량의 KOH를 첨가한 후, 300 ~ 400℃에서 열처리를 실시하게 되면, 하기의 반응식 1과 같이 표면이 카르복실기로 개질 처리된다. 다시 말해, 폴리아믹산은 300 ~ 400℃의 열처리 과정을 거치는 것에 의해 이미드화 반응이 일어나 폴리이미드가 된다.
When a small amount of KOH is added to the polyamic acid, the thermoplastic polyimide layer 140 is subjected to heat treatment at 300 to 400 ° C., and the surface is modified to a carboxyl group as shown in the following reaction formula 1. In other words, the polyamic acid is subjected to a heat treatment process at 300 to 400 ° C to cause an imidization reaction to become polyimide.

[반응식 1][Reaction Scheme 1]

Figure 112016084519389-pat00003

Figure 112016084519389-pat00003

이때, KOH는 폴리아믹산 100 중량부에 대하여, 0.5 ~ 3 중량부의 함량비로 첨가되는 것이 바람직하다. KOH의 첨가량이 0.5 중량부 미만일 경우에는 표면 개질 처리 효과를 제대로 발휘하는데 어려움이 따를 수 있다. 반대로, KOH의 첨가량이 3 중량부를 초과할 경우에는 KOH의 과량 첨가로 인하여 폴리아믹산 또는 폴리이미드의 이미드 구조가 깨져서 폴리이미드의 물리적 및 화학성 물성이 저하되므로, 바람직하지 못하다.
At this time, KOH is preferably added in an amount of 0.5 to 3 parts by weight based on 100 parts by weight of the polyamic acid. If the addition amount of KOH is less than 0.5 part by weight, it may be difficult to exhibit the effect of the surface modification treatment properly. On the contrary, when the amount of KOH added is more than 3 parts by weight, the imide structure of the polyamic acid or the polyimide is broken due to the excessive addition of KOH, which deteriorates the physical and chemical properties of the polyimide.

점착층(160)은 열가소성 폴리이미드층(140) 상에 부착된다. 이러한 점착층(160)은 아크릴계 점착제, 고무계 점착제, 실리콘계 점착제, 폴리비닐에테르 등의 각종 점착제가 사용될 수 있다. 이 중에서도 반도체 칩에 대한 접착성 및 박리 후의 세정성 등을 고려할 때, (메트)아크릴계 중합체를 베이스 중합체로 하는 (메트)아크릴계 점착제가 보다 바람직하다.
The adhesive layer 160 is deposited on the thermoplastic polyimide layer 140. As the adhesive layer 160, various pressure-sensitive adhesives such as an acrylic pressure-sensitive adhesive, a rubber pressure-sensitive adhesive, a silicone pressure-sensitive adhesive, and a polyvinyl ether can be used. Among them, a (meth) acrylic pressure-sensitive adhesive comprising a (meth) acrylic polymer as a base polymer is more preferable in view of adhesiveness to a semiconductor chip and cleaning properties after peeling.

전술한 본 발명의 실시예에 따른 반도체 패키지 리플로우 공정용 폴리이미드 필름은 열가소성 폴리이미드층으로 에테르기, 케톤기 및 메틸기 중 어느 하나가 있는 방향족 디아민과 에테르기, 케톤기 및 메틸기 중 어느 하나가 있는 방향족 디안하이드리드(aromatic dianhydride)를 유기 용매에 합성하여 제조된 폴리아믹산을 이용함으로써, 열가소성 폴리이미드층이 260℃ 이하의 낮은 유리전이온도를 가질 수 있게 된다.The polyimide film for a semiconductor package reflow process according to the above-described embodiment of the present invention is characterized in that any one of an aromatic diamine having an ether group, a ketone group and a methyl group and an ether group, a ketone group and a methyl group By using a polyamic acid prepared by synthesizing an aromatic dianhydride in an organic solvent, the thermoplastic polyimide layer can have a low glass transition temperature of 260 캜 or less.

이 결과, 본 발명의 실시예에 따른 반도체 패키지 리플로우 공정용 폴리이미드 필름은 260℃ 이하의 유리전이온도를 갖는 열가소성 폴리이미드층을 적용함으로써, 리플로우 공정을 완료한 후 이형성 확보로 반도체 칩과의 탈부착이 용이해질 수 있다.As a result, the polyimide film for the semiconductor package reflow process according to the embodiment of the present invention is formed by applying the thermoplastic polyimide layer having a glass transition temperature of 260 캜 or less, Can be easily detached and attached.

또한, 본 발명의 실시예에 따른 반도체 패키지 리플로우 공정용 폴리이미드 필름은 표면이 카르복실기로 개질 처리된 열가소성 폴리이미드층을 적용하는 것에 의해, 표면 개질을 통한 활성화로 카르복실기에 의해 열가소성 폴리이미드층과 점착층 간의 접착력 향상으로 우수한 접합 신뢰성을 확보할 수 있다.
Further, the polyimide film for semiconductor package reflow process according to the embodiment of the present invention can be obtained by applying a thermoplastic polyimide layer whose surface has been modified with a carboxyl group, thereby forming a thermoplastic polyimide layer It is possible to secure an excellent bonding reliability by improving the adhesive force between the adhesive layers.

한편, 도 2는 본 발명의 실시예에 따른 반도체 패키지 리플로우 공정용 폴리이미드 필름 제조 방법을 나타낸 공정 순서도이다.2 is a process flow diagram illustrating a method for fabricating a polyimide film for a semiconductor package reflow process according to an embodiment of the present invention.

도 2를 참조하면, 본 발명의 실시예에 따른 반도체 패키지 리플로우 공정용 폴리이미드 필름 제조 방법은 비열가소성 폴리이미드층 마련 단계(S110), 비열가소성 폴리이미드층 상에 열가소성 폴리이미드층 부착 단계(S120) 및 열가소성 폴리이미드층 상에 점착층 부착 단계(S130)를 포함한다.
Referring to FIG. 2, a method for fabricating a polyimide film for a semiconductor package reflow process according to an embodiment of the present invention includes a non-thermoplastic polyimide layer preparing step (S110), a thermoplastic polyimide layer attaching step S120) and a step of attaching an adhesive layer (S130) on the thermoplastic polyimide layer.

비열가소성 폴리이미드층 마련Preparing a non-thermoplastic polyimide layer

비열가소성 폴리이미드층 마련 단계(S110)에서는 비열가소성 폴리이미드층을 마련한다. 이러한 비열가소성 폴리이미드층은 폴리이미드 필름의 최 하부에 배치된다. 이때, 비열가소성 폴리이미드층은 반도체 패키지 리플로우 공정 온도인 대략 260℃ 이상의 온도를 견디기 위해 사용되며, 열경화성 폴리이미드일 수 있으나, 이에 제한되는 것은 아니다.
In the non-thermoplastic polyimide layer preparing step (S110), a non-thermoplastic polyimide layer is provided. This non-thermoplastic polyimide layer is disposed at the bottom of the polyimide film. At this time, the non-thermoplastic polyimide layer is used to withstand a temperature of about 260 ° C or more, which is a semiconductor package reflow process temperature, and may be a thermosetting polyimide, but is not limited thereto.

비열가소성 폴리이미드층 상에 열가소성 폴리이미드층 부착Adhesion of the thermoplastic polyimide layer on the non-thermoplastic polyimide layer

비열가소성 폴리이미드층 상에 열가소성 폴리이미드층 부착 단계(S120)에서는 비열가소성 폴리이미드층 상에 리플로우 공정 온도 이하의 유리전이온도를 가지며, 표면이 카르복실기로 개질 처리된 열가소성 폴리이미드층을 부착한다.In the step (S120) of attaching the thermoplastic polyimide layer on the non-thermoplastic polyimide layer, a thermoplastic polyimide layer having a glass transition temperature lower than the reflow process temperature and whose surface is modified with a carboxyl group is deposited on the non-thermoplastic polyimide layer .

이때, 열가소성 폴리이미드층은 리플로우 공정 온도 이하, 보다 바람직하게는 260℃ 이하의 유리전이온도를 갖는 것이 좋다.At this time, it is preferable that the thermoplastic polyimide layer has a glass transition temperature of not more than the reflow process temperature, more preferably not more than 260 캜.

이와 같이, 열가소성 폴리이미드층으로 260℃ 이하의 유리전이온도를 갖는 것을 이용하게 되면, 리플로우 공정시에는 열가소성 폴리이미드층이 녹아 고무처럼 유연한 성질을 가짐에 따라 점착층과의 접착력을 향상시킬 수 있게 되고, 리플로우 공정을 완료한 후에는 딱딱한 상태를 유지하게 되므로, 이형성이 향상되어 반도체 칩과의 탈부착이 용이해질 수 있게 된다.When a thermoplastic polyimide layer having a glass transition temperature of 260 DEG C or less is used, the thermoplastic polyimide layer melts and is flexible as a rubber in the reflow process, so that the adhesive strength to the adhesive layer can be improved And after the reflow process is completed, the semiconductor chip is maintained in a rigid state, so that the releasability is improved and the semiconductor chip can be easily attached to and detached from the semiconductor chip.

이를 위해, 열가소성 폴리이미드층은 에테르기, 케톤기 및 메틸기 중 어느 하나가 있는 방향족 디아민과 에테르기, 케톤기 및 메틸기 중 어느 하나가 있는 방향족 디안하이드리드(aromatic dianhydride)를 유기 용매에 합성하여 제조된 폴리아믹산을 이용하는 것이 바람직하다.For this purpose, the thermoplastic polyimide layer may be prepared by synthesizing an aromatic dianhydride having an ether group, a ketone group, or a methyl group, and an aromatic dianhydride having an ether group, a ketone group or a methyl group in an organic solvent It is preferable to use polyamic acid.

이때, 방향족 디아민은 3,3'-디메틸-[1,1'-비페닐]-4,4'-디아민을 포함한다.At this time, the aromatic diamine includes 3,3'-dimethyl- [1,1'-biphenyl] -4,4'-diamine.

또한, 방향족 디안하이드리드는 3,3', 4,4'-벤조페논테트라카르복실디안하이드리드(3,3', 4,4'-benzophenontetracarbolxylic dianhydride)을 포함한다.In addition, the aromatic dianhydrides include 3,3 ', 4,4'-benzophenonetetracarbolxylic dianhydride (3,3', 4,4'-benzophenontetracarboxylic dianhydride).

그리고, 유기 용매는 NMP(N-메틸-2-피롤리돈), 톨루엔, 디메틸 설폭사이드(Dimethyl Sulfoxide : DMSO), 에틸 락테이트(Ethyl Lactate ; EL) 등에서 선택된 1종 이상이 이용될 수 있으나, 이에 제한되는 것은 아니다.
The organic solvent may be at least one selected from NMP (N-methyl-2-pyrrolidone), toluene, dimethyl sulfoxide (DMSO), and ethyl lactate (EL) But is not limited thereto.

또한, 본 발명에서와 같이, 열가소성 폴리이미드층으로 표면이 카르복실기로 개질 처리된 것을 이용하게 되면, 카르복실기에 의해 열가소성 폴리이미드층과 점착층 간의 접착력을 향상시킬 수 있게 된다.In addition, as in the present invention, if the surface of the thermoplastic polyimide layer is modified with a carboxyl group, the adhesion between the thermoplastic polyimide layer and the adhesive layer can be improved by the carboxyl group.

이러한 열가소성 폴리이미드층은 폴리아믹산에 소량의 KOH를 첨가한 후, 300 ~ 400℃에서 열처리를 실시하게 되면, 하기의 반응식 1과 같이 표면이 카르복실기로 개질 처리된다. 다시 말해, 폴리아믹산은 300 ~ 400℃의 열처리 과정을 거치는 것에 의해 이미드화 반응이 일어나 폴리이미드가 된다.
When a small amount of KOH is added to the polyamic acid, the thermoplastic polyimide layer is subjected to heat treatment at 300 to 400 ° C., and the surface is modified to a carboxyl group as shown in the following reaction formula (1). In other words, the polyamic acid is subjected to a heat treatment process at 300 to 400 ° C to cause an imidization reaction to become polyimide.

[반응식 1][Reaction Scheme 1]

Figure 112016084519389-pat00004

Figure 112016084519389-pat00004

이때, KOH는 폴리아믹산 100 중량부에 대하여, 0.5 ~ 3 중량부의 함량비로 첨가되는 것이 바람직하다. KOH의 첨가량이 0.5 중량부 미만일 경우에는 표면 개질 처리 효과를 제대로 발휘하는데 어려움이 따를 수 있다. 반대로, KOH의 첨가량이 3 중량부를 초과할 경우에는 KOH의 과량 첨가로 인하여 폴리아믹산 또는 폴리이미드의 이미드 구조가 깨져서 폴리이미드의 물리적 및 화학성 물성이 저하되므로, 바람직하지 못하다.
At this time, KOH is preferably added in an amount of 0.5 to 3 parts by weight based on 100 parts by weight of the polyamic acid. If the addition amount of KOH is less than 0.5 part by weight, it may be difficult to exhibit the effect of the surface modification treatment properly. On the contrary, when the amount of KOH added is more than 3 parts by weight, the imide structure of the polyamic acid or the polyimide is broken due to the excessive addition of KOH, which deteriorates the physical and chemical properties of the polyimide.

열가소성 폴리이미드층 상에 점착층 부착Adhesion of an adhesive layer on the thermoplastic polyimide layer

열가소성 폴리이미드층 상에 점착층 부착 단계(S130)에서는 열가소성 폴리이미드층 상에 점착층을 부착한다.In the step of attaching the adhesive layer on the thermoplastic polyimide layer (S130), an adhesive layer is attached on the thermoplastic polyimide layer.

이때, 점착층은 아크릴계 점착제, 고무계 점착제, 실리콘계 점착제, 폴리비닐에테르 등의 각종 점착제가 사용될 수 있다. 이 중에서도 반도체 칩에 대한 접착성 및 박리 후의 세정성 등을 고려할 때, (메트)아크릴계 중합체를 베이스 중합체로 하는 (메트)아크릴계 점착제가 보다 바람직하다.
At this time, various kinds of pressure-sensitive adhesives such as an acrylic pressure-sensitive adhesive, a rubber pressure-sensitive adhesive, a silicone pressure-sensitive adhesive, and a polyvinyl ether can be used as the pressure-sensitive adhesive layer. Among them, a (meth) acrylic pressure-sensitive adhesive comprising a (meth) acrylic polymer as a base polymer is more preferable in view of adhesiveness to a semiconductor chip and cleaning properties after peeling.

상기의 과정(S110 ~ S130)에 의해 제조되는 본 발명의 실시예에 따른 반도체 패키지 리플로우 공정용 폴리이미드 필름은 열가소성 폴리이미드층으로 에테르기, 케톤기 및 메틸기 중 어느 하나가 있는 방향족 디아민과 에테르기, 케톤기 및 메틸기 중 어느 하나가 있는 방향족 디안하이드리드(aromatic dianhydride)를 유기 용매에 합성하여 제조된 폴리아믹산을 이용함으로써, 열가소성 폴리이미드층이 260℃ 이하의 낮은 유리전이온도를 가질 수 있게 된다.The polyimide film for semiconductor package reflow process according to the embodiment of the present invention manufactured by the above-described processes (S110 to S130) is a thermoplastic polyimide layer comprising an aromatic diamine having any one of an ether group, a ketone group and a methyl group, By using a polyamic acid prepared by synthesizing an aromatic dianhydride having one of a group, a ketone group and a methyl group in an organic solvent, the thermoplastic polyimide layer can have a low glass transition temperature do.

이 결과, 본 발명의 실시예에 따른 방법으로 제조되는 반도체 패키지 리플로우 공정용 폴리이미드 필름은 260℃ 이하의 유리전이온도를 갖는 열가소성 폴리이미드층을 적용함으로써, 리플로우 공정을 완료한 후 이형성 확보로 반도체 칩과의 탈부착이 용이해질 수 있다.As a result, the polyimide film for semiconductor package reflow process manufactured by the method according to the embodiment of the present invention can be manufactured by applying a thermoplastic polyimide layer having a glass transition temperature of 260 캜 or less, So that detachment of the semiconductor chip from the semiconductor chip can be facilitated.

또한, 본 발명의 실시예에 따른 방법으로 제조되는 반도체 패키지 리플로우 공정용 폴리이미드 필름은 표면이 카르복실기로 개질 처리된 열가소성 폴리이미드층을 적용하는 것에 의해, 표면 개질을 통한 활성화로 카르복실기에 의해 열가소성 폴리이미드층과 점착층 간의 접착력 향상으로 우수한 접합 신뢰성을 확보할 수 있다.
In addition, the polyimide film for semiconductor package reflow process manufactured by the method according to the embodiment of the present invention can be produced by applying a thermoplastic polyimide layer whose surface is modified with a carboxyl group, The bonding strength between the polyimide layer and the pressure-sensitive adhesive layer can be improved and excellent bonding reliability can be ensured.

실시예Example

이하, 본 발명의 이해를 돕기 위하여 바람직한 실시예를 설명한다. 하지만 하기 실시예는 본 발명을 예시하는 것일 뿐 본 발명의 범주 및 기술사상 범위 내에서 다양한 변경 및 수정이 가능함은 당업자에게 명백한 것이며, 이러한 변형 및 수정이 첨부된 특허 청구 범위에 속하는 것도 당연한 것이다.
Hereinafter, a preferred embodiment will be described in order to facilitate understanding of the present invention. It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit and scope of the invention as defined by the appended claims.

1. 폴리이미드 필름 제조1. Production of polyimide film

실시예 1Example 1

3,3'-디메틸-[1,1'-비페닐]-4,4'-디아민 36.6g 및 3,3', 4,4'-벤조페논테트라카르복실디안하이드리드 53.4g을 NMP 410g에서 중합하여 폴리아믹산을 합성하였다.36.6 g of 3,3'-dimethyl- [1,1'-biphenyl] -4,4'-diamine and 53.4 g of 3,3 ', 4,4'-benzophenone tetracarboxylic dianhydride were dissolved in 410 g of NMP To synthesize polyamic acid.

다음으로, 폴리아믹산 100 중량부에 대하여, KOH 2 중량부를 첨가한 폴리아믹산 조성물을 열경화성 폴리이미드 필름 상에 6㎛의 두께로 도포한 다음 350℃에서 열처리하여 표면이 카르복실기로 개질된 열가소성 폴리이미드 필름을 형성하였다.Next, a polyamic acid composition to which 2 parts by weight of KOH was added to 100 parts by weight of polyamic acid was coated on a thermosetting polyimide film to a thickness of 6 mu m and then heat-treated at 350 DEG C to form a thermoplastic polyimide film .

다음으로, 열가소성 폴리이미드 필름 상에 아크릴계 점착 필름을 부착하여 폴리이미드 필름을 제조하였다.
Next, an acrylic adhesive film was adhered on the thermoplastic polyimide film to prepare a polyimide film.

실시예 2Example 2

폴리아믹산 100 중량부에 대하여, KOH를 1.5 중량부를 첨가한 후, 340℃에서 열처리한 것을 제외하고는 실시예 1과 동일한 방법으로 폴리이미드 필름을 제조하였다.
A polyimide film was prepared in the same manner as in Example 1, except that 1.5 parts by weight of KOH was added to 100 parts by weight of polyamic acid and then heat-treated at 340 占 폚.

실시예 3Example 3

폴리아믹산 100 중량부에 대하여, KOH를 3.0 중량부를 첨가한 후, 360℃에서 열처리한 것을 제외하고는 실시예 1과 동일한 방법으로 폴리이미드 필름을 제조하였다.
A polyimide film was prepared in the same manner as in Example 1, except that 3.0 parts by weight of KOH was added to 100 parts by weight of polyamic acid and then heat-treated at 360 占 폚.

비교예 1Comparative Example 1

3,3'-디메틸-[1,1'-비페닐]-4,4'-디아민 36.6g 및 3,3', 4,4'-벤조페논테트라카르복실디안하이드리드 53.4g을 NMP 410g에서 중합하여 폴리아믹산을 합성한 후, 폴리아믹산을 열경화성 폴리이미드 필름 상에 6㎛의 두께로 도포한 다음 350℃에서 열처리하여 열가소성 폴리이미드 필름을 형성하였다.36.6 g of 3,3'-dimethyl- [1,1'-biphenyl] -4,4'-diamine and 53.4 g of 3,3 ', 4,4'-benzophenone tetracarboxylic dianhydride were dissolved in 410 g of NMP After the polyamic acid was synthesized by polymerizing, polyamic acid was applied on the thermosetting polyimide film to a thickness of 6 탆 and then heat-treated at 350 캜 to form a thermoplastic polyimide film.

다음으로, 열가소성 폴리이미드 필름 상에 아크릴계 점착 필름을 부착하여 폴리이미드 필름을 제조하였다.
Next, an acrylic adhesive film was adhered on the thermoplastic polyimide film to prepare a polyimide film.

2. 물성 평가2. Property evaluation

표 1은 실시예 1 ~ 3 및 비교예 1에 따라 제조된 폴리이미드 필름의 물성 평가 결과를 나타낸 것이다.
Table 1 shows the results of evaluating the physical properties of the polyimide films prepared according to Examples 1 to 3 and Comparative Example 1.

1) 유리전이온도1) Glass transition temperature

TA사의 Q400을 이용하여 열가소성 폴리이미드층의 유리전이온도를 측정하였다.
The glass transition temperature of the thermoplastic polyimide layer was measured using Q400 of TA Corporation.

2) 접착력2) Adhesion

폴리이미드 필름을 100mm(가로) × 100mm(세로)로 절단한 다음 260℃에 500kgf의 압력으로 압착 가열한 후, IPC 650 방법에 의거하여 열가소성 폴리이미드 필름과 점착 필름 간의 접착력을 측정하였다.
The polyimide film was cut into 100 mm (width) x 100 mm (length), and then pressed and heated at 260 ° C under a pressure of 500 kgf, and the adhesion between the thermoplastic polyimide film and the adhesive film was measured according to the IPC 650 method.

[표 1][Table 1]

Figure 112016084519389-pat00005
Figure 112016084519389-pat00005

표 1을 참조하면, 실시예 1 ~ 3에 따라 제조된 폴리이미드 필름의 경우, 열가소성 폴리이미드층의 유리전이온도가 196 ~ 203℃로 측정되어 목표값인 260℃ 이하를 모두 만족하는 것을 확인할 수 있다. 이 결과, 실시예 1 ~ 3에 따라 제조된 폴리이미드 필름의 경우, 열가소성 폴리이미드 필름과 점착 필름 간의 접착력이 1.3 ~ 1.5kgf/cm로 측정되어 우수한 접착력을 갖는 것을 확인하였다.Referring to Table 1, in the case of the polyimide film produced according to Examples 1 to 3, it was confirmed that the glass transition temperature of the thermoplastic polyimide layer was measured at 196 to 203 ° C and satisfied the target value of 260 ° C or less have. As a result, in the case of the polyimide film produced according to Examples 1 to 3, the adhesive force between the thermoplastic polyimide film and the pressure-sensitive adhesive film was measured to be 1.3 to 1.5 kgf / cm.

반면, 비교예 1에 따라 제조된 폴리이미드 필름의 경우, 열가소성 폴리이미드층의 유리전이온도가 목표값을 초과하는 274℃를 갖는데 기인하여 열가소성 폴리이미드 필름과 접착 필름 간의 접착력이 0.8kgf/cm에 불과한 것을 확인하였다.
On the other hand, in the case of the polyimide film produced according to Comparative Example 1, the adhesive force between the thermoplastic polyimide film and the adhesive film was 0.8 kgf / cm 2 due to the glass transition temperature of the thermoplastic polyimide layer exceeding the target value of 274 ° C .

이상에서는 본 발명의 실시예를 중심으로 설명하였지만, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 기술자의 수준에서 다양한 변경이나 변형을 가할 수 있다. 이러한 변경과 변형은 본 발명이 제공하는 기술 사상의 범위를 벗어나지 않는 한 본 발명에 속한다고 할 수 있다. 따라서 본 발명의 권리범위는 이하에 기재되는 청구범위에 의해 판단되어야 할 것이다.
Although the preferred embodiments of the present invention have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as disclosed in the accompanying claims. These changes and modifications may be made without departing from the scope of the present invention. Accordingly, the scope of the present invention should be determined by the following claims.

100 : 폴리이미드 필름
120 : 비열가소성 폴리이미드층
140 : 열가소성 폴리이미드층
160 : 점착층
100: polyimide film
120: non-thermoplastic polyimide layer
140: thermoplastic polyimide layer
160: Adhesive layer

Claims (10)

비열가소성 폴리이미드층;
상기 비열가소성 폴리이미드층 상에 적층되며, 리플로우 공정 온도 이하의 유리전이온도를 갖는 열가소성 폴리이미드층; 및
상기 열가소성 폴리이미드층 상에 부착된 점착층;을 포함하며,
상기 열가소성 폴리이미드층의 표면은 카르복실기로 개질 처리되되,
상기 열가소성 폴리이미드층은 에테르기, 케톤기 및 메틸기 중 어느 하나가 있는 방향족 디아민과 에테르기, 케톤기 및 메틸기 중 어느 하나가 있는 방향족 디안하이드리드(aromatic dianhydride)를 유기 용매에 합성하여 제조된 폴리아믹산이 이용되며,
상기 열가소성 폴리이미드층은 상기 폴리아믹산에 KOH를 첨가하고, 300 ~ 400℃에서 열처리하는 것에 의해 표면이 카르복실기로 개질 처리된 것을 특징으로 하는 반도체 패키지 리플로우 공정용 폴리이미드 필름.
A non-thermoplastic polyimide layer;
A thermoplastic polyimide layer laminated on the non-thermoplastic polyimide layer, the thermoplastic polyimide layer having a glass transition temperature lower than the reflow process temperature; And
And an adhesive layer adhered on the thermoplastic polyimide layer,
The surface of the thermoplastic polyimide layer is modified with a carboxyl group,
Wherein the thermoplastic polyimide layer is formed of an aromatic diamine having one of an ether group, a ketone group and a methyl group, and an aromatic dianhydride having an ether group, a ketone group and a methyl group, Mix acid is used,
Wherein the thermoplastic polyimide layer is modified to have a carboxyl group on its surface by adding KOH to the polyamic acid and heat-treating the polyamic acid at 300 to 400 ° C.
제1항에 있어서,
상기 열가소성 폴리이미드층은
260℃ 이하의 유리전이온도를 갖는 것을 특징으로 하는 반도체 패키지 리플로우 공정용 폴리이미드 필름.
The method according to claim 1,
The thermoplastic polyimide layer
Wherein the polyimide film has a glass transition temperature of 260 DEG C or less.
삭제delete 제1항에 있어서,
상기 방향족 디아민은
3,3'-디메틸-[1,1'-비페닐]-4,4'-디아민을 포함하고,
상기 방향족 디안하이드리드는 3,3', 4,4'-벤조페논테트라카르복실디안하이드리드(3,3', 4,4'-benzophenontetracarbolxylic dianhydride)을 포함하는 것을 특징으로 하는 반도체 패키지 리플로우 공정용 폴리이미드 필름.
The method according to claim 1,
The aromatic diamine
3,3'-dimethyl- [1,1'-biphenyl] -4,4'-diamine,
Characterized in that the aromatic dianhydride comprises 3,3 ', 4,4'-benzophenonetetracarbolxyl dianhydride (3,3', 4,4'-benzophenontetracarbolxyl dianhydride). Polyimide film.
삭제delete (a) 비열가소성 폴리이미드층을 마련하는 단계;
(b) 상기 비열가소성 폴리이미드층 상에 리플로우 공정 온도 이하의 유리전이온도를 가지며, 표면이 카르복실기로 개질 처리된 열가소성 폴리이미드층을 부착하는 단계; 및
(c) 상기 열가소성 폴리이미드층 상에 점착층을 부착하는 단계;를 포함하며,
상기 (b) 단계에서, 상기 열가소성 폴리이미드층은 에테르기, 케톤기 및 메틸기 중 어느 하나가 있는 방향족 디아민과 에테르기, 케톤기 및 메틸기 중 어느 하나가 있는 방향족 디안하이드리드(aromatic dianhydride)를 유기 용매에 합성하여 폴리아믹산을 제조하는 것에 의해, 260℃ 이하의 유리전이온도를 갖고,
상기 열가소성 폴리이미드층은 상기 폴리아믹산에 KOH를 첨가하고, 300 ~ 400℃에서 열처리하는 것에 의해 표면이 카르복실기로 개질 처리된 것을 특징으로 하는 반도체 패키지 리플로우 공정용 폴리이미드 필름 제조 방법.
(a) providing a non-thermoplastic polyimide layer;
(b) attaching a thermoplastic polyimide layer having a glass transition temperature lower than the reflow process temperature on the non-thermoplastic polyimide layer and having a surface modified with a carboxyl group; And
(c) attaching an adhesive layer on the thermoplastic polyimide layer,
In the step (b), the thermoplastic polyimide layer may contain an aromatic dianhydride having any one of an ether group, a ketone group and a methyl group and an aromatic dianhydride having an ether group, a ketone group and a methyl group, And a polyamic acid is produced by synthesizing the polyamic acid with a solvent to have a glass transition temperature of 260 DEG C or lower,
Wherein the thermoplastic polyimide layer is formed by modifying the surface of the thermoplastic polyimide layer to a carboxyl group by adding KOH to the polyamic acid and performing heat treatment at 300 to 400 ° C.
삭제delete 제6항에 있어서,
상기 방향족 디아민은
3,3'-디메틸-[1,1'-비페닐]-4,4'-디아민을 포함하고,
상기 방향족 디안하이드리드는 3,3', 4,4'-벤조페논테트라카르복실디안하이드리드(3,3', 4,4'-benzophenontetracarbolxylic dianhydride)을 포함하는 것을 특징으로 하는 반도체 패키지 리플로우 공정용 폴리이미드 필름 제조 방법.
The method according to claim 6,
The aromatic diamine
3,3'-dimethyl- [1,1'-biphenyl] -4,4'-diamine,
Characterized in that the aromatic dianhydride comprises 3,3 ', 4,4'-benzophenonetetracarbolxyl dianhydride (3,3', 4,4'-benzophenontetracarbolxyl dianhydride). / RTI >
삭제delete 제6항에 있어서,
상기 KOH는
상기 폴리아믹산 100 중량부에 대하여, 0.5 ~ 3 중량부로 첨가하는 것을 특징으로 하는 반도체 패키지 리플로우 공정용 폴리이미드 필름 제조 방법.
The method according to claim 6,
The KOH
Wherein the polyamic acid is added in an amount of 0.5 to 3 parts by weight based on 100 parts by weight of the polyamic acid.
KR1020160110930A 2016-08-30 2016-08-30 Polyimide film for semiconductor package reflow process and method of manufacturing the same KR101696347B1 (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
KR1020160110930A KR101696347B1 (en) 2016-08-30 2016-08-30 Polyimide film for semiconductor package reflow process and method of manufacturing the same
JP2019532901A JP6816286B2 (en) 2016-08-30 2017-06-29 Polyimide film for reflow process of semiconductor package and its manufacturing method
PCT/KR2017/006871 WO2018043897A1 (en) 2016-08-30 2017-06-29 Polyimide film for semiconductor package reflow process, and manufacturing method therefor
CN201780052747.3A CN109661719B (en) 2016-08-30 2017-06-29 Polyimide film for semiconductor packaging reflow process and preparation method thereof
US16/329,394 US11015089B2 (en) 2016-08-30 2017-06-29 Polyimide film for semiconductor package reflow process, and manufacturing method therefor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020160110930A KR101696347B1 (en) 2016-08-30 2016-08-30 Polyimide film for semiconductor package reflow process and method of manufacturing the same

Publications (1)

Publication Number Publication Date
KR101696347B1 true KR101696347B1 (en) 2017-01-13

Family

ID=57835385

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020160110930A KR101696347B1 (en) 2016-08-30 2016-08-30 Polyimide film for semiconductor package reflow process and method of manufacturing the same

Country Status (5)

Country Link
US (1) US11015089B2 (en)
JP (1) JP6816286B2 (en)
KR (1) KR101696347B1 (en)
CN (1) CN109661719B (en)
WO (1) WO2018043897A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11492519B2 (en) 2018-09-07 2022-11-08 Ipi Tech Inc Polyimide film for semiconductor package

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH091723A (en) * 1995-04-17 1997-01-07 Kanegafuchi Chem Ind Co Ltd Heat resisting bonding sheet
JP2002190502A (en) * 2000-12-22 2002-07-05 Tomoegawa Paper Co Ltd Bonding tape for semiconductor device
JP2010238852A (en) * 2009-03-31 2010-10-21 Mitsui Chemicals Inc Tape for manufacturing semiconductor and method for manufacturing semiconductor device

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3361589A (en) * 1964-10-05 1968-01-02 Du Pont Process for treating polyimide surface with basic compounds, and polyimide surface having thin layer of polyamide acid
JP3952196B2 (en) * 2003-06-25 2007-08-01 信越化学工業株式会社 Method for producing flexible metal foil polyimide laminate
TWI298076B (en) * 2004-04-30 2008-06-21 Eternal Chemical Co Ltd Precursor solution for polyimide/silica composite material, its manufacture method and polyimide/silica composite material having low volume shrinkage
US20050272608A1 (en) * 2004-06-08 2005-12-08 Mitsui Chemicals, Inc. Polyimide metal laminate and its production method
TWI377224B (en) 2004-07-27 2012-11-21 Kaneka Corp Polyimide film having high adhesiveness and production method therefor
TW200709751A (en) * 2005-08-31 2007-03-01 Thinflex Corp Polyimide copper foil laminate and method of producing the same
WO2007029609A1 (en) * 2005-09-05 2007-03-15 Kaneka Corporation Heat resistant adhesive sheet
KR101232587B1 (en) 2011-06-30 2013-02-12 에스케이씨코오롱피아이 주식회사 Polyimde Film and Method for Preparing the Same
CN103907179B (en) 2011-10-26 2017-07-07 日立化成株式会社 Backflow film, solder projection forming method, the forming method of solder engagement and semiconductor device
JP2013110402A (en) 2011-10-26 2013-06-06 Hitachi Chemical Co Ltd Reflow film, method for forming solder bump, method for forming solder join, and semiconductor device
JP6517146B2 (en) * 2013-11-01 2019-05-22 東レ・デュポン株式会社 Graphite laminate
JP2016143741A (en) 2015-01-30 2016-08-08 国立大学法人大阪大学 Method for mounting electronic component, board with electronic component and joining layer thereof, board with joining material layer, and sheet-like joining member
CN107004975B (en) 2015-02-19 2018-12-21 积水化学工业株式会社 The manufacturing method of connection structural bodies

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH091723A (en) * 1995-04-17 1997-01-07 Kanegafuchi Chem Ind Co Ltd Heat resisting bonding sheet
JP2002190502A (en) * 2000-12-22 2002-07-05 Tomoegawa Paper Co Ltd Bonding tape for semiconductor device
JP2010238852A (en) * 2009-03-31 2010-10-21 Mitsui Chemicals Inc Tape for manufacturing semiconductor and method for manufacturing semiconductor device

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
"Influence of Surface Treatment of Polyimide film on Adhesion Enhancement between Polyimide and Metal Films". Bulle. Korean Chem. Soc. 2007 Vol. 28, No. 2, pp.188* *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11492519B2 (en) 2018-09-07 2022-11-08 Ipi Tech Inc Polyimide film for semiconductor package

Also Published As

Publication number Publication date
CN109661719B (en) 2023-02-28
JP6816286B2 (en) 2021-01-20
US20190194496A1 (en) 2019-06-27
JP2019534578A (en) 2019-11-28
WO2018043897A1 (en) 2018-03-08
US11015089B2 (en) 2021-05-25
CN109661719A (en) 2019-04-19

Similar Documents

Publication Publication Date Title
TWI230567B (en) Printed circuit board and method of producing the same
TWI278471B (en) Adhesive polyimide resin and adhesive laminate
TWI780992B (en) Polyimide, adhesive, film-like adhesive material, adhesive layer, adhesive sheet, copper foil with resin, copper-clad laminate, printed wiring board, and multilayer wiring board, and method for producing the same
TW200423316A (en) Adhesive film for semiconductor, adhesive film attached on metal plate, wiring circuit and semiconductor device with the same, and the manufacturing method for semiconductor device
JP6303503B2 (en) Resin composition, cured film, laminated film, and method for manufacturing semiconductor device
CN108138013A (en) Temporary adhesion laminate film uses the substrate processome of temporary adhesion laminate film and the manufacturing method of multilayer board processome and the manufacturing method using their semiconductor devices
JP6834941B2 (en) Method for manufacturing resin composition, resin layer, permanent adhesive, temporary adhesive, laminated film, wafer processed product and electronic component or semiconductor device
KR101854722B1 (en) Manufacturing method of composite sheet with excellent heat resistance, chemical resistance and flexibility
KR101475139B1 (en) Mask sheet for manufacturing semiconductor device and manufacturing method of semiconductor device using the same
CN105612600A (en) Element-processing layered structure, method for manufacturing element-processing layered structure, and method for manufacturing thin element using same
TW201939698A (en) Temporary protective film for semiconductor encapsulation molding, lead frame provided with temporary protective film, encapsulated molded body provided with temporary protective film, and method for manufacturing semiconductor device
JP2003119440A (en) Adhesive film for semiconductor, lead frame having the adhesive film for semiconductor and semiconductor device
JP5632426B2 (en) Polyamic acid and non-thermoplastic polyimide resin
JPH0967559A (en) Adhesive tape for electronic part and liquid adhesive
KR101696347B1 (en) Polyimide film for semiconductor package reflow process and method of manufacturing the same
JP5382274B2 (en) Heat-sealable polyimide film and production method thereof, and polyimide metal laminate using heat-sealable polyimide film
JP7414301B2 (en) Polyimide film for semiconductor packages
JP2008030434A (en) Polyimide composite flexible sheet and its manufacturing method
JP4332739B2 (en) Method for producing flexible copper-clad laminate
JPH02272077A (en) Heat-resistant adhesive material
JP3986949B2 (en) Flexible metal laminate for flexible printed circuit board
JPH1192719A (en) Adhesive tape for electronic component
KR101392442B1 (en) Liquid adhesive for electronic parts and method for applying to a lead-frame using the same
JPH09316408A (en) Production of polyimide resin adhesive film
KR20050024396A (en) Adhesive film for semiconductor, metal sheet with such adhesive film, wiring substrate with adhesive film, semiconductor device, and method for manufacturing semiconductor device

Legal Events

Date Code Title Description
E701 Decision to grant or registration of patent right
GRNT Written decision to grant