KR101690867B1 - Output circuit and detection sensor - Google Patents

Output circuit and detection sensor Download PDF

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KR101690867B1
KR101690867B1 KR1020150054428A KR20150054428A KR101690867B1 KR 101690867 B1 KR101690867 B1 KR 101690867B1 KR 1020150054428 A KR1020150054428 A KR 1020150054428A KR 20150054428 A KR20150054428 A KR 20150054428A KR 101690867 B1 KR101690867 B1 KR 101690867B1
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transistor
terminal
output
circuit
resistor
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KR1020150054428A
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KR20160001612A (en
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타케시 히키치
지로 카미야
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파나소닉 디바이스 썬크스 주식회사
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/16—Modifications for eliminating interference voltages or currents
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)

Abstract

An object of the present invention is to provide an output circuit and a detection sensor capable of suppressing malfunction of an output transistor. The output transistor is connected between the external terminal and the wiring. An active clamp circuit is connected between the external terminal and the gate terminal of the output transistor, and a resistor is connected between the gate terminal of the output transistor and the wiring. An output control signal is supplied to the buffer circuit. The transistor is connected between the wiring and the gate terminal of the output transistor, and the output signal of the buffer circuit is supplied to the gate terminal. The transistor is connected between the gate terminal and the wiring of the output transistor, and an output signal is supplied to the gate terminal. The resistor is inserted between the gate terminal of the output transistor and the transistor.

Description

OUTPUT CIRCUIT AND DETECTION SENSOR < RTI ID = 0.0 >

The present invention relates to an output circuit and a detection sensor.

Conventionally, a detection sensor using light such as a light-emitting type or a reflection type has an output circuit for outputting a signal depending on the presence or absence of a detection target. The output circuit has a transistor connected to the output terminal, and current flows through the output transistor. The controller connected to the detection sensor determines the level of the output signal of the detection sensor in accordance with the level in the load connected to the output transistor. In such an output circuit, a driving circuit (output circuit) for driving a load such as a motor, for example, is connected to an output terminal of the output transistor in order to secure the immunity of the output transistor to noise or electrostatic discharge And a protection circuit for protecting the transistor (for example, see Patent Document 1).

Japanese Patent Laid-Open No. 2008-35067

In the output circuit, the transistor may be inadvertently turned on, that is, malfunction may occur. For example, in order to reduce power consumption, a MOS transistor, for example, may be used for the output transistor. The drain terminal of the MOS transistor is connected to the output terminal of the sensor and constitutes a so-called open drain output circuit. In this output circuit, when noise or the like is applied to the output terminal, the gate voltage of the MOS transistor is varied by the junction capacitance between the drain gates of the MOS transistor, and the transistor is unintentionally turned on.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and its object is to suppress malfunction of the output transistor.

An output circuit that solves the above problem is an output circuit designed to a detection sensor, comprising: an output transistor having a first terminal connected to an output terminal and a second terminal connected to a first wiring on a low potential side; A first resistor connected between the control terminal of the output transistor and the first wiring; a buffer circuit to which an output control signal is supplied to the input terminal; A first transistor having a second terminal connected to a second wiring of the high potential side, a first terminal connected to a control terminal of the output transistor, and a control terminal supplied with an output signal of the buffer circuit; The first terminal is connected to the terminal, the second terminal is connected to the first wiring, the output circuit of the buffer circuit is supplied to the control terminal, A second transistor which is complementarily turned on / off with respect to the gates, and a second transistor which is connected between the control terminal of the output transistor and the first terminal of the second transistor and between the second terminal of the second transistor and the first wiring And a second resistor connected to at least one side of the first resistor.

According to this structure, when the second transistor is turned on, the control terminal of the output transistor is connected to the first wiring on the low potential side via the second transistor and the second resistor, and the output transistor is turned off. And a series circuit of the second transistor and the second resistor is connected in parallel to the first resistor. Therefore, the resistance value of the composite resistance between the control terminal of the output transistor and the first wiring is made smaller than that of the first resistor alone. The synthetic resistor and the first active clamp circuit clamp the output terminal voltage to a predetermined voltage due to the surge applied to the output terminal and protect the output transistor. Further, the composite resistance between the control terminal of the output transistor and the first wiring suppresses the voltage fluctuation of the control terminal of the output transistor by noise or the like, and the unintentional turning on of the output transistor, that is, the malfunction of the output transistor is reduced.

In the output circuit, it is preferable that a resistance value of the first resistor is set to be larger than a resistance value of the second resistor.

According to this configuration, when the second transistor is turned off and the first transistor is turned on, the control terminal of the output transistor is connected to the first wiring with only the first resistor. Accordingly, the resistance value of the first resistor is increased to reduce the amount of current between the control terminal of the output transistor and the first wiring, thereby suppressing an increase in power consumption.

A third transistor having a second terminal connected to a control terminal of the second transistor and having a first terminal connected to the first wiring, and a third transistor connected between the output terminal and the control terminal of the third transistor, And a third resistor connected between the control terminal of the third transistor and the first wiring.

According to this configuration, the third transistor turned on by the current flowing in the second active clamp circuit connects the control terminal of the second transistor to the first wiring on the low potential side, and the second transistor is turned off. Therefore, when the surge is applied to the output terminal, the second transistor is turned off, and the surge flows to the first wiring by the output transistor turned on by the first active clamp circuit and the first resistor, thereby ensuring the immunity of the output transistor.

In the output circuit, the control terminal of the second transistor is preferably connected to an output terminal of the buffer circuit through a fourth resistor.

According to this configuration, the second transistor can be easily turned off by the third transistor.

In the output circuit, it is preferable that the output transistor is a MOS transistor in which the first terminal is a drain terminal and the second terminal is a source terminal.

According to this configuration, the power consumption for driving the output transistor which is a MOS transistor is reduced as compared with the case where the bipolar transistor is used.

In the above output circuit, it is preferable that the first active clamp circuit includes a zener diode having a forward connection diode and a reverse connection with respect to a direction from the output terminal to the control terminal of the output transistor.

According to this configuration, the zener diode of the active clamp circuit surrenders due to the surge applied to the output terminal. The surge flows to the first wiring on the low potential side by the current flowing in the active clamp circuit and the output transistor turned on by the first resistor. Therefore, immunity of the output transistor is ensured.

A detection sensor that solves the above problem includes a detection circuit that outputs a detection signal according to a physical quantity of an object to be detected, a determination circuit that outputs a determination signal in accordance with the detection signal, and a signal processing Circuit, and the output circuit.

According to this configuration, the output circuit ensures resistance to the surge of the output transistor. Further, the output circuit is reduced in malfunction of the output transistor due to noise. And a detection sensor having the output circuit is provided.

According to the present invention, malfunction of the output transistor can be suppressed.

According to the embodiments of the present invention, when the second transistor is turned on, the control terminal of the output transistor is connected to the first wiring on the low potential side via the second transistor and the second resistor, and the output transistor is turned off. And a series circuit of the second transistor and the second resistor is connected in parallel to the first resistor. Therefore, the resistance value of the composite resistance between the control terminal of the output transistor and the first wiring is made smaller than that of the first resistor alone. The synthetic resistor and the first active clamp circuit clamp the output terminal voltage to a predetermined voltage due to the surge applied to the output terminal and protect the output transistor. Further, the composite resistance between the control terminal of the output transistor and the first wiring suppresses the voltage fluctuation of the control terminal of the output transistor by noise or the like, and the unintentional turning on of the output transistor, that is, the malfunction of the output transistor is reduced.

1 is a circuit diagram of a detection sensor block according to the first embodiment.
2 is a circuit diagram of the output circuit of the first embodiment.
3 is a circuit diagram of the output circuit of the second embodiment.

(First Embodiment)

 The first embodiment will be described below.

The detection sensor 10 shown in Fig. 1 is connected to a controller (not shown). For example, the external terminals T1 to T4 of the detection sensor 10 are connected to the controller via a cable (not shown). The external terminals T1 and T4 are power supply terminals, and drive voltages (high-potential voltage VC and low-potential voltage GND) are supplied from the controller. The external terminals T2 and T3 are output terminals.

The detection sensor 10 includes a power supply circuit 11, a light emitting circuit 12, a light receiving circuit 13, a light receiving determination circuit 14, a signal processing circuit 15 and output circuits 16 and 17. The detection sensor 10 operates in accordance with the supplied drive voltage and turns on / off the output transistor of the output circuits 16 and 17. The controller receives a signal corresponding to ON / OFF of the output transistor.

The power supply circuit 11 is connected to the external terminal T1 of the detection sensor 10. A drive voltage of the detection sensor 10 is supplied to the external terminal T1 from a controller (not shown) to which the detection sensor 10 is connected. The power supply circuit 11 generates a high potential voltage VDD for each circuit to operate in accordance with the driving voltage. The supply of the high-potential voltage VDD is omitted in Fig.

The light-projecting circuit 12 is a light-emitting element (for example, a light-emitting diode). The floodlight circuit 12 operates according to an operating voltage (for example, a high potential voltage (VDD)) supplied from the power supply circuit 11 and emits light. The light receiving circuit 13 includes a light receiving element (for example, a phototransistor) and outputs a detection signal KS of a level corresponding to the amount of incident light. The detection sensor 10 is, for example, a photosensor (photoelectric sensor) in which a light-emitting element and a light-receiving element are arranged facing each other in a single housing. The object to be detected shields (shields) light from the light emitting circuit 12 to the light receiving circuit 13.

The light receiving determination circuit 14 receives the light receiving signal DS having a level (H level / L level) in accordance with the incident / shading of the light with respect to the light receiving circuit 13 in accordance with the detection signal KS output from the light receiving circuit 13, . Therefore, the level of the light receiving signal DS corresponds to the presence or absence of the detection target. For example, the light-receiving determination circuit 14 outputs a light-receiving signal DS of H level at the time of incidence and outputs a light-receiving signal DS of L level at the time of light-shielding.

The signal processing circuit 15 is connected to the mode setting switch SW1 and the display light emitting diode PD1. The signal processing circuit 15 inputs a mode setting signal MS in accordance with ON / OFF of the mode setting switch SW1. The mode setting switch SW1 sets the operation mode (display mode) of the signal processing circuit 15. The ON / OFF state of the display light-emitting diode PD1 indicates the input / shield state of the light-receiving circuit 13.

For example, the signal processing circuit 15 determines the first mode (MODE: 1) according to the L-level mode setting signal MS (mode setting switch SW1) (MODE: 0) in accordance with the control signal MS (mode setting switch SW1 is turned off). The first mode (MODE: 1) is a mode (ON mode at the time of light incident) in which the display light emitting diode PD1 is turned on (Light-off ON mode) in which the light-emitting diode PD1 is turned on (in the light-off state).

In the first mode (MODE: 1), the signal processing circuit 15 outputs the control signal PC of the H level in accordance with the light reception signal DS of the H level. The display light emitting diode PD1 is turned on in accordance with the control signal PC of the H level. Therefore, when the light receiving circuit 13 is incident, the display light emitting diode PD1 is turned on. Then, the signal processing circuit 15 outputs the control signal PC of the L level in accordance with the light reception signal DS of the L level. Therefore, when the light receiving circuit 13 is shielded from light, the display light emitting diode PD1 is turned off.

In the second mode (MODE: 0), the signal processing circuit 15 outputs the control signal PC of the L level in accordance with the light reception signal DS of the H level. Therefore, when the light receiving circuit 13 is incident, the display light emitting diode PD1 is turned off. Then, the signal processing circuit 15 outputs the control signal PC of the H level in accordance with the light reception signal DS of the L level. Therefore, when the light receiving circuit 13 is shielded from light, the display light emitting diode PD1 is turned on.

The signal processing circuit 15 is connected to the output circuits 16 and 17. The output circuit 16 includes an output transistor connected to the external terminal T2. The output circuit 17 includes an output transistor connected to the external terminal T3. The signal processing circuit 15 generates output control signals OC1 and OC2 in accordance with the light receiving signal DS. In this embodiment, the signal processing circuit 15 compensates for the two output circuits 16 and 17, that is, turns on one of the output circuits 16 and 17 and turns on the other output circuits 17 and 16, The output control signals OC1 and OC2 are generated.

For example, the signal processing circuit 15 generates the output control signal OC1 of the L level and the output control signal OC2 of the H level in accordance with the light reception signal DS of the H level. The output transistor of the output circuit 16 is turned on in response to the output control signal OC1 of the L level. The output transistor of the output circuit 17 is turned off in accordance with the output control signal OC2 of the H level. Therefore, when the light receiving circuit 13 is incident, the output circuit 16 is turned on and the output circuit 17 is turned off. On the other hand, the signal processing circuit 15 generates the H level output control signal OC1 and the L level output control signal OC2 in accordance with the L level light reception signal DS. Therefore, when the light receiving circuit 13 is shielded from light, the output circuit 16 is turned off and the output circuit 17 is turned on.

Next, the configuration of the output circuit 16 will be described. Since the output circuit 16 and the output circuit 17 have the same configuration, the illustration and description of the output circuit 17 will be omitted.

 2, the output circuit 16 has a buffer circuit 21, transistors M1, M2 and M3, a capacitor C1, resistors R1 and R2, a zener diode ZD1 and a diode D1 .

The buffer circuit 21 is supplied with the output control signal OC1. The buffer circuit 21 outputs a signal S1 that is logically equivalent to the level of the output control signal OC1. The output terminal of the buffer circuit 21 is connected to the gate terminal (control terminal) of the transistor M2 and the gate terminal (control terminal) of the transistor M3.

The transistor M2 is a P-channel MOS transistor, and the transistor M3 is an N-channel MOS transistor. The source terminal (second terminal) of the transistor M2 is connected to a wiring (hereinafter, referred to as a wiring VDD) to which the high potential voltage VDD is supplied and the drain terminal (first terminal) (Control terminal) of the transistors M1, M2. This transistor M1 is, for example, a P-channel MOS transistor and an output transistor. The output transistor M1 will be described below.

The gate terminal of the output transistor M1 is connected to the drain terminal (first terminal) of the transistor M3 through the resistor R2. The source terminal (second terminal) of the transistor M3 is connected to a wiring of a low potential voltage (for example, ground GND) (hereinafter referred to as wiring GND).

The source terminal (second terminal) of the output transistor M1 is connected to the wiring GND and the drain terminal (first terminal) of the output transistor M1 is connected to the external terminal T2. Thus, the output circuit 16 is an open-drain output circuit.

The external terminal T2 is connected to the negative terminal of the Zener diode ZD1. The positive terminal of the zener diode ZD1 is connected to the positive terminal of the diode D1 and the negative terminal of the diode D1 is connected to the gate terminal of the output transistor M1. The reverse connection Zener diode ZD1 and the forward connection diode D1 are connected in series from the external terminal T2 in order between the external terminal T2 and the gate terminal of the output transistor M1. The zener diode (ZD1) and the diode (D1) constitute an active clamp circuit (22).

The negative terminal of the diode D1 is connected to the wiring GND through the resistor R1. Therefore, the resistor R1 is connected between the active clamp circuit and the wiring GND. The resistor R1 is connected in parallel to the series circuit of the resistor R2 and the transistor M3.

The external terminal T2 is connected to the first terminal of the capacitor C1 and the second terminal of the capacitor C1 is connected to the gate terminal of the output transistor M1. Thus, the capacitor C1 is connected between the gate and the drain of the output transistor M1.

The operation of this output circuit 16 will be described.

When the output control signal OC1 is at the L level, the transistor M2 is turned on and the transistor M3 is turned off in accordance with the output signal S1 of the buffer circuit 21. The gate terminal of the output transistor M1 is connected to the wiring VDD by the turned-on transistor M2 and to the wiring GND by the resistor R1. The resistance value of the resistor R1 is set to a large value so as not to interfere with the rise of the gate voltage of the output transistor M1 by the turned on transistor M2. Then, the high-potential voltage VDD is supplied to the gate terminal of the output transistor Ml to turn on the output transistor Ml. That is, by setting the resistance value of the resistor R1 to a sufficiently large value, the output transistor M1 is reliably turned on. Therefore, current flows through the output transistor M1 through the load resistance of a controller (not shown), and the controller inputs the signal of L level.

By setting the resistance value of the resistor R1 to a large value, an increase in power consumption is suppressed. That is, the first terminal of the resistor R1 is connected to the wiring VDD through the transistor M2, and the second terminal of the resistor R1 is connected to the wiring GND. The transistor M2 is turned on in response to the output signal S1 (L level) of the buffer circuit 21. [ Therefore, a current flows from the wiring VDD to the wiring GND through the transistor M2 and the resistor R1 in an ON state. This amount of current depends on the resistance value of the resistor R1. Therefore, by setting the resistance value of the resistor R1 as described above, an increase in power consumption is suppressed.

On the other hand, when the output control signal OC1 is at the H level, the transistor M2 is turned off and the transistor M3 is turned on in accordance with the output signal S1 of the buffer circuit 21. Then, the gate terminal of the output transistor M1 becomes the low potential voltage (GND) level through the resistor R1 and the turned on transistor M3 and the resistor R2, and the output transistor M1 is turned off. Therefore, since the current does not flow through the output transistor Ml, the controller inputs the H level signal by the load resistance.

When a surge such as electrostatic discharge (ESD) is applied to the external terminal T2 while the output transistor M1 is turned off, the level of the external terminal T2 sharply rises. The zener diode ZD1 surrenders depending on the level of the external terminal T2 and a current flows through the zener diode ZD1 and the diode D1.

At this time, the gate terminal of the output transistor M1 is connected to the wiring GND through the resistor R1 and the turned-on transistor M3 and the resistor R2 in parallel. Therefore, the output transistor M1 is turned on by the resistance of the value obtained by combining the on-resistance values of the resistors R1 and R2 and the turned-on transistor M3. Therefore, the surge voltage (current) applied to the external terminal T2 flows to the external terminal T4 (the wiring (GND)) through the output transistor M1 which is turned on, so that ESD immunity is ensured.

When noise is applied to the external terminal T2 while the output transistor M1 is turned off, the gate of the output transistor M1 is turned on by capacitive coupling by the parasitic capacitance between the drain and gate of the output transistor M1. Voltage fluctuates. At this time, if only the resistor R1 having a large resistance value is connected between the gate and the source of the output transistor M1, the output transistor M1 may be turned on by the gate voltage fluctuating due to noise or the like. In other words, the output transistor M1 may malfunction due to noise.

However, in the present embodiment, the series circuit of the resistor R2 and the transistor M3 is connected in parallel to the resistor R1. When the output transistor Ml is turned off, the transistor M3 is turned on. Therefore, by setting the resistance value of the resistor R2 to a small value, the voltage rise at the gate terminal of the output transistor M1 is suppressed, and the malfunction of the output transistor M1 is suppressed.

As described above, according to the present embodiment, the following effects can be obtained.

(1-1) When the transistor M3 is turned on in accordance with the output control signal OC1, the gate terminal of the output transistor M1 is connected to the low potential side wiring GND , And the output transistor Ml is turned off. The series circuit of the transistor M3 and the resistor R2 is connected in parallel to the resistor R1. Therefore, the resistance value of the composite resistor between the gate terminal of the output transistor M1 and the wiring (GND) becomes smaller than the case where only the resistor R1 is provided. The resistors R1 and R2 and the active clamp circuit 22 clamp the voltage of the external terminal T2 due to the surge applied to the external terminal T2 to a predetermined voltage and protect the output transistor M1. The resistors R1 and R2 between the gate terminal of the output transistor M1 and the wiring GND suppress the voltage fluctuation of the gate terminal of the output transistor M1 due to noise or the like, It is possible to reduce the malfunction that would otherwise occur.

(1-2) The resistance value of the resistor R1 is set to be larger than the resistance value of the resistor R2. Therefore, when the transistor M3 is turned off and the transistor M1 is turned on, the gate terminal of the output transistor M1 is connected to the wiring GND only by the resistor R1. Therefore, by increasing the resistance value of the resistor R1 and reducing the amount of current between the gate terminal of the output transistor M1 and the wiring GND with respect to the current flowing through the turned-on transistor M2, Can be suppressed.

(Second Embodiment)

The second embodiment will be described below.

Since the configuration of the detection sensor is the same as that of the first embodiment, the drawings and description are omitted.

In the following description, the same reference numerals are used for the same members as in the first embodiment, and a part or all of the explanations are omitted.

3, the output circuit 31 of the present embodiment includes a buffer circuit 21, transistors M1, M2, M3, and M4, a capacitor C1, resistors R11, R12, R13, Zener diodes ZD1 and ZD2, and diodes D1 and D2.

The output terminal of the buffer circuit 21 is connected to the gate terminal (control terminal) of the transistor M2 and to the gate terminal (control terminal) of the transistor M3 through the resistor R13. The source terminal of the transistor M2 is connected to the wiring VDD and the drain terminal of the transistor M2 is connected to the gate terminal (control terminal) of the transistor M1. Transistor M1 is an output transistor. The output transistor M1 will be described below. The gate terminal of the output transistor M1 is connected to the drain terminal of the transistor M3 through the resistor R12. The source terminal of the transistor M3 is connected to the wiring GND. The resistance values of the resistors R11 and R12 are set equal to the resistance values of the resistors R1 and R2 of the first embodiment, for example.

Is connected to the drain terminal and the external terminal T2 of the output transistor M1 and the source terminal of the output transistor M1 is connected to the wiring GND. Therefore, the output circuit 31 is an open-drain output circuit.

The external terminal T2 is connected to the negative terminal of the zener diode ZD1 and the positive terminal of the zener diode ZD1 is connected to the positive terminal of the diode D1 and the negative terminal of the diode D1 is connected to the transistor M1. As shown in FIG. The Zener diode ZD1 and the diode D1 constitute an active clamp circuit 22. [

The positive terminal of the diode D1 is connected to the wiring GND via a resistor R11.

The external terminal T2 is connected to the gate terminal of the transistor M1 through the capacitor C1.

The external terminal T2 is connected to the negative terminal of the zener diode ZD2 and the positive terminal of the zener diode ZD2 is connected to the positive terminal of the diode D2 and the negative terminal of the diode D2 is connected to the transistor M4. As shown in FIG. The Zener diode ZD2 and the diode D2 constitute an active clamp circuit 23. [

The source terminal (second terminal) of the transistor M4 is connected to the gate terminal of the transistor M2 and the drain terminal (first terminal) of the transistor M4 is connected to the wiring GND. The transistor M4 is the same conductivity type MOS transistor as the transistor M3, that is, an N-channel MOS transistor. The gate terminal of the transistor M4 is connected to the wiring GND via the resistor R14. The resistance value of the resistor R14 is set to be smaller than, for example, the resistance value of the resistor R11. As a result, the gate voltage of the transistor M4 rises faster than the gate voltage of the output transistor Ml and turns on the transistor M4.

The operation of the output circuit 31 will be described.

When the output control signal OC1 is at the L level, the output signal S1 of the buffer circuit 21 is supplied to the gate terminal of the transistor M2 and also to the gate terminal of the transistor M3 through the resistor R13 . The gate terminal of the transistor M4 connected to the gate terminal of the transistor M3 is pulled down by the resistor R14 and turned off. Therefore, the transistor M2 is turned on and the transistor M3 is turned off according to the output signal S1. The gate terminal of the output transistor M1 is connected to the wiring VDD by the turned on transistor M2 and is connected to the wiring GND by the resistor R11. Therefore, the resistance value of the resistor R11 is set to a large value so as not to interfere with the rise of the gate voltage of the output transistor Ml by the turned-on transistor M2. As a result, the high-potential voltage VDD is supplied to the gate terminal of the output transistor M1, and the output transistor M1 is turned on. Therefore, current flows through the output transistor M1 through the load resistance of a controller (not shown), and the controller inputs the signal of L level.

On the other hand, when the output control signal OC1 is at the H level, the transistor M2 is turned off and the transistor M3 is turned on in accordance with the output signal S1 of the buffer circuit 21. Thus, the gate terminal of the output transistor Ml is connected to the wiring GND through the turned-on transistor M3, and the output transistor Ml is turned off. Therefore, since the current does not flow through the output transistor Ml, the controller inputs the H level signal by the load resistance.

When noise is applied to the external terminal T2 when the output transistor M1 is turned off, the gate voltage of the output transistor M1 is increased by capacitive coupling by the parasitic capacitance between the drain and the gate of the output transistor M1 Change. The gate terminal of the output transistor Ml is connected to the wiring GND via the turned-on transistor M3. Thus, the turned-on transistor M3 suppresses the voltage rise at the gate terminal of the output transistor M1. This prevents malfunction of the output transistor (M1).

When a surge such as electrostatic discharge (ESD) is applied to the external terminal T2 while the output transistor M1 is turned off, the level of the external terminal T2 rises. The zener diode ZD1 surrenders depending on the level of the external terminal T2 and a current flows through the zener diode ZD1 and the diode D1.

The zener diode ZD2 surrenders depending on the level of the external terminal T2 and a current flows through the zener diode ZD2 and the diode D2. With this current, the gate voltage of the transistor M4 rises and the transistor M4 turns on. The transistor M4 turned on connects the gate terminal of the transistor M3 to the wiring GND. As a result, the transistor M3 is turned off. That is, the transistor M4 turns off the transistor M3 according to the surge.

Then, the gate terminal of the output transistor Ml is connected to the wiring GND through the resistor R11. Therefore, since the current flows through the resistor R11 to the wiring GND, the output transistor M1 is turned on by the resistor R11. Thus, the surge voltage (current) applied to the external terminal T2 flows to the external terminal T4 (wiring (GND)) through the output transistor M1 which is turned on, so that ESD immunity is ensured.

As described above, according to the present embodiment, the following effects can be obtained.

(2-1) The transistor M3 turned on in accordance with the output control signal OC1 connects the gate terminal of the output transistor M1 to the wiring GND on the low potential side, and when the output transistor M1 is off do. Therefore, when the noise is applied, the transistor M3 suppresses the voltage fluctuation of the gate terminal of the output transistor M1, so that the unintentional turning on of the output transistor M1, that is, the malfunction of the output transistor M1 can be reduced .

(2-2) When a current flows through the active clamp circuit 23 due to a surge applied to the external terminal T2, the gate voltage of the transistor M4 rises due to the current to turn on the transistor M4. Since the transistor M4 turned on connects the gate terminal of the transistor M3 to the wiring GND, the transistor M3 is turned off. Therefore, the surge flows to the wiring GND by the active clamp circuit 22 and the output transistor M1 turned on by the resistor R11, and the resistance of the output transistor M1 can be ensured.

(2-3) The gate terminal of the transistor M3 is connected to the output terminal of the buffer circuit 21 via the resistor R13, and the transistor M4 is connected to the gate terminal of the transistor M3. In the normal operation of the transistor M4, the gate terminal is connected to the wiring GND via the resistor R14 and is turned off. Therefore, since the transistor M4 does not increase the operation current of the output circuit in the normal operation, it does not hinder the reduction of power consumption. And the transistor M3 can be turned on and off by the output signal of the buffer circuit 21. [ When the output signal is being output from the buffer circuit 21 to turn on the transistor M3, the transistor M4 is turned on to connect the gate terminal of the transistor M3 to the wiring GND, Can be easily turned off.

Each of the above embodiments may be implemented in the following manner.

In the first embodiment, the resistor R2 may be connected between the transistor M3 and the wiring GND. A resistor may be inserted between at least one of the gate terminal of the transistor M3 and the output transistor M1 and between the transistor M3 and the wiring GND.

- For each of the above embodiments, the output transistor may be a PMOS transistor.

In the first embodiment, the transistors M1 to M3 may be bipolar transistors. In the second embodiment, the transistors M1 to M4 may be bipolar transistors.

- For each of the above-described modes, a so-called reflection type detection sensor may be used in which reflected light from the detected object is received by the light receiving circuit 13.

- For each of the above embodiments, a detection system in which the light emitting circuit 12 and the light receiving circuit 13 are housed in different cases may be used. That is, the sensor 10 shown in Fig. 1 may be a sensor in which the light emitting circuit 12 is omitted.

- For each of the above-described forms, it may be a detection sensor for detecting an object by a physical quantity other than light (for example, magnetic force, temperature, pressure, ultrasonic wave, etc.).

10 detection sensor
13 Light receiving circuit (detection circuit)
14 Light-receiving judgment circuit (judgment circuit)
15 signal processing circuit
16, 17, 31 Output Circuit
21 buffer circuit
22 active clamp circuit (first active clamp circuit)
23 Active clamp circuit (second active clamp circuit)
DS light receiving signal (judgment signal)
KS detection signal
M1 output transistor
M2 transistor (first transistor)
M3 transistor (second transistor)
M4 transistor (third transistor)
R1 resistance (first resistance)
R2 resistance (second resistance)
R11 resistance (first resistance)
R12 resistance (second resistance)
R13 resistance (fourth resistance)
R14 resistance (third resistance)
ZD1, ZD2 Zener diodes
D1, D2 diode
TE external terminal (output terminal)
GND wiring (first wiring)
VDD wiring (second wiring)

Claims (7)

An output circuit provided in a detection sensor,
An output transistor having a first terminal connected to the output terminal and a second terminal connected to the first wiring on the low potential side;
A first active clamp circuit connected between the output terminal and a control terminal of the output transistor;
A first resistor connected between the control terminal of the output transistor and the first wiring;
A buffer circuit to which an output control signal is supplied to an input terminal;
A first transistor having a second terminal connected to a second wiring of a high potential side, a first terminal connected to a control terminal of the output transistor, and an output signal of the buffer circuit being supplied to a control terminal;
A first terminal is connected to a control terminal of the output transistor, a second terminal is connected to the first wiring, an output signal of the buffer circuit is supplied to a control terminal, and a complementary on / A second transistor which is turned off; And
And a second resistor inserted between at least one of the control terminal of the output transistor and the first terminal of the second transistor and between the second terminal of the second transistor and the first wiring,
A series circuit of the second transistor and the second resistor is connected in parallel to the first resistor,
A third transistor having a second terminal connected to a control terminal of the second transistor and a first terminal connected to the first wiring;
A second active clamp circuit connected between the output terminal and the control terminal of the third transistor; And
And a third resistor coupled between the control terminal of the third transistor and the first wiring. The method according to claim 1,
Wherein the resistance value of the first resistor is set to be larger than the resistance value of the second resistor. delete The method according to claim 1,
And the control terminal of the second transistor is connected to an output terminal of the buffer circuit through a fourth resistor. The method according to any one of claims 1, 2, and 4,
Wherein the output transistor is a MOS type transistor in which the first terminal is a drain terminal and the second terminal is a source terminal. The method according to any one of claims 1, 2, and 4,
Wherein the first active clamp circuit includes a forward connection diode and a reverse connection Zener diode in a direction from the output terminal to the control terminal of the output transistor. A detection circuit for outputting a detection signal according to a physical quantity of the detection object,
A determination circuit for outputting a determination signal in accordance with the detection signal;
A signal processing circuit for outputting an output control signal in accordance with the determination signal;
A detection sensor comprising the output circuit according to any one of claims 1, 2, and 4.
KR1020150054428A 2014-06-27 2015-04-17 Output circuit and detection sensor KR101690867B1 (en)

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JP6825223B2 (en) * 2016-04-15 2021-02-03 富士電機株式会社 Drive and inductive load drive
JP7356340B2 (en) * 2019-12-25 2023-10-04 株式会社タムラ製作所 gate drive circuit

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