KR101690032B1 - Phase locked loop circuit and driving method thereof - Google Patents

Phase locked loop circuit and driving method thereof Download PDF

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KR101690032B1
KR101690032B1 KR1020150069857A KR20150069857A KR101690032B1 KR 101690032 B1 KR101690032 B1 KR 101690032B1 KR 1020150069857 A KR1020150069857 A KR 1020150069857A KR 20150069857 A KR20150069857 A KR 20150069857A KR 101690032 B1 KR101690032 B1 KR 101690032B1
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frequency
signal
frequency signal
divided
pll
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KR1020150069857A
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KR20160136112A (en
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김충환
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주식회사 우리로
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/07—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop using several loops, e.g. for redundant clock signal generation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/087—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
    • H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop

Abstract

A PLL circuit of the present invention includes a first PLL unit that receives a reference frequency signal and a first frequency signal that is an output of a first voltage controlled oscillator and outputs a first control voltage to control the first voltage controlled oscillator; And a second PLL unit receiving the reference frequency signal and a second frequency signal which is an output of the second voltage controlled oscillator and outputting a second control voltage for controlling the second voltage controlled oscillator.

Description

[0001] PHASE LOCKED LOOP CIRCUIT AND DRIVING METHOD THEREOF [0002]

The present invention relates to a PLL circuit and a driving method thereof, and more particularly to a PLL circuit for a radar distance measuring instrument and a driving method thereof.

The laser range finder has been used in many places where distance measurement is necessary instead of the conventional tape measure, and it is widely used in construction field, manufacturing field, leisure industry such as golf, and military industry.

The basic principle of the laser range finder is to measure the distance by emitting a laser toward the target and then detecting the returning laser. This method is generally referred to as a time of flight (TOF) method, which is divided into a pulse method and a modulation method.

The pulse method is to measure the distance by measuring the time of arrival (TOA) until the laser beam is reflected after the transmission of the laser pulse, and the modulation method is a method of measuring the distance between the transmission signal transmitted by the amplitude modulation of the continuously operating laser light intensity and the reception And detects the phase difference of the signal to calculate the distance to the reflector.

The pulse method can measure distances from 1 to 2 km, but the distance accuracy of consumer products is about 1 meter. On the other hand, the modulation method can measure a relatively short distance of about 200 to 300 meters, but the distance accuracy is relatively accurate to about 1 mm.

The modulation method is divided into a homodyne method and a heterodyne method. The modulation frequency of the transmission and reception is the same as that of the homodyne method. When the two frequencies are different, the method is called the heterodyne method.

6 is a diagram illustrating a frequency spectrum of a conventional heterodyne transmission frequency signal.

Referring to FIG. 6, the frequency to be transmitted is one of an Upper Side Band Frequency (fUSB) and a Lower Side Band Frequency (fLSB) containing information. For example, if it is desired to transmit the upper sideband frequency fUSB, it is desirable to attenuate the lower sideband frequency component fLSB and the local oscillator frequency fLO as much as possible.

However, when attenuating the lower sideband frequency component (fLSB) and the local oscillation frequency component (fLO) through a double balanced differential structure and a plurality of frequency mixers according to the conventional method, the IMRR (IMAGE Rejection Ratio) and LORR (LOcal signal rejection ratio) can not be increased as much as desired, and peripheral harmonics can not be attenuated.

Therefore, a new method for generating a transmission frequency signal that excludes unnecessary frequency components such as harmonics is needed.

1. Korean Patent Publication No. 2009-0105752 (2009.10.07)

SUMMARY OF THE INVENTION The present invention provides a PLL circuit for outputting a stable frequency signal and a driving method thereof.

A PLL circuit according to an embodiment of the present invention is a PLL circuit included in a heterodyne communication system and receives a reference frequency signal and a first frequency signal which is an output of a first voltage controlled oscillator, A first PLL unit for outputting a first control voltage for controlling the oscillator; And a second PLL unit receiving the reference frequency signal and a second frequency signal which is an output of the second voltage controlled oscillator and outputting a second control voltage for controlling the second voltage controlled oscillator.

Wherein the first PLL unit comprises: a first frequency divider for dividing the first frequency signal by N1 and outputting a first frequency-divided frequency signal; And a first phase frequency detector for comparing the first frequency-divided frequency signal and the reference frequency signal.

The second PLL unit includes: a second frequency divider for dividing the second frequency signal into N2 and outputting a second divided frequency signal; And a second phase frequency detector for comparing the second frequency divided signal and the reference frequency signal.

The reference frequency signal may be an intermediate frequency signal, the first frequency signal may be a local oscillator frequency signal, and the second frequency signal may be a side band frequency signal.

The frequency difference between the first frequency signal and the second frequency signal may be the same as the frequency of the reference frequency signal.

The N1 may be set such that the frequency of the first frequency-divided signal is equal to the frequency of the reference frequency signal.

The N2 may be set such that the frequency of the second frequency-divided signal is equal to the frequency of the reference frequency signal.

The difference between N1 and N2 may be one.

The first PLL unit may further include a first charge pump and a first loop filter, and the second PLL unit may further include a second charge pump and a second loop filter.

And a division unit for receiving a clock signal from a clock signal source and dividing the clock signal to output the reference frequency signal.

Wherein the frequency divider comprises: a third frequency divider for dividing the clock signal into N3 and outputting a third divided frequency signal; And a fourth frequency divider for dividing the third divided frequency signal by N4 and outputting a fourth divided frequency signal, and the fourth divided frequency signal may be the reference frequency signal.

The N3 may be set such that the third frequency-divided signal is used as a trigger signal of an analog-to-digital converter (ADC).

A method of driving a PLL circuit according to an embodiment of the present invention is a method of driving a PLL circuit including a first PLL unit and a second PLL unit included in a heterodyne communication system, The unit receiving a reference frequency signal; The first PLL unit receives a first frequency signal from the first voltage controlled oscillator and the second PLL unit receives a second frequency signal from the second voltage controlled generator; And a first frequency divider included in the first PLL unit divides the first frequency signal by N1 to output a first frequency division signal, and a second frequency divider included in the second PLL unit divides the second frequency Dividing the frequency of the reference frequency signal by N2 and outputting a second divided frequency signal, wherein N1 is set such that the frequency of the reference frequency signal and the frequency of the first frequency divided signal are the same, And N2 is set so that the frequency of the second frequency-divided signal is the same.

Wherein the first PLL unit includes a first phase frequency detector and the second PLL unit includes a second phase frequency detector wherein the first frequency divided signal and the reference frequency signal are compared And comparing the second divided frequency signal and the reference frequency signal in the second phase frequency detector.

The reference frequency signal may be an intermediate frequency signal, the first frequency signal may be a local oscillation frequency signal, and the second frequency signal may be a sideband frequency signal.

The frequency difference between the first frequency signal and the second frequency signal may be the same as the frequency of the reference frequency signal.

The control voltage of the first voltage controlled oscillator is determined corresponding to the output value of the first phase frequency detector and the control voltage of the second voltage controlled oscillator is determined in accordance with the output value of the second phase frequency detector As shown in FIG.

Dividing the clock signal into N3 to generate a third frequency-divided signal; And dividing the third divided frequency signal by N4 to generate a fourth divided frequency signal, wherein the fourth divided frequency signal may be the reference frequency signal.

And using the third frequency-divided signal as a trigger signal of the ADC.

According to the embodiment of the present invention, a PLL circuit for outputting a stable frequency signal and a driving method thereof can be provided.

1 is a diagram showing a PLL circuit according to a first embodiment of the present invention.
2 is a diagram showing a detailed configuration of a PLL circuit according to the first embodiment of the present invention.
3 is a diagram illustrating a PLL circuit according to a second embodiment of the present invention.
4 is a diagram showing a detailed configuration of a PLL circuit according to a second embodiment of the present invention.
5 is a diagram illustrating a frequency spectrum of a transmission frequency signal output using a PLL circuit according to an embodiment of the present invention.
6 is a diagram illustrating a frequency spectrum of a conventional heterodyne transmission frequency signal.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings, which will be readily apparent to those skilled in the art to which the present invention pertains. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein.

In the drawings, the thickness is enlarged to clearly represent the layers and regions. Like parts are designated with like reference numerals throughout the specification. It will be understood that when an element such as a layer, film, region, plate, or the like is referred to as being "on" another portion, it includes not only the element directly over another element, Conversely, when a part is "directly over" another part, it means that there is no other part in the middle.

Also, throughout the specification, when an element is referred to as "including" an element, it is understood that the element may include other elements as well, without departing from the other elements unless specifically stated otherwise. Also, throughout the specification, the term "on " means to be located above or below a target portion, and does not necessarily mean that the target portion is located on the image side with respect to the gravitational direction.

1 is a diagram illustrating a PLL circuit (Phase Locked Loop Circuit) according to a first embodiment of the present invention.

Referring to FIG. 1, a PLL circuit 10a according to the first embodiment of the present invention includes a first PLL unit 100 and a second PLL unit 200. The PLL circuit 10a receives a reference frequency signal and is connected to a first voltage controlled oscillator (VCO) 21 and a second voltage controlled oscillator 22.

The first PLL unit 100 serves to fix the frequency of the first frequency signal output from the first voltage controlled oscillator 21 and the second PLL unit 200 serves to output the output of the second voltage controlled oscillator 22 The frequency of the second frequency signal is fixed. The first voltage-controlled oscillator 21 and the second voltage-controlled oscillator 22 output a frequency signal of a specific frequency according to an input control voltage. The frequency of the first and second frequency signals, which are output frequency signals, Can be varied. Therefore, the first PLL unit 100 outputs the first control voltage to the first voltage-controlled oscillator 21 so that the frequency of the first frequency signal is fixed to the target frequency, and the frequency of the second frequency signal becomes the target frequency The second PLL unit 200 outputs the second control voltage to the second voltage controlled oscillator 22. [ The first PLL unit 100 and the second PLL unit 200 may further include a configuration for frequency tuning, but a detailed description thereof will be omitted.

The reference frequency signal is supplied to the first PLL unit 100 and the second PLL unit 200, respectively. The first PLL unit 100 detects whether the frequency of the first frequency signal fluctuates based on the reference frequency signal and the first frequency signal fed back from the first voltage controlled oscillator 21. The second PLL unit 200 detects whether the frequency of the second frequency signal fluctuates based on the reference frequency signal and the second frequency signal fed back from the second voltage controlled oscillator 22.

2 is a diagram showing a detailed configuration of a PLL circuit according to the first embodiment of the present invention.

Referring to FIG. 2, the first PLL unit 100 includes a frequency divider 110, a first phase frequency detector 120, a first charge pump 130, And a first loop filter 140. The second PLL unit 200 includes a second frequency divider 210, a second phase frequency detector 220, a second charge pump 230, And a second loop filter 240.

In the first embodiment, the reference frequency signal is an intermediate frequency signal (fIF), and the first frequency signal output from the first voltage controlled oscillator 21 is a Local Oscillator Frequency Signal (fLO ), And the second frequency signal output from the second voltage-controlled oscillator 22 is a side band frequency signal. The sideband signal used for the transmission signal may be the upper sideband or the lower sideband, but it is assumed that the upper sideband signal fUSB in the present invention.

Generally, in the heterodyne method, a baseband frequency signal containing information is not immediately upconverted to a carrier frequency, which is a frequency of a transmission signal, and a selectivity, sensitivity ), Stability, and so on, and upconverts them in two stages via an intermediate frequency. To this end, a separate IF stage (Intermediate Frequency Part) separate from the RF stage (Radio Frequency Part) is required, thus complicating the circuit configuration. However, in the present invention, since the sideband signal fUSB is directly generated by the second voltage-controlled oscillator 22, There is an advantage that an IF stage is not required in the RF transmitting unit (not shown), and the circuit configuration becomes simple. In addition, as described above, a process of attenuating unnecessary frequency signal components (unused sideband frequency components, local oscillation frequency components, and harmonic components) is required in the RF transmission unit. According to the present invention, fUSB) so that the attenuation process is unnecessary. That is, as shown in FIG. 5, sideband frequency and local oscillation frequency components which are not used are not separately generated in the transmission frequency spectrum, and the magnitude of harmonic components is also very small.

The first frequency divider 110 receives the first frequency signal, divides it into N1, and outputs a first divided frequency signal. N1 can be set so that the frequency of the first frequency-divided signal is equal to the frequency of the reference frequency signal.

The first phase frequency detector 120 receives and compares the reference frequency signal fIF with the first frequency-divided signal. The first phase frequency detector 120 outputs a pulse signal having a pulse width different from the pulse width according to the difference between the frequency of the first frequency-divided signal and the frequency of the reference frequency signal fIF.

The first charge pump 130 converts the pulse signal into a corresponding voltage signal and outputs the converted voltage signal. The first charge pump 130 may include a switch, a capacitor, and the like, and may adjust the charge stored in the capacitor by changing the switching according to the pulse width and the sign, thereby converting the level of the voltage signal.

The first loop filter 140 filters out unnecessary harmonic components in this voltage signal and outputs a first control voltage. The first loop filter 140 may comprise a low pass filter (LPF) for a frequency corresponding to the difference between the frequency of the reference frequency signal fIF and the frequency of the first frequency divided signal.

The first voltage controlled oscillator 21 outputs the first frequency signal fLO in accordance with the first control voltage in accordance with the local oscillation frequency. The first frequency signal fLO may be used in an RF receiver or the like.

The second frequency divider 210 receives the second frequency signal, divides it into N2, and outputs a second divided frequency signal. N2 may be set so that the frequency of the second frequency-divided signal is equal to the frequency of the reference frequency signal.

The second phase frequency detector 220 receives and compares the reference frequency signal fIF and the second frequency-divided signal. The second phase frequency detector 220 outputs a pulse signal having a different pulse width from the frequency of the second frequency-divided signal and the frequency of the reference frequency signal fIF.

The second charge pump 230 receives the pulse signal, converts the pulse signal into a corresponding voltage signal, and outputs the corresponding voltage signal. The second charge pump 230 may include a switch, a capacitor, and the like to adjust the charge stored in the capacitor by changing the switching according to the pulse width and the sign, thereby converting the level of the voltage signal.

The second loop filter 240 filters out unnecessary harmonic components in this voltage signal and outputs a second control voltage. The second loop filter 240 may be a low-pass filter for a frequency corresponding to a difference between the frequency of the reference frequency signal fIF and the frequency of the second frequency-divided signal.

The second voltage controlled oscillator 22 outputs the second frequency signal fUSB in accordance with the second control voltage in accordance with the local oscillation frequency. Although not shown, the RF transmitter may mix the second frequency signal fUSB and the baseband signal to generate a transmit frequency signal.

In the first embodiment, the frequency difference between the first frequency signal fLO and the second frequency signal fUSB is the same as the frequency of the reference frequency signal fIF. That is, the relationship fUSB = fIF + fLO holds. Therefore, the difference between N1 and N2 becomes 1. For example, N1 and N2 may be natural numbers, N1 may be 100, and N2 may be 101. At this time, fLO = 100 * fIF and fUSB = 101 * fIF are established. Thus, for example, if the frequency of the reference frequency signal fIF is 8 MHz, the frequency of the first frequency signal fLO is 800 MHz and the frequency of the second frequency signal fUSB is 808 MHz.

In another embodiment, if the second frequency signal is designed to output a lower sideband signal, N1 = 100, N2 = 99.

3 is a diagram illustrating a PLL circuit according to a second embodiment of the present invention.

3, the PLL circuit 10b according to the second embodiment of the present invention includes a frequency divider 300, a first PLL unit 100, and a second PLL unit 200. [ The description of the first PLL unit 100 and the second PLL unit 200 is the same as described above and will be omitted here.

The frequency divider 300 receives the clock signal from the clock signal source 30, divides the frequency of the clock signal, and outputs a reference frequency signal. The first and second PLL units 100 and 200 receive the reference frequency signal and use the reference frequency signal as a reference signal of the phase frequency detector. The reference frequency signal may be an intermediate frequency signal.

4 is a diagram showing a detailed configuration of a PLL circuit according to a second embodiment of the present invention.

Referring to FIG. 4, the frequency divider 300 of the PLL circuit 10b includes a third divider 310 and a fourth divider 320. The detailed configurations of the first PLL unit 100 and the second PLL unit 200 are the same as those described above with reference to FIG. 2, and therefore detailed description thereof will be omitted.

The third frequency divider 310 receives the clock signal from the clock signal source 30, divides the clock signal into N3, and outputs the third divided frequency signal 4fIF. And N3 may be a natural number that divides the frequency of the clock signal so as to be the frequency of the third divided frequency signal 4fIF.

The third frequency-divided frequency signal 4fIF can be used as a trigger signal of an analog-to-digital converter (ADC) The frequency of the third frequency-divided frequency signal 4fIF may be M times the intermediate frequency. Where M is a natural number. That is, when measuring the intermediate frequency signal fIF with the ADC 40, the third frequency divided signal 4fIF can be used as the measurement trigger signal of the ADC 40 as a signal synchronized with the intermediate frequency signal fIF . In order to measure the phase, it is desirable to perform the ADC measurement at least four times per cycle of the intermediate frequency signal fIF. Therefore, M may be a natural number of 4 or greater. 4, when M is 4, the third frequency-divided frequency signal 4fIF is expressed by 4fIF, but the frequency of the third frequency-divided frequency signal 4fIF may vary according to the value of M.

In the receiver (not shown), the distance can be calculated according to the measured phase value. The principle is as follows.

For example, the ideal transmission signal STX may be expressed by Equation 1 below.

[Equation 1]

Figure 112015047965450-pat00001

As described above, since the frequency of the transmission signal STX may be the upper sideband or the lower sideband frequency, in the expression (1), fLO + fIF = fUSB or fLO-fIF = fLSB is expressed as the frequency of the transmission signal STX .

The received signal SRX can be expressed by the following equation (2).

&Quot; (2) "

Figure 112015047965450-pat00002

here

Figure 112015047965450-pat00003
Is a phase delay value caused by reciprocating the distance d,
Figure 112015047965450-pat00004
Is a phase delay value due to an electrical delay of the transmission / reception circuit.
Figure 112015047965450-pat00005
Can be expressed as Equation (3) below. c is the speed of light.

&Quot; (3) "

Figure 112015047965450-pat00006

When the received signal SRX according to Equation (2) is mixed with the first frequency signal fLO having the local oscillation frequency and passed through the low-pass filter, the received signal SRX is expressed as Equation (4) (SRX2).

&Quot; (4) "

Figure 112015047965450-pat00007

The phase delay value due to the electrical signal of the second received signal SRX2

Figure 112015047965450-pat00008
Lt; RTI ID = 0.0 > ADC < / RTI &
Figure 112015047965450-pat00009
The distance d can be calculated by calculating the value (Equation 5).

&Quot; (5) "

Figure 112015047965450-pat00010

The fourth divider 320 receives the third divided frequency signal 4fIF, divides the third divided frequency signal 4fIF into N4, and outputs a fourth divided frequency signal. At this time, N4 may be set so that the fourth divided frequency signal is equal to the reference frequency signal fIF. Therefore, when M is 4, N4 can also be 4. The fourth frequency-divided frequency signal is used as a reference signal for the first phase frequency detector 120 and the second phase frequency detector 220.

It is to be understood that both the foregoing general description and the following detailed description of the present invention are illustrative and explanatory only and are intended to be illustrative of the invention and are not to be construed as limiting the scope of the invention as defined by the appended claims. It is not. Therefore, those skilled in the art will appreciate that various modifications and equivalent embodiments are possible without departing from the scope of the present invention. Accordingly, the true scope of the present invention should be determined by the technical idea of the appended claims.

10a and 10b: PLL circuit
21: a first voltage-controlled oscillator
22: second voltage-controlled oscillator
30: Clock signal source
40: ADC
100: first PLL unit
200: second PLL unit

Claims (19)

A PLL circuit included in a heterodyne communication system,
A first PLL unit receiving a reference frequency signal and a first frequency signal which is an output of the first voltage controlled oscillator and outputting a first control voltage for controlling the first voltage controlled oscillator; And
And a second PLL unit receiving a reference frequency signal and a second frequency signal which is an output of the second voltage controlled oscillator and outputting a second control voltage for controlling the second voltage controlled oscillator,
The reference frequency signal is an intermediate frequency signal,
The first frequency signal is a local oscillator frequency signal,
The second frequency signal is a side band frequency signal
PLL circuit. The method according to claim 1,
The first PLL unit
A first frequency divider for dividing the first frequency signal by N1 and outputting a first divided frequency signal; And
And a first phase frequency detector for comparing the first frequency divided signal and the reference frequency signal
PLL circuit. 3. The method of claim 2,
The second PLL unit
A second frequency divider for dividing the second frequency signal by N2 and outputting a second divided frequency signal; And
And a second phase frequency detector for comparing the second frequency divided signal and the reference frequency signal
PLL circuit. delete The method of claim 3,
Wherein the frequency difference between the first frequency signal and the second frequency signal is equal to the frequency of the reference frequency signal
PLL circuit. 6. The method of claim 5,
The N1 is
The frequency of the first frequency-divided signal is set to be equal to the frequency of the reference frequency signal
PLL circuit. The method according to claim 6,
N2 is
The frequency of the second frequency-divided signal is set to be equal to the frequency of the reference frequency signal
PLL circuit. 8. The method of claim 7,
The difference between N1 and N2 is 1
PLL circuit. 9. The method of claim 8,
The first PLL unit may further include a first charge pump and a first loop filter,
The second PLL unit further includes a second charge pump and a second loop filter
PLL circuit. 9. The method of claim 8,
And a division unit for receiving a clock signal from a clock signal source and dividing the clock signal to output the reference frequency signal
PLL circuit. 11. The method of claim 10,
The dispensing unit
A third frequency divider dividing the clock signal into N3 and outputting a third divided frequency signal; And
And a fourth frequency divider for dividing the third divided frequency signal by N4 and outputting a fourth divided frequency signal,
The fourth divided frequency signal is the reference frequency signal
PLL circuit. 12. The method of claim 11,
The N3
And the third frequency-divided signal is set to be used as a trigger signal of an analog-to-digital converter (ADC)
PLL circuit. A method of driving a PLL circuit including a first PLL unit and a second PLL unit included in a heterodyne communication system,
Receiving the reference frequency signal by the first and second PLL units;
The first PLL unit receives a first frequency signal from the first voltage controlled oscillator and the second PLL unit receives a second frequency signal from the second voltage controlled generator; And
Wherein the first frequency divider included in the first PLL unit divides the first frequency signal into N1 to output a first frequency division signal, and a second frequency divider included in the second PLL unit divides the second frequency signal To N2, and outputting a second divided frequency signal,
The N1 is set such that the frequency of the reference frequency signal and the frequency of the first frequency division signal are the same,
The N2 is set such that the frequency of the reference frequency signal and the frequency of the second frequency division signal are the same,
Wherein the reference frequency signal is an intermediate frequency signal,
Wherein the first frequency signal is a local oscillation frequency signal,
The second frequency signal is a sideband frequency signal
A method of driving a PLL circuit. 14. The method of claim 13,
Wherein the first PLL unit comprises a first phase frequency detector and the second PLL unit comprises a second phase frequency detector,
Wherein the first frequency-divided frequency signal and the reference frequency signal are compared in the first phase-frequency detector and the second frequency-divided frequency signal and the reference frequency signal are compared in the second phase-frequency detector
A method of driving a PLL circuit. delete 15. The method of claim 14,
Wherein the frequency difference between the first frequency signal and the second frequency signal is equal to the frequency of the reference frequency signal
A method of driving a PLL circuit. 17. The method of claim 16,
The control voltage of the first voltage controlled oscillator is determined corresponding to the output value of the first phase frequency detector and the control voltage of the second voltage controlled oscillator is determined in accordance with the output value of the second phase frequency detector Further comprising
A method of driving a PLL circuit. 14. The method of claim 13,
Dividing the clock signal into N3 to generate a third frequency-divided signal; And
Dividing the third divided frequency signal by N4 to generate a fourth divided frequency signal,
The fourth divided frequency signal is the reference frequency signal
A method of driving a PLL circuit. 19. The method of claim 18,
And using the third frequency-divided signal as the trigger signal of the ADC
A method of driving a PLL circuit.
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JP2006180349A (en) 2004-12-24 2006-07-06 Sharp Corp Phase locked loop circuit and semiconductor integrated circuit

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