KR101680970B1 - Integrated fan-out structure with openings in buffer layer - Google Patents

Integrated fan-out structure with openings in buffer layer Download PDF

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Publication number
KR101680970B1
KR101680970B1 KR1020150074280A KR20150074280A KR101680970B1 KR 101680970 B1 KR101680970 B1 KR 101680970B1 KR 1020150074280 A KR1020150074280 A KR 1020150074280A KR 20150074280 A KR20150074280 A KR 20150074280A KR 101680970 B1 KR101680970 B1 KR 101680970B1
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South Korea
Prior art keywords
package
molding compound
buffer layer
opening
layer
Prior art date
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KR1020150074280A
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Korean (ko)
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KR20160075299A (en
Inventor
징청 린
리후에이 청
포하오 차이
우선 치우
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타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드
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Priority claimed from US14/577,450 external-priority patent/US9455211B2/en
Application filed by 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 filed Critical 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드
Publication of KR20160075299A publication Critical patent/KR20160075299A/en
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Publication of KR101680970B1 publication Critical patent/KR101680970B1/en

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Abstract

패키지는 몰딩 화합물, 몰딩 화합물을 관통하는 쓰루 비아, 몰딩 화합물 내에 몰딩된 디바이스 다이, 및 몰딩 화합물과 접촉하면서 몰딩 화합물 상에 있는 버퍼층을 포함한다. 개구는 버퍼층을 관통하여 쓰루 비아에 이른다. 버퍼층은 몰딩 화합물과 버퍼층 사이의 계면에 평행한 평면에서 리플들을 개구의 둘레 주변에 갖는다. 다른 실시예들은 패키지에 접합된 추가적인 패키지, 및 패키지를 형성하기 위한 방법을 구상한다.The package comprises a molding compound, a throughvia through the molding compound, a device die molded in the molding compound, and a buffer layer on the molding compound in contact with the molding compound. The aperture penetrates the buffer layer and reaches the throughvia. The buffer layer has ripples around the periphery of the opening in a plane parallel to the interface between the molding compound and the buffer layer. Other embodiments envisage an additional package bonded to the package, and a method for forming the package.

Figure R1020150074280
Figure R1020150074280

Description

버퍼층에서 개구들을 갖는 집적 팬 아웃 구조물{INTEGRATED FAN-OUT STRUCTURE WITH OPENINGS IN BUFFER LAYER}[0001] INTEGRATED FAN-OUT STRUCTURE WITH OPENINGS IN BUFFER LAYER [0002]

본 출원은 “Integrated Fan-Out Structure with Guiding Trenches in Buffer Layer”이라는 명칭으로 2013년 9월 11일에 출원된 미국 특허 출원 14/024,311의 일부 계속 출원이며, 이 특허 출원 내용 전체는 참조로서 본 명세서내에 병합된다.This application is a continuation-in-part of U.S. Patent Application No. 14 / 024,311, filed on September 11, 2013, entitled " Integrated Fan-Out Structure with Guiding Trenches in Buffer Layer, "Lt; / RTI >

반도체 기술들의 진화로 인해, 반도체 칩/다이는 계속해서 점점 작아지고 있다. 그러는 동안, 보다 많은 기능들이 반도체 다이 내로 통합될 필요가 있다. 이에 따라, 반도체 다이는 보다 작은 영역 내에 계속해서 보다 많은 수의 I/O 패드들을 패킹할 필요가 있고, I/O 패드들의 밀도는 시간이 흘러감에 따라 급속도로 상승한다. 그 결과로서, 반도체 다이의 패키지화는 더욱 어려워지고, 이것은 패키지화의 수율에 악영향을 미친다.Due to the evolution of semiconductor technologies, semiconductor chips / dies are getting smaller and smaller. In the meantime, more functions need to be integrated into the semiconductor die. Accordingly, the semiconductor die needs to continuously pack a greater number of I / O pads in a smaller area, and the density of I / O pads rises rapidly with time. As a result, the packaging of the semiconductor die becomes more difficult, which adversely affects the yield of packaging.

통상적인 패키지 기술들은 두 개의 카테고리들로 분할될 수 있다. 제1 카테고리에서, 웨이퍼 상의 다이들은 자신들이 서잉(saw)되기 전에 패키지화된다. 이 패키지화 기술은 보다 큰 쓰루풋과 보다 낮은 비용과 같은, 몇가지 유리한 특징들을 갖는다. 또한, 언더필(underfill) 또는 몰딩 화합물이 거의 필요하지 않다. 하지만, 이 패키지화 기술은 또한 단점들로부터 고충을 겪는다. 앞서 언급한 바와 같이, 다이의 크기는 계속해서 점점 더 작아지고 있고, 각각의 패키지들은 단지 각각의 다이의 I/O 패드들이 각각의 다이의 표면 바로 위의 영역으로 제한되는 팬 인(fan-in) 타입 패키지들만일 수 있다. 다이의 제한된 영역들 때문에, I/O 패드들의 개수는 I/O 패드들의 피치의 제한으로 인해 제한된다. 패드들의 피치가 감소되면, 솔더 브릿지들이 발생할 수 있다. 추가적으로, 고정된 볼 크기 요건하에서, 솔더 볼들은 일정한 크기를 가져야만 하는데, 이것은 다이의 표면 상에 패킹(pack)될 수 있는 솔더 볼들의 개수를 제한시킨다.Conventional package technologies can be divided into two categories. In the first category, the dies on the wafer are packaged before they are sawed. This packaging technology has several advantageous features, such as greater throughput and lower cost. Also, underfilling or molding compounds are rarely needed. However, this packaging technique also suffers from shortcomings. As previously mentioned, the size of the die continues to become smaller and smaller, and each package is only fan-in, where the I / O pads of each die are limited to the area just above the surface of each die. ) Type packages. Because of the limited areas of the die, the number of I / O pads is limited due to the limitation of the pitch of the I / O pads. If the pitch of the pads is reduced, solder bridges may occur. Additionally, under fixed ball size requirements, the solder balls must have a certain size, which limits the number of solder balls that can be packed on the surface of the die.

나머지 다른 하나의 패키지화 카테고리에서는, 다이들이 패키지화되기 전에 웨이퍼들로부터 서잉되며, 오로지 "양품으로서 알려진 다이들"만이 패키지화된다. 이 패키지화 기술의 유리한 특징은 팬 아웃(fan-out) 패키지들을 형성할 가능성인데, 이것은 다이 상의 I/O 패드들이 다이보다 큰 영역으로 재분배될 수 있어서, 다이들의 표면들 상에 패킹된 I/O 패드들의 개수가 증가될 수 있다는 것을 의미한다.In the other packaging category, the dies are wafted from the wafers before being packaged, and only the "dies known as good" are packaged. An advantageous feature of this packaging technology is the possibility of forming fan-out packages, which can redistribute I / O pads on the die to areas larger than the die so that packed I / O Which means that the number of pads can be increased.

몇몇의 실시예들에 따르면, 바닥 패키지는 몰딩 화합물, 몰딩 화합물에 접촉하며 몰딩 화합물 위에 있는 버퍼층, 및 몰딩 화합물을 관통하는 쓰루 비아를 포함한다. 디바이스 다이는 몰딩 화합물 내에 몰딩된다. 가이딩 트렌치는 버퍼층의 최상단면으로부터 버퍼층 내로 연장하며, 가이딩 트렌치는 디바이스 다이와 오정렬된다.According to some embodiments, the bottom package includes a molding compound, a buffer layer in contact with the molding compound and above the molding compound, and a throughvia through the molding compound. The device die is molded into the molding compound. The guiding trenches extend from the top surface of the buffer layer into the buffer layer, and the guiding trenches are misaligned with the device die.

다른 실시예들에 따르면, 패키지는 바닥 패키지와, 바닥 패키지에 접합된 최상단 패키지를 포함한다. 바닥 패키지는 평면 최상단면과 평면 바닥면을 갖는 몰딩 화합물, 몰딩 화합물 내에 몰딩된 디바이스 다이, 몰딩 화합물의 평면 최상단면과 접촉하면서 이 평면 최상단면 위에 있는 평면 유전체층, 몰딩 화합물을 관통하는 쓰루 비아, 및 평면 유전체층 내에 있는 제1 가이딩 트렌치 링을 포함한다. 최상단 패키지는 갭에 의해 바닥 패키지로부터 이격되어 있으며, 제1 가이딩 트렌치 링이 갭에 연결된다. 언더필은 제1 가이딩 트렌치 링의 적어도 일부분과 갭의 주변을 채우고, 갭의 중심 부분은 언더필에 의해 에워싸여지며, 중심 부분은 빈 공간을 형성한다.According to other embodiments, the package includes a bottom package and a top package bonded to the bottom package. The bottom package comprises a molding compound having a planar top section and a planar bottom surface, a device die molded in the molding compound, a planar dielectric layer on top of the planar top section in contact with the planar top section of the molding compound, a throughvia passing through the molding compound, And a first guiding trench ring within the planar dielectric layer. The topmost package is spaced from the bottom package by a gap, and the first guiding trench ring is connected to the gap. The underfill fills at least a portion of the first guiding trench ring and the periphery of the gap, the central portion of the gap is surrounded by the underfill, and the central portion forms an empty space.

또다른 실시예들에 따르면, 방법은, 유전체 버퍼층 위에 쓰루 비아를 형성하는 단계, 유전체 버퍼층 위에 디바이스 다이를 배치하는 단계, 몰딩 화합물 내에 디바이스 다이와 쓰루 비아를 몰딩하는 단계, 및 몰딩 화합물을 평탄화하여 디바이스 다이의 금속 필라와 쓰루 비아를 노출시키는 단계를 포함한다. 쓰루 비아와 금속 필라에 전기적으로 결합되면서 이 쓰루 비아와 금속 필라 위에 재분배 라인들이 형성된다. 쓰루 비아를 노출시키기 위해 개구들이 유전체 버퍼층 내에 형성된다. 가이딩 트렌치 링이 유전체 버퍼층 내에 형성된다. According to yet other embodiments, the method includes forming a through-via on the dielectric buffer layer, placing a device die on the dielectric buffer layer, molding the device die and throughbia in the molding compound, and planarizing the molding compound to form a device And exposing the metal pillar and through vias of the die. Redistribution lines are formed on this throughvia and metal pillar, electrically coupled to thruvia and metal pillar. Openings are formed in the dielectric buffer layer to expose the through vias. A guiding trench ring is formed in the dielectric buffer layer.

추가적인 실시예들에 따르면, 구조물은 제1 패키지를 포함한다. 제1 패키지는 몰딩 화합물, 몰딩 화합물을 관통하는 쓰루 비아, 몰딩 화합물 내에 몰딩된 디바이스 다이, 및 몰딩 화합물과 접촉하면서 몰딩 화합물 상에 있는 버퍼층을 포함한다. 개구는 버퍼층을 관통하여 쓰루 비아에 이른다. 버퍼층은 몰딩 화합물과 버퍼층 사이의 계면에 평행한 평면에서 리플들을 개구의 둘레 주변에 갖는다.According to further embodiments, the structure comprises a first package. The first package comprises a molding compound, a throughvia through the molding compound, a device die molded into the molding compound, and a buffer layer on the molding compound in contact with the molding compound. The aperture penetrates the buffer layer and reaches the throughvia. The buffer layer has ripples around the periphery of the opening in a plane parallel to the interface between the molding compound and the buffer layer.

다른 추가적인 실시예들에 따르면, 구조물은 제1 패키지와, 제1 패키지에 접합된 제2 패키지를 포함한다. 제1 패키지는 평면 최상단면과 평면 바닥면을 포함하는 몰딩 화합물, 몰딩 화합물에 의해 횡측으로 캡슐화된 디바이스 다이, 몰딩 화합물을 관통하는 쓰루 비아, 및 몰딩 화합물의 평면 최상단면과 접촉하면서 이 평면 최상단면 위에 있는 평면 유전체층을 포함한다. 개구는 평면 유전체층을 관통하여 쓰루 비아에 이른다. 개구를 둘러싸는 평면 유전체층 내에 리플들이 존재한다. 외부 전기적 커넥터는 제1 패키지를 제2 패키지에 전기적으로 결합시키고, 외부 전기적 커넥터는 개구 내에 적어도 부분적으로 배치된다.According to further additional embodiments, the structure comprises a first package and a second package bonded to the first package. The first package comprises a molding compound comprising a planar top section and a planar bottom surface, a device die transversely encapsulated by the molding compound, a throughvia passing through the molding compound, and a planar top section of the molding compound, Lt; RTI ID = 0.0 > dielectric < / RTI > The openings penetrate the planar dielectric layer to the through vias. There are ripples in the planar dielectric layer surrounding the aperture. The external electrical connector electrically couples the first package to the second package, and the external electrical connector is disposed at least partially within the opening.

또다른 추가적인 실시예들에 따르면, 방법은 패키지를 형성하는 단계를 포함한다. 패키지를 형성하는 단계는 복합 구조물을 형성하는 단계를 포함한다. 복합 구조물은 디바이스 다이, 몰딩 화합물, 및 쓰루 비아를 포함한다. 몰딩 화합물은 몰딩 화합물의 제1 표면과 몰딩 화합물의 제2 표면 사이에 있는 디바이스 다이를 적어도 횡측으로 캡슐화한다. 쓰루 비아는 몰딩 화합물 내에 있고 몰딩 화합물의 제1 표면으로부터 몰딩 화합물의 제2 표면까지 연장한다. 패키지를 형성하는 단계는 몰딩 화합물의 제1 표면 상에 버퍼층을 형성하는 단계, 및 레이저 드릴링을 이용하여 버퍼층을 관통하여 쓰루 비아에 이르는 개구를 형성하는 단계를 더 포함한다. 버퍼층은 개구 주변에서 리플들을 갖는다.According to still further embodiments, the method includes forming a package. The step of forming the package includes forming the composite structure. The composite structure includes device die, molding compound, and throughvia. The molding compound encapsulates the device die at least transversely between the first surface of the molding compound and the second surface of the molding compound. The throughvia is within the molding compound and extends from the first surface of the molding compound to the second surface of the molding compound. The forming of the package further comprises forming a buffer layer on the first surface of the molding compound and forming an opening through the buffer layer using laser drilling to the throughbia. The buffer layer has ripples around the aperture.

본 발명개시의 실시예들에서, TIV 패키지 및 그 위에 있는 최상단 패키지는 에어 갭 또는 진공상태 빈 공간일 수 있는 빈 공간에 의해 서로 분리된다. 이러한 빈 공간의 단열(heat-insulating) 능력은 언더필의 단열 능력보다 우수하기 때문에, 이러한 빈 공간은 TIV 패키지 내의 디바이스 다이에서의 열이 최상단 패키지 내의 다이들로 전도되는 것을 방지하고 이러한 최상단 패키지 내의 다이들의 동작에 영향을 미치는 것을 방지하는 우수한 능력을 갖는다. 만약 가이딩 트렌치들이 형성되지 않으면, TIV 패키지와 최상단 패키지 사이의 갭 내로 언더필이 채워지는 거리들은 무작의적이고, 이에 따라 빈 공간들의 형성은 불균일할 것이라는 점을 알 것이다. 버퍼층 내의 가이딩 트렌치들의 형성을 통해, 빈 공간의 형성은 보다 제어가능하며, 보다 균일하다.In embodiments of the present disclosure, the TIV package and the uppermost package thereon are separated from each other by an empty space, which may be an air gap or a vacuum state void space. This void space prevents heat from the device die in the TIV package from being conducted to the dies in the top-end package, because the heat-insulating capability of such void space is superior to the insulating capability of the underfill, And has an excellent ability to prevent influences on the operation of the apparatus. If the guiding trenches are not formed, then the distances to fill the underfill into the gap between the TIV package and the topmost package will be random and thus the formation of void spaces will be non-uniform. Through the formation of the guiding trenches in the buffer layer, the formation of voids is more controllable and more uniform.

본 실시예들 및 이들의 이점에 대한 보다 완벽한 이해를 위하여, 이하에서는 첨부된 도면과 결합한 다음 설명들을 참조한다.
도 1 내지 도 12 및 도 13a는 몇몇의 예시적인 실시예들에 따른 쓰루 집적형 팬 아웃 비아(Through Integrated fan-out Via; TIV) 패키지의 제조에서의 중간 스테이지들의 단면도들이다.
도 13b 내지 도 13d는 몇몇의 예시적인 실시예들에 따른 TIV 패키지에서 형성된 개구의 도면들이다.
도 13e 내지 도 13j는 몇몇의 예시적인 실시예들에 따른 TIV 패키지에서 형성된, 다양한 치수들을 갖는 개구들의 레이아웃도들이다.
도 14a와 도 14b는 몇몇의 예시적인 실시예들에 따른 TIV 패키지의 단면도와 평면도를 각각 나타낸다.
도 15는 최상단 패키지와 TIV 패키지의 접합을 나타낸다.
도 16은 몇몇의 대안적인 예시적 실시예들에 따른 TIV 패키지와 최상단 패키지 사이의 갭 내로의 언더필의 디스펜싱(dispensing)을 나타낸다.BRIEF DESCRIPTION OF THE DRAWINGS For a more complete understanding of the embodiments and their advantages, reference is made to the following descriptions taken in conjunction with the accompanying drawings, in which:
Figures 1 to 12 and 13A are cross-sectional views of intermediate stages in the manufacture of a through integrated fan-out vias (TIV) package in accordance with some exemplary embodiments.
Figures 13B-D are illustrations of an opening formed in a TIV package in accordance with some exemplary embodiments.
Figures 13E-13J are layout diagrams of apertures having various dimensions formed in a TIV package in accordance with some exemplary embodiments.
14A and 14B show a cross-sectional view and a plan view, respectively, of a TIV package according to some exemplary embodiments.
15 shows the junction of the top package and the TIV package.
Figure 16 illustrates the dispensing of underfill into the gap between the TIV package and the topmost package in accordance with some alternative exemplary embodiments.

본 개시의 실시예들의 실시 및 이용을 아래 보다 자세히 설명한다. 그러나, 본 실시예들은 폭넓게 다양한 특정 환경들에서 구체화될 수 있는 많은 적용가능한 개념들을 제공한다는 것을 알아야 한다. 설명하는 특정한 실시예들은 본 발명개시의 예시에 불과하며, 본 발명개시의 범위를 한정시키려는 것은 아니다.The implementation and use of embodiments of the present disclosure are described in more detail below. It should be understood, however, that the embodiments provide a number of applicable concepts that may be embodied in a wide variety of specific environments. The specific embodiments described are merely illustrative of the disclosure of the invention and are not intended to limit the scope of the disclosure.

쓰루 비아들을 포함한 집적형 팬 아웃(Integrated Fan-Out; InFO) 패키지 및 그 형성 방법이 다양한 예시적인 실시예들에 따라 제공된다. InFO 패키지를 형성하는 중간 스테이지들이 도시된다. 본 실시예들의 변형들을 논의한다. 다양한 도면들과 예시적인 실시예들 전반에 걸쳐, 동일한 엘리먼트들을 지정하기 위해 동일한 참조 번호들이 이용된다.An integrated fan-out (InFO) package including through vias and a method of forming the same are provided in accordance with various exemplary embodiments. The intermediate stages forming the InFO package are shown. Variations of these embodiments are discussed. Throughout the various drawings and the exemplary embodiments, the same reference numerals are used to designate the same elements.

도 1 내지 도 12, 도 13a, 도 14a, 도 15 및 도 16은 몇몇의 예시적인 실시예들에 따른 패키지 구조물의 제조에 있어서의 중간 스테이지들의 단면도들이다. 도 1을 참조하면, 캐리어(20)가 제공되고, 접착제층(22)이 캐리어(20) 상에 배치된다. 캐리어(20)는 블랭크 유리 캐리어, 블랭크 세라믹 캐리어 등일 수 있다. 접착제층(22)은 극자외선(Ultra-Violet; UV) 아교, 광열변환(Light-to-Heat Conversion; LTHC) 아교 등과 같은 접착제로 형성될 수 있지만, 다른 유형들의 접착제들이 이용될 수 있다. Figures 1 to 12, 13A, 14A, 15 and 16 are cross-sectional views of intermediate stages in the manufacture of a package structure according to some exemplary embodiments. Referring to FIG. 1, a carrier 20 is provided, and an adhesive layer 22 is disposed on the carrier 20. The carrier 20 may be a blank glass carrier, a blank ceramic carrier, or the like. The adhesive layer 22 may be formed of an adhesive such as Ultra-Violet (UV) glue, Light-to-Heat Conversion (LTHC) glue, or the like, but other types of adhesives may be used.

도 2를 참조하면, 버퍼층(24)이 접착제층(22) 위에 형성된다. 버퍼층(24)은 폴리머를 포함하는 폴리머층일 수 있는 유전체층이다. 폴리머는 예컨대, 폴리이미드, PBO(PolyBenzOxazole), BCB(BenzoCycloButene), ABF(Ajinomoto Buildup Film), SR(Solder Resist film) 등일 수 있다. 버퍼층(24)은 균일한 두께를 갖는 평면층이며, 두께(T1)는 약 2㎛보다 클 수 있고, 약 2㎛와 약 40㎛ 사이일 수 있다. 버퍼층(24)의 최상단면과 바닥면이 또한 평면이다.Referring to FIG. 2, a buffer layer 24 is formed over the adhesive layer 22. The buffer layer 24 is a dielectric layer which may be a polymer layer containing a polymer. The polymer may be, for example, polyimide, PBO (PolyBenzOxazole), BCB (BenzoCycloButene), ABF (Ajinomoto Buildup Film), SR (Solder Resist film) and the like. The buffer layer 24 is a planar layer having a uniform thickness, and the thickness Tl may be greater than about 2 占 퐉, and may be between about 2 占 퐉 and about 40 占 퐉. The top surface and the bottom surface of the buffer layer 24 are also planar.

시드층(26)은 예컨대, 물리적 기상 증착(Physical Vapor Deposition; PVD) 또는 금속 포일 라미네이팅을 통해 버퍼층(24) 상에 형성된다. 시드층(26)은 구리, 구리 합금, 알루미늄, 티타늄, 티타늄 합금, 또는 이들의 조합들을 포함할 수 있다. 몇몇의 실시예들에서, 시드층(26)은 티타늄층(26A)과, 티타늄층(26A) 위의 구리층(26B)을 포함한다. 대안적인 실시예들에서, 시드층(26)은 구리층이다. The seed layer 26 is formed on the buffer layer 24, for example, through physical vapor deposition (PVD) or metal foil laminating. Seed layer 26 may comprise copper, a copper alloy, aluminum, titanium, a titanium alloy, or combinations thereof. In some embodiments, the seed layer 26 includes a titanium layer 26A and a copper layer 26B over the titanium layer 26A. In alternate embodiments, the seed layer 26 is a copper layer.

도 3을 참조하면, 포토레지스트(28)가 시드층(26) 위에 도포되고, 그 후 패터닝된다. 그 결과로서, 개구들(30)이 포토레지스트(28) 내에 형성되고, 이 포토레지스트(28)를 통해 시드층(26)의 일부분들이 노출된다. Referring to FIG. 3, a photoresist 28 is applied over the seed layer 26, and then patterned. As a result, openings 30 are formed in the photoresist 28 and portions of the seed layer 26 are exposed through the photoresist 28.

도 4에서 도시된 바와 같이, 금속 피처들(32)이 도금을 통해 포토레지스트(28) 내에 형성되고, 이 도금은 전기 도금 또는 무전해 도금일 수 있다. 금속 피처들(32)은 시드층(26)의 노출된 부분들 상에 도금된다. 금속 피처들(32)은 구리, 알루미늄, 텅스텐, 니켈, 솔더, 또는 이들의 합금들을 포함할 수 있다. 금속 피처들(32)의 평면도 형상들은 직사각형, 정사각형, 원형 등일 수 있다. 금속 피처들(32)의 높이는 나중에 배치되는 다이들(34)(도 7 참조)의 두께에 의해 결정되며, 몇몇의 실시예들에서 금속 피처들(32)의 높이는 다이들(34)의 두께보다 크다. 금속 피처들(32)의 도금 후, 포토레지스트(28)가 제거되고, 결과적인 구조물이 도 5에서 도시된다. 포토레지스트(28)가 제거된 후, 포토레지스트(28)에 의해 덮혀진 시드층(26)의 일부분들은 노출된다. As shown in FIG. 4, metal features 32 are formed in the photoresist 28 through plating, which may be electroplating or electroless plating. Metal features 32 are plated on the exposed portions of the seed layer 26. The metal features 32 may include copper, aluminum, tungsten, nickel, solder, or alloys thereof. The topographic features of the metal features 32 may be rectangular, square, circular, and the like. The height of the metal features 32 is determined by the thickness of later placed dies 34 (see FIG. 7), and in some embodiments the height of the metal features 32 is less than the thickness of the dies 34 Big. After plating the metal features 32, the photoresist 28 is removed and the resulting structure is shown in FIG. After the photoresist 28 is removed, portions of the seed layer 26 covered by the photoresist 28 are exposed.

도 6을 참조하면, 시드층(26)의 노출된 부분들을 제거하기 위해 에칭 단계가 수행되며, 이러한 에칭은 이방성 에칭일 수 있다. 한편, 금속 피처들(32)과 오버랩하는 시드층(26)의 일부분들은 에칭되지 않고 남아있다. 설명 전반에 걸쳐, 금속 피처들(32) 및 금속 피처들(32) 아래에 남아있는 시드층(26)의 일부분들을 조합하여 쓰루 InFO 비아(Through InFO Via; TIV)(33)라고 부르며, 이것을 쓰루 비아(33)라고도 부른다. 시드층(26)이 금속 피처들(32)과 별개의 층으로서 도시되지만, 시드층(26)이 위에 있는 각각의 금속 피처들(32)과 유사하거나 또는 동일한 물질로 형성될 때, 시드층(26)은 자신과 금속 피처들(32) 사이에 어떠한 구별적인 계면을 갖지 않고서 금속 피처들(32)과 병합될 수 있다. 대안적인 실시예들에서, 시드층(26)과 위에 있는 금속 피처들(32) 사이에 구별적인 계면들이 존재한다. Referring to FIG. 6, an etching step is performed to remove exposed portions of the seed layer 26, which may be an anisotropic etch. On the other hand, portions of the seed layer 26 overlapping with the metal features 32 remain unetched. Throughout the description, the metal features 32 and portions of the seed layer 26 remaining under the metal features 32 are referred to as through InFO Via (TIV) 33, It is also called Tsurubia (33). Although the seed layer 26 is shown as a separate layer from the metal features 32, when the seed layer 26 is formed of a material similar or identical to the respective metal features 32 on it, the seed layer 26 26 may be merged with the metal features 32 without any distinctive interface between themselves and the metal features 32. In alternative embodiments, there are distinct interfaces between the seed layer 26 and the overlying metal features 32.

도 7은 버퍼층(24) 위의 디바이스 다이들(34)의 배치를 도시한다. 디바이스 다이들(34)은 접착제층(들)(36)을 통해 버퍼층(24)에 부착될 수 있다. 디바이스 다이들(34)은 논리 트랜지스터들을 내부에 포함한 논리 디바이스 다이들일 수 있다. 몇몇의 예시적인 실시예들에서, 디바이스 다이들(34)은 모바일 응용들을 위해 설계되며, 중앙 처리 장치(Central Computing Unit; CPU) 다이, 전력 관리 집적 회로(Power Management Integrated Circuit; PMIC) 다이, 트랜스시버(Transceiver; TRX) 다이 등일 수 있다. 디바이스 다이들(34) 각각은 접착제층(36)과 접촉하는 반도체 기판(35)(예컨대, 실리콘 기판)을 포함하며, 이 때 반도체 기판(35)의 후면이 접착제층(36)과 접촉한다.Figure 7 shows the placement of device dies 34 on the buffer layer 24. The device dies 34 may be attached to the buffer layer 24 through the adhesive layer (s) 36. Device dies 34 may be logic device dies that contain logic transistors therein. In some exemplary embodiments, the device dies 34 are designed for mobile applications and include a central processing unit (CPU) die, a power management integrated circuit (PMIC) die, a transceiver A transceiver (TRX) die, or the like. Each of the device dies 34 includes a semiconductor substrate 35 (e.g., a silicon substrate) in contact with an adhesive layer 36, wherein the backside of the semiconductor substrate 35 contacts the adhesive layer 36.

몇몇의 예시적인 실시예들에서, (구리 포스트와 같은) 금속 필라들(40)이 디바이스 다이들(34)의 최상단부들로서 형성되고, 디바이스 다이들(34) 내의 트랜지스터(미도시됨)와 같은 디바이스들에 전기적으로 결합된다. 몇몇의 실시예들에서, 유전체층(38)이 각각의 디바이스 다이(34)의 최상단면에 형성되며, 금속 필라들(40)은 적어도 유전체층(38) 내에 있는 하위 부분들을 갖는다. 몇몇의 실시예들에서 금속 필라들(40)의 최상단면들은 또한 유전체층(38)의 최상단면들과 동일한 높이에 있을 수 있다. 대안적으로, 유전체층들(38)은 형성되지 않고, 금속 필라들(40)은 각각의 디바이스 다이들(34)의 최상단 유전체층 위로 돌출한다.In some exemplary embodiments, metal pillars 40 (such as copper posts) are formed as the top edges of the device dies 34, such as transistors (not shown) in the device dies 34 And are electrically coupled to the devices. In some embodiments, a dielectric layer 38 is formed in the top surface of each device die 34, and the metal pillars 40 have lower portions that are at least in the dielectric layer 38. In some embodiments, the top surfaces of the metal pillars 40 may also be at the same height as the top surfaces of the dielectric layer 38. Alternatively, the dielectric layers 38 are not formed, and the metal pillars 40 project over the uppermost dielectric layer of each device die 34.

도 8을 참조하면, 몰딩 물질(42)이 디바이스 다이들(34)과 TIV(33) 상에서 몰딩된다. 몰딩 물질(42)은 디바이스 다이들(34)과 TIV(33) 사이의 갭들을 채우고, 버퍼층(24)과 접촉할 수 있다. 또한, 금속 필라들(40)이 돌출 금속 필라들인 경우, 몰딩 물질(42)이 금속 필라들(40) 사이의 갭들 내로 채워진다. 몰딩 물질(42)은 몰딩 화합물, 몰딩 언더필, 에폭시, 또는 수지를 포함할 수 있다. 몰딩 물질(42)의 최상단면은 금속 필라들(40)과 TIV(33)의 최상단 말단부들보다 높다. Referring to FIG. 8, a molding material 42 is molded over the device dies 34 and the TIV 33. The molding material 42 fills gaps between the device dies 34 and the TIV 33 and may contact the buffer layer 24. Also, when the metal pillars 40 are protruding metal pillars, the molding material 42 is filled into the gaps between the metal pillars 40. The molding material 42 may comprise a molding compound, molding underfill, epoxy, or resin. The uppermost end surface of the molding material 42 is higher than the uppermost end portions of the metal pillars 40 and the TIV 33.

다음으로, 금속 필라들(40)과 TIV(33)가 노출될 때 까지, 몰딩 물질(42)을 시닝(thin)하기 위해 그라인딩 단계가 수행된다. 결과적인 구조물이 도 9에 도시된다. 그라인딩으로 인해, 금속 피처들(32)의 최상단 말단부들(32A)은 금속 필라들(40)의 최상단 말단부들(40A)과 실질적으로 동일한 높이(동평면)에 있고, 몰딩 물질(42)의 최상단면(42A)과 실질적으로 동일한 높이(동평면)에 있다. 그라인딩의 결과로서, 금속 입자들과 같은 금속 잔류물들이 생성되어서, 최상단면들(32A, 40A, 42A) 상에 남아있을 수 있다. 이에 따라, 그라인딩 이후, 금속 잔류물이 제거되도록, 세정이, 예컨대 습식 에칭을 통해 수행될 수 있다. Next, a grinding step is performed to thin the molding material 42 until the metal pillars 40 and the TIV 33 are exposed. The resulting structure is shown in Fig. The uppermost end portions 32A of the metal features 32 are at substantially the same height (coplanar) as the uppermost end portions 40A of the metal pillars 40, And is substantially at the same height (same plane) as the end surface 42A. As a result of the grinding, metal residues such as metal particles can be created and remain on the top surfaces 32A, 40A, 42A. Thus, after grinding, cleaning can be performed, for example, by wet etching, so that metal residues are removed.

다음으로, 도 10을 참조하면, 금속 필라들(40)과 TIV(33)에 연결하기 위한 재분배 라인(Redistribution Line; RDL)들(44)이 몰딩 물질(42) 위에 형성된다. RDL들(44)은 또한 금속 필라들(40)과 TIV(33)를 상호연결시킬 수 있다. 다양한 실시예들에 따르면, 하나 또는 복수의 유전체층들(46)이 도 9에서 도시된 구조물 위에 형성되며, 이 때 RDL들(44)은 유전체층들(46) 내에 형성된다. 몇몇의 실시예들에서, RDL들(44)과 유전체층들(46)의 하나의 층의 형성은 블랭킷(blanket) 구리 시드층을 형성하는 것, 블랭킷 구리 시드층 위에 마스크층을 형성하고 패터닝하는 것, RDL들(44)을 형성하기 위한 도금을 수행하는 것, 마스크층을 제거하는 것, 및 RDL들(44)에 의해 덮혀있지 않은 블랭킷 구리 시드층의 일부분들을 제거하기 위해 플래쉬(flash) 에칭을 수행하는 것을 포함한다. 대안적인 실시예들에서, 금속층들을 퇴적하고, 금속층들을 패터닝하며, RDL들(44) 사이의 갭들을 유전체층들(46)로 채움으로써 RDL들(44)이 형성된다. RDL들(44)은 알루미늄, 구리, 텅스텐, 및/또는 이들의 합금들을 비롯한 금속 또는 금속 합금을 포함할 수 있다. 도 10은 두 개의 층의 RDL들(44)을 도시하지만, 각각의 패키지의 라우팅 요건에 따라, 하나 또는 두 개보다 많은 층의 RDL들이 존재할 수 있다. 이러한 실시예들에서의 유전체층들(46)은 폴리이미드, BCB(benzocyclobutene), PBO(polybenzoxazole) 등과 같은 폴리머를 포함할 수 있다. 대안적으로, 유전체층들(46)은 실리콘 산화물, 실리콘 질화물, 실리콘 탄화물, 실리콘 산화질화물 등과 같은 무기 유전체 물질들을 포함할 수 있다.10, redistribution lines (RDLs) 44 for connection to the metal pillars 40 and the TIV 33 are formed on the molding material 42. Next, as shown in FIG. The RDLs 44 may also interconnect the metal pillars 40 and the TIV 33. According to various embodiments, one or more dielectric layers 46 are formed over the structure shown in FIG. 9, wherein the RDLs 44 are formed in the dielectric layers 46. In some embodiments, the formation of one layer of RDLs 44 and dielectric layers 46 may be accomplished by forming a blanket copper seed layer, forming and patterning a mask layer over the blanket copper seed layer , Performing plating to form the RDLs 44, removing the mask layer, and flash etching to remove portions of the blanket copper seed layer that are not covered by the RDLs 44 . ≪ / RTI > In alternative embodiments, the RDLs 44 are formed by depositing metal layers, patterning the metal layers, and filling the gaps between the RDLs 44 with the dielectric layers 46. The RDLs 44 may comprise a metal or metal alloy, including aluminum, copper, tungsten, and / or alloys thereof. Figure 10 shows two layers of RDLs 44, but depending on the routing requirements of each package, there may be more than one or two layers of RDLs. The dielectric layers 46 in these embodiments may include polymers such as polyimide, benzocyclobutene (BCB), polybenzoxazole (PBO), and the like. Alternatively, the dielectric layers 46 may comprise inorganic dielectric materials such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, and the like.

도 11은 몇몇의 예시적인 실시예들에 따른 전기적 커넥터들(48)의 형성을 도시한다. 전기적 커넥터들(48)의 형성은 RDL들(44)의 노출된 부분들 상에 솔더 볼들(또는, 언더 범프 금속들이 형성되는 경우, 이러한 언더 범프 금속들(미도시됨))을 배치하고, 그 후 솔더 볼들을 리플로우(reflow)시키는 것을 포함할 수 있다. 대안적인 실시예들에서, 전기적 커넥터들(48)의 형성은 RDL들(44) 위에 솔더 영역들을 형성하기 위한 도금 단계를 수행하고, 그 후 솔더 영역들을 리플로우시키는 것을 포함한다. 전기적 커넥터들(48)은 또한 금속 필라들, 또는 금속 필라들과 솔더 캡들을 포함할 수 있으며, 이 때의 솔더 캡들은 또한 도금을 통해 형성될 수 있다. 설명 전반에 걸쳐, 디바이스 다이들(34), TIV들(33), 몰딩 물질(42), 위에 있는 RDL들(44)과 유전체층들(46), 및 버퍼층(24)을 포함하는 결합된 구조물을 복합 웨이퍼일 수 있는 TIV 패키지(50)라고 부른다. Figure 11 illustrates the formation of electrical connectors 48 in accordance with some exemplary embodiments. The formation of the electrical connectors 48 may be accomplished by placing solder balls (or such underbump metals (not shown) if underbump metals are formed) on the exposed portions of the RDLs 44, And then reflowing the solder balls. In alternate embodiments, the formation of the electrical connectors 48 includes performing a plating step to form solder regions over the RDLs 44, and then reflowing the solder regions. The electrical connectors 48 may also include metal pillar or metal pillar and solder caps, wherein the solder caps may also be formed through plating. Throughout the description, device structures 34, TIVs 33, molding material 42, coupled structures including RDLs 44 and dielectric layers 46 on top, and buffer layer 24, Called TIV package 50, which can be a composite wafer.

다음으로, TIV 패키지(50)는 캐리어(20)로부터 접합해제된다. 접착제층(22)이 또한 TIV 패키지(50)로부터 치워진다. 결과적인 구조물이 도 12에 도시된다. 접착제층(22)의 제거의 결과로서, 버퍼층(24)이 노출된다. TIV 패키지(50)는 추가적으로 다이싱 테이프(52)에 부착되는데, 이 때 전기적 커넥터들(48)은 다이싱 테이프(52) 쪽을 향해 있고 다이싱 테이프(52)와 접촉할 수 있다. 몇몇의 실시예들에서, 라미네이팅막(54)이 노출된 버퍼층(24) 상에 배치되며, 라미네이팅막(54)은 SR, ABF, 후면 코팅 테이프 등을 포함할 수 있다. 대안적인 막에서, 어떠한 라미네이팅막(54)도 버퍼층(24) 위에 배치되지 않는다.Next, the TIV package 50 is unjoined from the carrier 20. The adhesive layer 22 is also removed from the TIV package 50. The resulting structure is shown in Fig. As a result of the removal of the adhesive layer 22, the buffer layer 24 is exposed. The TIV package 50 is additionally attached to the dicing tape 52 at which time the electrical connectors 48 are directed toward the dicing tape 52 and may contact the dicing tape 52. In some embodiments, the laminating film 54 is disposed on the exposed buffer layer 24, and the laminating film 54 may include SR, ABF, back coating tape, and the like. In an alternative film, no laminating film 54 is disposed over the buffer layer 24.

도 13a는 버퍼층(24) 및 라미네이팅막(54)(존재하는 경우)의 개구를 도시한다. 개구들(56)과 가이딩 트렌치들(58)이 버퍼층(24)과 라미네이팅막(54)에 형성된다. 몇몇의 실시예들에 따르면, 개구들(56)과 가이딩 트렌치들(58)은 레이저 드릴링(laser drilling)을 이용하여 형성되지만, 포토리소그래피 공정들이 또한 이용될 수 있다. TIV들(33)은 개구들(56)을 통해 노출된다. 시드층(26)(도 2 참조)이 티타늄 부분(26A)을 포함하는 실시예들에서, 구리 부분(26B)을 제거하기 위해 에칭 단계가 수행되며, 이로써 시드층(26)의 티타늄 부분(26A)은 노출된다. 그렇지 않고, 시드층(26)이 티타늄을 포함하지 않으면, 에칭 단계는 건너뛴다. 13A shows the opening of the buffer layer 24 and the laminating film 54 (if present). Openings 56 and guiding trenches 58 are formed in the buffer layer 24 and the laminating film 54. According to some embodiments, openings 56 and guiding trenches 58 are formed using laser drilling, but photolithographic processes may also be used. The TIVs 33 are exposed through the openings 56. In embodiments where the seed layer 26 (see FIG. 2) includes a titanium portion 26A, an etching step is performed to remove the copper portion 26B, thereby removing the titanium portion 26A of the seed layer 26 ) Is exposed. Otherwise, if the seed layer 26 does not contain titanium, the etching step is skipped.

도 13b 내지 도 13d는 레이저 드릴링을 이용하여 형성될 때의 개구들(56)의 양태들을 도시하며, 도 13e 내지 도 13j는 다양한 크기들을 갖는 예시적인 개구들(56)을 도시한다. 도 13b는 라미네이팅막(54)과 버퍼층(24)에서의 개구(56)의 일부분의 (예컨대, 도 13a의 단면도에 대응하는 X-Z 평면의) 단면도를 도시한다. 버퍼층(24)은 개구(56)를 형성하기 위한 레이저 드릴링(82)의 결과로서 리플(80)을 가질 수 있다. 레이저 드릴링(82)(예컨대, 레이저)은 다양한 층들의 (예컨대, 도시된 Z 방향의) 법선(84)에 대한 입사각 θ로 이러한 층들에 부딪칠 수 있다. 도시된 바와 같이, 리플(80)은 버퍼층(24)에 형성되며, 다른 실시예들에서, 리플(80)은 또한 (라미네이팅막(54)이 존재하는 경우) 라미네이팅막(54)에 형성될 수 있다. 도면에서, 버퍼층(24) 내의 리플(80)은 라미네이팅막(54)의 측벽으로부터 멀어지는 방향으로 개구(56) 쪽을 향해 돌출해 있다.FIGS. 13B-13D illustrate aspects of openings 56 when formed using laser drilling, and FIGS. 13E-13J illustrate exemplary openings 56 having various sizes. Figure 13B shows a cross-sectional view of a portion of the opening 56 in the laminating film 54 and the buffer layer 24 (e.g., in the X-Z plane corresponding to the cross-sectional view of Figure 13A). The buffer layer 24 may have a ripple 80 as a result of laser drilling 82 to form an opening 56. Laser drilling 82 (e.g., a laser) may strike these layers at an angle of incidence? Relative to the normal 84 of the various layers (e.g., in the illustrated Z direction). As shown, the ripple 80 is formed in the buffer layer 24, and in other embodiments, the ripple 80 can also be formed in the laminating film 54 (if the laminating film 54 is present) have. In the figure, the ripple 80 in the buffer layer 24 protrudes toward the opening 56 in the direction away from the side wall of the laminating film 54.

도 13c와 도 13d는 개구(56)의 (예컨대, X-Y 평면의) 레이아웃도를 도시한다. 도 13d는 도 13c에서의 삽도(inset)(86)를 보다 상세하게 도시한다. 버퍼층(24)에서의 리플들(80)은 개구(56)의 둘레 주변에 형성된다. 리플들(80)은 개구(56)의 둘레 주변에서 주기적으로 구성되어 있을 수 있다. 개구(56)는 직경(D)을 가질 수 있는데, 이 직경(D)은 개구(56)에 의해 노출된 시드층(26) 및/또는 TIV(33)의 일부분의 직경일 수 있다. 직경(D)은 순시적 직경(instantaneous diameter)의 관점에서 표현될 수 있으며, 이 직경은 리플(80)에서 반대편 리플(80)까지, 골에서 반대편 골까지, 또는 골에서 반대편 리플(80)까지일 수 있다. 평균 직경(DAVE)은 개구(56)의 순시적 직경(D)의 평균으로서 표현될 수 있다. 몇몇의 실시예들에서, 개구(56)의 평균 직경(DAVE)은 약 10㎛ 내지 약 600㎛일 수 있다.13C and 13D show a layout of the opening 56 (e.g., in the XY plane). Figure 13d shows the inset 86 in Figure 13c in more detail. Ripples 80 in the buffer layer 24 are formed around the periphery of the opening 56. The ripples 80 may be periodically configured around the perimeter of the opening 56. The opening 56 may have a diameter D which may be the diameter of a portion of the seed layer 26 and / or the TIV 33 exposed by the opening 56. The diameter D may be expressed in terms of an instantaneous diameter which may range from the ripple 80 to the opposite ripple 80, from the bone to the opposite bone, or from the bone to the opposite lip 80 Lt; / RTI > The average diameter D AVE can be expressed as an average of the instantaneous diameters D of the openings 56. In some embodiments, the average diameter (D AVE ) of the openings 56 may be between about 10 microns and about 600 microns.

이웃하는 리플들(80)은 피크간 거리(Δ)를 가질 수 있다. 또한, 리플들(80)은 골과 피크간 높이(H)를 가질 수 있다. 몇몇의 실시예들에서, 리플들(80)의 높이(H)는 약 0.2㎛ 내지 약 20㎛일 수 있다. 몇몇의 실시예들에서, 거리(Δ)는 약 0.2㎛ 내지 약 20㎛일 수 있다. 몇몇의 실시예들에서, 거리(Δ)는

Figure 112015051065232-pat00001
로서 표현될 수 있으며, 여기서, λ는 방사선, 예컨대 레이저 드릴링에서 이용되는 레이저의 파장이며, θ는 (도 13b에서 도시된 바와 같이) 레이저 드릴링에서 이용되는 방사선의 입사각이다. 몇몇의 실시예들에서, 레이저 드릴링의 레이저 소스는 UV 소스(355㎚의 파장을 가질 수 있음), 녹색 소스(532㎚의 파장을 가질 수 있음), Nd:YAG 소스(1064㎚의 파장을 가질 수 있음), CO2 소스(9.4㎛의 파장을 가질 수 있음) 등일 수 있다. 도 13c와 도 13d에서 도시된 실시예에서, 높이(H)는 대략 8㎛이고, 거리(Δ)는 대략 10㎛이다.Neighboring ripples 80 may have a peak-to-peak distance [Delta]. Further, the ripples 80 may have a height (H) between the valley and the peak. In some embodiments, the height H of the ripples 80 may be about 0.2 [mu] m to about 20 [mu] m. In some embodiments, the distance [Delta] may be between about 0.2 [mu] m and about 20 [mu] m. In some embodiments, the distance [Delta]
Figure 112015051065232-pat00001
Where lambda is the wavelength of the laser used in the laser, e.g. laser drilling, and [theta] is the angle of incidence of the radiation used in laser drilling (as shown in Fig. 13B). In some embodiments, the laser source of laser drilling may be a UV source (which may have a wavelength of 355 nm), a green source (which may have a wavelength of 532 nm), an Nd: YAG source CO 2 source (which may have a wavelength of 9.4 탆), and the like. In the embodiment shown in Figures 13c and 13d, the height H is approximately 8 占 퐉 and the distance? Is approximately 10 占 퐉.

도 13e 내지 도 13j는 상이한 평균 직경들(DAVE)을 갖는 개구들(56)의 (예컨대, X-Y 평면의) 레이아웃도들을 도시한다. 도 13e에서의 개구(56)의 평균 직경(DAVE)은 80㎛이다. 도 13f에서의 개구(56)의 평균 직경(DAVE)은 120㎛이다. 도 13g에서의 개구(56)의 평균 직경(DAVE)은 152㎛이다. 도 13h에서의 개구(56)의 평균 직경(DAVE)은 190㎛이다. 도 13i에서의 개구(56)의 평균 직경(DAVE)은 220㎛이다. 도 13j에서의 개구(56)의 평균 직경(DAVE)은 250㎛이다.Figures 13E-13J show layout diagrams (e.g., in the XY plane) of the openings 56 with different average diameters (D AVE ). The average diameter (D AVE ) of the openings 56 in Fig. 13E is 80 mu m. The average diameter (D AVE ) of the openings 56 in Fig. 13F is 120 占 퐉. The average diameter (D AVE ) of the openings 56 in Fig. 13G is 152 mu m. The average diameter (D AVE ) of the openings 56 in Fig. 13H is 190 mu m. The average diameter (D AVE ) of the openings 56 in Fig. 13I is 220 占 퐉. The average diameter (D AVE ) of the openings 56 in Fig. 13J is 250 占 퐉.

도 13a를 다시 참조하면, 가이딩 트렌치들(58)이 또한 버퍼층(24)과 라미네이팅막(54)에 형성된다. 몇몇의 실시예들에서, 가이딩 트렌치들(58)은 도 14b에서 도시된 바와 같이, 링으로서 형성된다. 따라서, 가이딩 트렌치들(58)은 가이딩 트렌치 링(58)으로서 대안적으로 불리어지지만, 이것들은 또한 개별적인 가이딩 트렌치 스트립들 또는 부분적인 링들로서 형성될 수 있다. 몇몇의 실시예들에서, 도 13a에서 도시된 바와 같이, 가이딩 트렌치들(58) 각각은, 가이딩 트렌치들(58)이 디바이스 다이(34)와 오정렬된 상태에서, 디바이스 다이(34) 전체와 오버랩하는 버퍼층(24)의 중심 부분을 에워싼다. 달리 말하면, 가이딩 트렌치들(58)은 디바이스 다이들(34) 바로 위에 있는 영역들 내로 연장하지 않는다. 가이딩 트렌치들(58)의 바닥들은 몰딩 물질(42)의 최상단면(42A)과 실질적으로 동일한 높이에 있을 수 있고, 이에 따라 가이딩 트렌치들(58)은 버퍼층(24)과 라미네이팅막(54)을 관통한다. 대안적인 실시예들에서, 가이딩 트렌치들(58)은 버퍼층(24)을 관통하지 않으며, 버퍼층(24)의 하위 부분은 가이딩 트렌치들(58) 아래에 남는다. 또다른 대안적인 실시예들에서, 가이딩 트렌치들(58)은 버퍼층(24)을 관통하며, 몰딩 물질(42) 내로 연장한다. Referring again to FIG. 13A, guiding trenches 58 are also formed in the buffer layer 24 and the laminating film 54. In some embodiments, the guiding trenches 58 are formed as a ring, as shown in Fig. 14B. Thus, while the guiding trenches 58 are alternatively referred to as guiding trench rings 58, they can also be formed as individual guiding trench strips or partial rings. 13A, each of the guiding trenches 58 is configured such that, in a state where the guiding trenches 58 are misaligned with the device die 34, the entirety of the device die 34 And the buffer layer 24 overlaps the center portion of the buffer layer 24. In other words, the guiding trenches 58 do not extend into the areas directly above the device dies 34. [ The bottoms of the guiding trenches 58 may be at substantially the same height as the top surface 42A of the molding material 42 so that the guiding trenches 58 are formed by the buffer layer 24 and the laminating film 54 ). In alternative embodiments, the guiding trenches 58 do not penetrate the buffer layer 24 and the bottom portion of the buffer layer 24 remains below the guiding trenches 58. In yet another alternative embodiment, the guiding trenches 58 extend through the buffer layer 24 and into the molding material 42.

다음으로, TIV 패키지(50)가 복수의 TIV 패키지들(60)로 서잉(saw)된다. 도 14a 및 도 14b는 TIV 패키지들(60) 중의 하나의 TIV 패키지의 평면도와 단면도를 각각 도시한다. 몇몇의 실시예들에서, 노출된 TIV들(33)을 보호하기 위해 솔더 페이스트(미도시됨)가 도포된다. 대안적인 실시예들에서, 어떠한 솔더 페이스트도 도포되지 않는다. 도 14b에서 도시된 평면도에서, 가이딩 트렌치 링들(58)은 디바이스 다이(34)를 에워싼다. 가이딩 트렌치 링들(58)의 안쪽 가장자리들이 디바이스 다이(34)의 각각의 가장자리들로부터 오프셋(off-set)되어 있는 것이 도시되지만, 가이딩 트렌치 링들(58)의 안쪽 가장자리들은 또한 각각의 디바이스 다이(34)의 가장자리들에 정렬될 수 있다. 몇몇의 실시예들에서, 각각의 TIV 패키지(60) 내에 단일 가이딩 트렌치 링(58)이 존재한다. 대안적인 실시예들에서, 가이딩 트렌치 링(58)은 두 개 이상 존재한다. 가이딩 트렌치 링들(58)의 폭(W1, W2)은 약 60㎛보다 클 수 있고, 약 60㎛와 약 250㎛ 사이일 수 있다. 가이딩 트렌치 링들(58)의 깊이(D1)(도 14a 참조)는 약 2㎛보다 클 수 있고, 약 2㎛와 약 50㎛ 사이일 수 있다.Next, the TIV package 50 is sawed with the plurality of TIV packages 60. 14A and 14B show a top view and a cross-sectional view of one TIV package of the TIV packages 60, respectively. In some embodiments, a solder paste (not shown) is applied to protect the exposed TIVs 33. In alternative embodiments, no solder paste is applied. In the plan view shown in FIG. 14B, guiding trench rings 58 surround device die 34. Although the inner edges of the guiding trench rings 58 are shown as being off-set from the respective edges of the device die 34, the inner edges of the guiding trench rings 58 may also be formed Lt; RTI ID = 0.0 > 34 < / RTI > In some embodiments, a single guiding trench ring 58 is present in each TIV package 60. In alternate embodiments, there may be more than one guiding trench ring 58. The widths W1 and W2 of the guiding trench rings 58 may be greater than about 60 microns and may be between about 60 microns and about 250 microns. The depth D1 (see FIG. 14A) of the guiding trench rings 58 can be greater than about 2 microns, and can be between about 2 microns and about 50 microns.

도 15는 TIV 패키지(60)로의 최상단 패키지(62)의 접합을 도시하며, 이러한 접합은 솔더 영역들(68)을 통해서 행해질 수 있다. TIV 패키지들(60)은 도 15에서 도시된 바와 같이, 바닥 패키지들로서 역할을 할 수 있기 때문에, 설명 전반에 걸쳐, TIV 패키지들(60)을 또한 바닥 패키지(60)라고도 부른다. 몇몇의 실시예들에서, 최상단 패키지(62)는 패키지 기판(64)에 접합된 디바이스 다이들(66)을 포함한다. 디바이스 다이들(66)은 메모리 다이(들)을 포함할 수 있으며, 이러한 메모리 다이(들)은 예컨대, 정적 랜덤 액세스 메모리(Static Random Access Memory; SRAM) 다이, 동적 랜덤 액세스 메모리(Dynamic Random Access Memory; DRAM) 다이 등일 수 있다. 최상단 패키지(62)의 바닥면과 TIV 패키지(60)의 최상단면은 갭(70)에 의해 서로 이격되며, 최상단 패키지(62)와 TIV 패키지(60)는 스탠드오프(standoff) 거리(S1)를 가질 수 있으며, 이 스탠드오프 거리(S1)는 약 10㎛와 약 100㎛ 사이일 수 있지만, 이 스탠드오프 거리(S1)는 다른 값들을 가질 수 있다.Figure 15 shows the bonding of the top package 62 to the TIV package 60, and such bonding can be done through the solder areas 68. [ TIV packages 60 are also referred to as floor packages 60 throughout the description, since TIV packages 60 can serve as floor packages, as shown in FIG. In some embodiments, the topmost package 62 includes device dies 66 bonded to a package substrate 64. Device die 66 may include memory die (s), such as a static random access memory (SRAM) die, a dynamic random access memory ; DRAM) die or the like. The top surface of the top package 62 and the top surface of the TIV package 60 are spaced from each other by a gap 70 and the top package 62 and the TIV package 60 are spaced apart from each other by a standoff distance S1 And the standoff distance S1 may be between about 10 mu m and about 100 mu m, but the standoff distance S1 may have other values.

도 16을 참조하면, 접합된 최상단 패키지(62)와 TIV 패키지(60)는, 몇몇의 실시예들에서 패키지 기판일 수 있는 다른 패키지 컴포넌트(72)에 추가적으로 접합된다. 대안적인 실시예들에서, 패키지 컴포넌트(72)는 인쇄 회로 기판(Printed Circuit Board; PCB)을 포함한다. 패키지 컴포넌트(72)는 양측면 상에 (금속 패드들 또는 금속 필라들과 같은) 전기적 커넥터들(76)과, 이러한 전기적 커넥터들(76)을 상호연결시키는 금속 트레이스들(78)을 가질 수 있다. 16, bonded top package 62 and TIV package 60 are additionally bonded to another package component 72, which in some embodiments may be a package substrate. In alternate embodiments, the package component 72 includes a Printed Circuit Board (PCB). The package component 72 may have electrical connectors 76 on both sides (such as metal pads or metal pillars) and metal traces 78 interconnecting these electrical connectors 76.

몇몇의 실시예들에서, 갭(70)(도 15 참조)을 채우기 위해 언더필(74)이 디스펜싱(dispense)된다. 언더필(74)은 또한 갭(70)의 주변 부분을 실링(seal)할 수 있는 반면에, 갭(70)의 중심 부분(70')은 언더필(74)에 의해 채워지지 않는다. 언더필(74)의 디스펜싱으로, 언더필(74)은 갭(70)과 가이딩 트렌치들(58)(도 15 참조) 내로 흐른다. 가이딩 트렌치들(58)은 갭(70)의 중심 부분(70')보다 깊기 때문에, 언더필(74)은 갭 중심 부분(70')에서 보다는 가이딩 트렌치들(58)에서 보다 빠르게 흐를 것이다. 따라서, 언더필(74)은 디바이스 다이(34)와 오버랩하는 중심 부분(70') 내로 흐를 수 있기 전에 가이딩 트렌치들(58)을 먼저 채울 것이다. 언더필링 공정을 적절한 시간에 끝냄으로써, 언더필(74)은 가이딩 트렌치들(58) 내에 채워지지만, 갭 중심 부분(70')에는 진입하지 않는다. 따라서, 언더필(74)은 갭 중심 부분(70')을 에워쌀 수는 있지만, 갭 중심 부분(70') 내에는 채워지지 않는다. 따라서, 갭 중심 부분(70')은 에어(air) 또는 진공상태 빈 공간으로 채워진 에어 갭일 수 있는 빈 공간으로 남는다.In some embodiments, the underfill 74 is dispensed to fill the gap 70 (see FIG. 15). The underfill 74 can also seal the peripheral portion of the gap 70 while the central portion 70 'of the gap 70 is not filled by the underfill 74. [ With the dispensing of the underfill 74, the underfill 74 flows into the gap 70 and into the guiding trenches 58 (see FIG. 15). Because the guiding trenches 58 are deeper than the central portion 70 'of the gap 70, the underfill 74 will flow faster at the guiding trenches 58 than at the gap center portion 70'. Thus, the underfill 74 will first fill up the guiding trenches 58 before it can flow into the overlapping central portion 70 'with the device die 34. By terminating the underfilling process at an appropriate time, the underfill 74 is filled in the guiding trenches 58 but does not enter the gap center portion 70 '. Thus, the underfill 74 may surround the gap center portion 70 ', but is not filled in the gap center portion 70'. Thus, the gap center portion 70 'remains as an empty space which can be an air gap filled with air or vacuum void spaces.

실시예들 및 이들의 이점이 자세히 설명되어 있지만, 다른 변경, 대체 및 변형이 첨부된 청구범위에 의해 정의된 실시예들의 범위 및 사상에 벗어남이 본 발명 내에서 행해질 수 있음을 이해하여야 한다. 또한, 본 발명의 범위는 명세서 내에 설명된 프로세스, 머신, 제조 및 물질의 조성, 수단, 방법 및 단계들의 특정 실시예들로 제한되지 않는 것으로 의도된다. 본 발명분야의 당업자라면 여기서 설명된 대응하는 실시예들과 실질적으로 동일한 기능을 수행하거나 또는 이와 실질적으로 동일한 결과를 달성하는, 현존하거나 후에 개발될 물질, 수단, 방법, 또는 단계의 공정, 머신, 제조, 조성이 본 발명개시에 따라 이용될 수 있다는 것을 본 발명개시로부터 손쉽게 알 것이다. 따라서, 첨부된 청구항들은 이와 같은 물질, 수단, 방법, 또는 단계의 공정, 머신, 제조, 조성을 청구항의 범위내에 포함하는 것으로 한다. 또한, 각각의 청구항은 개별적인 실시예를 구성하며, 다양한 청구항들 및 실시예들의 조합은 본 발명개시의 범위내에 있다.While the embodiments and their advantages have been described in detail, it should be understood that other changes, substitutions and alterations can be made herein without departing from the scope and spirit of the embodiments as defined by the appended claims. It is also intended that the scope of the invention is not limited to the specific embodiments of the process, machine, manufacture and composition of matter, means, methods and steps described in the specification. Means, methods, or steps of a material, means, method, or step to be developed that will perform substantially the same function or achieve substantially the same result as those of the corresponding embodiments described herein, It will be readily appreciated from the disclosure of the present invention that manufacture and composition can be used according to the disclosure of the present invention. Accordingly, the appended claims are intended to cover within the scope of the claims the process, machine, manufacture, composition of such material, means, method, or step. In addition, each claim constitutes an individual embodiment, and the various claims and combinations of embodiments are within the scope of the disclosure of the present invention.

Claims (10)

패키지 구조물에 있어서,
제1 패키지
를 포함하고, 상기 제1 패키지는,
몰딩 화합물;
상기 몰딩 화합물을 관통하는 쓰루 비아;
상기 몰딩 화합물 내에서 몰딩된 디바이스 다이; 및
상기 몰딩 화합물과 접촉하면서 상기 몰딩 화합물 상에 있는 버퍼층
을 포함하고, 개구가 상기 버퍼층을 관통하여 상기 쓰루 비아에 이르고, 상기 버퍼층은 상기 몰딩 화합물과 상기 버퍼층 사이의 계면에 평행한 평면에서 상기 개구의 둘레 주변에 리플(ripple)들을 가지며, 상기 리플들의 피크(peak)와 골(valley)은 모두 상기 몰딩 화합물과 상기 버퍼층 사이의 상기 계면에 평행한 상기 평면에 배치된 것인, 패키지 구조물.In the package structure,
The first package
Wherein the first package comprises:
Molding compound;
Throughbia penetrating the molding compound;
A device die molded within the molding compound; And
Contacting the molding compound with a buffer layer < RTI ID = 0.0 >
Wherein the openings pass through the buffer layer to the through vias and the buffer layer has ripples around a periphery of the opening in a plane parallel to the interface between the molding compound and the buffer layer, Wherein both the peak and the valley are disposed in the plane parallel to the interface between the molding compound and the buffer layer. 제1항에 있어서, 상기 제1 패키지는 상기 버퍼층 상의 라미네이팅막을 더 포함하고, 상기 버퍼층은 상기 라미네이팅막과 상기 몰딩 화합물 사이에 배치되며, 상기 개구는 상기 라미네이팅막을 관통하는 것인, 패키지 구조물.The package structure of claim 1, wherein the first package further comprises a laminating film on the buffer layer, wherein the buffer layer is disposed between the laminating film and the molding compound, the opening penetrating the laminating film. 제1항에 있어서, 상기 리플들은 상기 개구의 둘레 주변에서 주기적으로 구성되어 있는 것인, 패키지 구조물.The package structure of claim 1, wherein the ripples are periodically configured around a periphery of the opening. 제1항에 있어서, 상기 개구를 관통하는 전기적 커넥터에 의해 상기 제1 패키지에 접합된 제2 패키지를 더 포함하는, 패키지 구조물.The package structure of claim 1, further comprising a second package bonded to the first package by an electrical connector passing through the opening. 제1항에 있어서, 상기 제1 패키지는 상기 버퍼층의 표면에서부터 상기 버퍼층 내로 연장하는 가이딩 트렌치를 더 포함하며, 상기 가이딩 트렌치는 상기 디바이스 다이와 오정렬된 것인, 패키지 구조물.2. The package structure of claim 1, wherein the first package further comprises a guiding trench extending from the surface of the buffer layer into the buffer layer, wherein the guiding trench is misaligned with the device die. 제5항에 있어서, 상기 가이딩 트렌치는 링(ring)을 형성하고, 상기 가이딩 트렌치는 상기 패키지 구조물을 상부에서 아래로 바라보았을 때 상기 버퍼층의 중심 부분을 완전히 에워싸며, 상기 버퍼층의 상기 중심 부분은 상기 디바이스 다이 전체와 오버랩하는 것인, 패키지 구조물.6. The method of claim 5, wherein the guiding trench forms a ring, the guiding trench completely surrounding the central portion of the buffer layer when viewed from top to bottom of the package structure, Portion overlaps with the entire device die. 패키지 구조물에 있어서,
제1 패키지로서, 상기 제1 패키지는,
평면 최상단면과 평면 바닥면을 포함한 몰딩 화합물;
상기 몰딩 화합물에 의해 횡측으로 캡슐화된 디바이스 다이;
상기 몰딩 화합물을 관통하는 쓰루 비아; 및
상기 몰딩 화합물의 상기 평면 최상단면과 접촉하면서 상기 평면 최상단면 위에 있는 평면 유전체층
을 포함하고, 개구가 상기 평면 유전체층을 관통하여 상기 쓰루 비아에 이르며, 상기 개구를 둘러싸는 상기 평면 유전체층 내에 리플들이 있고, 상기 평면 유전체층의 최상부면은 상기 패키지 구조물의 평면도 상에서 상기 개구의 둘레 주변의 물결 형상(wavy shape)을 포함하는 것인, 상기 제1 패키지; 및
상기 제1 패키지에 접합된 제2 패키지
를 포함하고, 외부 전기적 커넥터가 상기 제1 패키지를 상기 제2 패키지에 전기적으로 결합시키며, 상기 외부 전기적 커넥터는 상기 개구 내에 적어도 부분적으로 배치된 것인, 패키지 구조물.In the package structure,
A first package, the first package comprising:
A molding compound including a planar top section and a planar bottom surface;
A device die transversely encapsulated by the molding compound;
Throughbia penetrating the molding compound; And
A planar top layer of the molding compound,
Wherein the openings extend through the planar dielectric layer to the through vias and there are ripples in the planar dielectric layer surrounding the openings and wherein a top surface of the planar dielectric layer is located on a perimeter of the opening in the top view of the package structure The first package including a wavy shape; And
A second package bonded to the first package;
Wherein an external electrical connector electrically couples the first package to the second package, wherein the external electrical connector is at least partially disposed within the opening. 제7항에 있어서, 상기 제1 패키지와 상기 제2 패키지 사이에 적어도 부분적으로 배치된 언더필(underfill)을 더 포함하는, 패키지 구조물.8. The package structure of claim 7, further comprising an underfill disposed at least partially between the first package and the second package. 패키지 형성 방법에 있어서,
패키지를 형성하는 단계
를 포함하고, 상기 패키지를 형성하는 단계는,
디바이스 다이, 몰딩 화합물, 및 쓰루 비아를 포함하는 복합 구조물을 형성하는 단계로서, 상기 몰딩 화합물은 상기 몰딩 화합물의 제1 표면과 상기 몰딩 화합물의 제2 표면 사이에 상기 디바이스 다이를 적어도 횡측으로 캡슐화하며, 상기 쓰루 비아는 상기 몰딩 화합물 내에 있고 상기 몰딩 화합물의 상기 제1 표면에서부터 상기 몰딩 화합물의 상기 제2 표면까지 연장하는 것인, 상기 복합 구조물을 형성하는 단계;
상기 몰딩 화합물의 상기 제1 표면 상에 버퍼층 - 상기 버퍼층은 절연 재료를 포함함 - 을 형성하는 단계; 및
레이저 드릴링을 이용하여 상기 버퍼층을 관통하여 상기 쓰루 비아에 이르는 개구를 형성하는 단계
를 포함하며, 상기 레이저 드릴링은 상기 개구 주변에서 상기 버퍼층 내에 리플들을 형성하는 것인, 패키지 형성 방법.In the package forming method,
Step of forming package
Wherein forming the package comprises:
Forming a composite structure comprising a device die, a molding compound, and a throughbia, the molding compound encapsulating the device die at least transversely between a first surface of the molding compound and a second surface of the molding compound Wherein said throughbia is in said molding compound and extends from said first surface of said molding compound to said second surface of said molding compound;
Forming a buffer layer on the first surface of the molding compound, the buffer layer comprising an insulating material; And
Forming an opening through the buffer layer using laser drilling to the through vias
Wherein the laser drilling forms ripples in the buffer layer around the aperture. 제9항에 있어서, 상기 레이저 드릴링은 상기 버퍼층의 노출면의 법선에 대한 입사각 θ으로 레이저를 이용하는 것을 포함하며, 상기 레이저는 광 파장 λ를 갖고, 상기 리플들은
Figure 112016032749938-pat00002
에 의해 정의된 피크간 거리 Δ를 갖는 것인, 패키지 형성 방법.10. The method of claim 9, wherein the laser drilling comprises using a laser at an angle of incidence &thetas; with respect to the normal of the exposed surface of the buffer layer, the laser having an optical wavelength,
Figure 112016032749938-pat00002
Lt; RTI ID = 0.0 > A < / RTI >
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