KR101680282B1 - Radio Frequency Integrated Circuit - Google Patents

Radio Frequency Integrated Circuit Download PDF

Info

Publication number
KR101680282B1
KR101680282B1 KR1020150034543A KR20150034543A KR101680282B1 KR 101680282 B1 KR101680282 B1 KR 101680282B1 KR 1020150034543 A KR1020150034543 A KR 1020150034543A KR 20150034543 A KR20150034543 A KR 20150034543A KR 101680282 B1 KR101680282 B1 KR 101680282B1
Authority
KR
South Korea
Prior art keywords
conductive layer
layer
region
capacitor
conductive
Prior art date
Application number
KR1020150034543A
Other languages
Korean (ko)
Other versions
KR20160109682A (en
Inventor
김남영
왕종
이양
Original Assignee
광운대학교 산학협력단
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 광운대학교 산학협력단 filed Critical 광운대학교 산학협력단
Priority to KR1020150034543A priority Critical patent/KR101680282B1/en
Publication of KR20160109682A publication Critical patent/KR20160109682A/en
Application granted granted Critical
Publication of KR101680282B1 publication Critical patent/KR101680282B1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0288—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using passive elements as protective elements, e.g. resistors, capacitors, inductors, spark-gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/10—Inductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/20—Resistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors

Abstract

An RF integrated circuit includes: a semiconductor substrate in which a resistance region, a capacitor region, and an inductance region are defined; A conductive pattern disposed on the semiconductor substrate and including a first conductive layer and a second conductive layer; A surface mount resistor comprising a first portion and a second portion of the first conductive layer spaced apart from each other in the resistance region and a layer of a resistive material disposed between the first portion and the second portion; A third portion of the first conductive layer and a first portion of the second conductive layer functioning as both side electrodes in the capacitor region and a second portion of the first portion of the first conductive layer, A capacitor comprising a capacitor dielectric layer disposed between the portions; An inductor comprising a fourth portion of the first conductive layer and a second portion of the second conductive layer in electrical connection with the fourth portion of the first conductive layer in the inductance region; And a passivation layer covering the upper surface of the second conductive layer, the passivation layer being made of an SU-8 photoresist material.

Description

An RF integrated circuit (Radio Frequency Integrated Circuit)

The present invention relates to an RF integrated circuit, and more particularly, to an RF integrated circuit including an inductor of an air bridge structure.

With the development of wireless communications, the importance of RF devices such as filters implemented with passive components is increasing. Accordingly, studies are being conducted to realize an RF device as an integrated circuit. However, when the RF device is implemented as an integrated circuit, it is difficult to realize the required performance and there may be an interference problem between the RF integrated circuit and the peripheral circuit.

SUMMARY OF THE INVENTION It is an object of the present invention to provide an RF integrated circuit which can achieve low cost and high efficiency and is highly reliable in order to solve the above problems.

According to an aspect of the present invention, there is provided an RF integrated circuit including: a semiconductor substrate having a resistance region, a capacitor region, and an inductance region defined therein; A conductive pattern disposed on the semiconductor substrate and including a first conductive layer and a second conductive layer; A surface mount resistor comprising a first portion and a second portion of the first conductive layer spaced apart from each other in the resistance region and a layer of a resistive material disposed between the first portion and the second portion; A third portion of the first conductive layer and a first portion of the second conductive layer functioning as both side electrodes in the capacitor region and a second portion of the first portion of the first conductive layer, A capacitor comprising a capacitor dielectric layer disposed between the portions; An inductor comprising a fourth portion of the first conductive layer and a second portion of the second conductive layer in electrical connection with the fourth portion of the first conductive layer in the inductance region; And a passivation layer covering the upper surface of the second conductive layer, the passivation layer being made of an SU-8 photoresist material.

In exemplary embodiments, the surface mount resistor, the capacitor, and the inductor may constitute a passive RF device.

In exemplary embodiments, the semiconductor device may further include an element isolation layer formed between the semiconductor substrate and the conductive pattern, the element isolation layer including an inorganic insulating material.

In exemplary embodiments, the inductance region is electrically connected to the second portion of the second conductive layer, and the fifth portion of the first conductive layer spaced from the fourth portion of the first conductive layer, And the second portion of the second conductive layer may extend from the top of the fourth portion of the first conductive layer to the top of the fifth portion with an air bridge structure.

In the exemplary embodiments, the second portion of the second conductive layer is vertically overlapped with the fifth portion of the first conductive layer, and the second portion of the second conductive layer contacts the first conductive Layer may be spaced apart from the fifth portion of the layer.

In exemplary embodiments, the first conductive layer may have a planar surface morphology.

In exemplary embodiments, the first conductive layer may have a root mean square roughness (RMS) roughness of 30 nm or less.

In exemplary embodiments, the device may further include an active RF device including a transistor disposed on the semiconductor substrate.

The RF integrated circuit according to the present invention can have improved reliability as it includes a passivation layer comprising an SU-8 photoresist material. As the RF integrated circuit includes the first conductive layer having excellent flatness, the breakdown voltage of the capacitor is increased and the precision of the surface mounting resistance including the first conductive layer can be improved. Thus, the RF integrated circuit can have excellent RF characteristics.

1 is an equivalent circuit diagram of an RF integrated circuit according to exemplary embodiments.
2A is a perspective view showing an RF integrated circuit according to exemplary embodiments, and FIG. 2B is an enlarged view of a portion 2B in FIG. 2A.
3 is a cross-sectional view of portions corresponding to surface mount resistors, capacitors and inductors of FIG. 2A.
4A-4C are planar layouts of surface mount resistors, capacitors, and inductors of an RF integrated circuit according to exemplary embodiments.
5A to 5H are cross-sectional views illustrating a method of manufacturing an RF integrated circuit according to exemplary embodiments.
FIG. 6 is focused ion beam (FIB) images representing the parts of the RF integrated circuit.
FIGS. 7A and 7B are AFM (atomic force microscopy) images showing the surface morphology of the first conductive layer according to Experimental Examples and Comparative Examples.
8 is a graph showing the Q-factor of the inductor according to the experimental example and the comparative example.
9 is a graph showing resistance values of surface mount resistances and breakdown voltages of capacitors according to Experimental Examples and Comparative Examples.
10 is a graph showing a reliability test result of an RF integrated circuit according to an experimental example.

In order to fully understand the structure and effects of the present invention, preferred embodiments of the present invention will be described with reference to the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. It should be understood, however, that the description of the embodiments is provided to enable the disclosure of the invention to be complete, and will fully convey the scope of the invention to those skilled in the art. In the accompanying drawings, the components are enlarged for the sake of convenience of explanation, and the proportions of the components can be exaggerated or reduced.

It is to be understood that when an element is referred to as being "on" or "tangent" to another element, it is to be understood that other elements may directly contact or be connected to the image, something to do. On the other hand, when an element is described as being "directly on" or "directly adjacent" another element, it can be understood that there is no other element in between. Other expressions that describe the relationship between components, for example, "between" and "directly between"

The terms first, second, etc. may be used to describe various elements, but the elements should not be limited by the terms. The terms may only be used for the purpose of distinguishing one element from another. For example, without departing from the scope of the present invention, the first component may be referred to as a second component, and similarly, the second component may also be referred to as a first component.

The singular forms "a", "an" and "the" include plural referents unless the context clearly dictates otherwise. The word "comprising" or "having ", when used in this specification, is intended to specify the presence of stated features, integers, steps, operations, elements, A step, an operation, an element, a part, or a combination thereof.

The terms used in the embodiments of the present invention may be construed as commonly known to those skilled in the art unless otherwise defined.

Hereinafter, the present invention will be described in detail with reference to the preferred embodiments of the present invention with reference to the accompanying drawings.

1 is an equivalent circuit diagram of an RF integrated circuit 100 according to exemplary embodiments.

Referring to FIG. 1, the RF integrated circuit 100 may be a lumped-element Wilkinson power divider. A resistor R is connected between the two output ports OUT1 and OUT2 and an inductor L may be disposed between the input port IN and the output ports OUT1 and OUT2. Capacitor C can be implemented in two types: 2A) may be connected in series between the inductor L and the ground terminal (GR in Fig. 2A), and two second capacitors (C_2 in Fig. 2A) may be connected in series between the inductor L and the ground terminal And the ground terminal GR in parallel with each other.

The inductor L and the capacitor C can be determined as shown in the following equations (1) and (2).

Figure 112015024368407-pat00001
-(One)

Figure 112015024368407-pat00002
-(2)

Here,? Is the driving frequency of the RF integrated circuit 100, and Z 0 is the characteristic impedance value. For example, L = 5.65 nH and C = 0.78 pF when the driving frequency is 2.4 GHz and the characteristic impedance Z 0 is 50 Ω.

2A is a perspective view showing an RF integrated circuit 100 according to exemplary embodiments, and FIG. 2B is an enlarged view of a portion 2B in FIG. 2A. 3 is a cross-sectional view of portions corresponding to the surface mount resistor R, the capacitor C and the inductor L of FIG.

2A to 3, the RF integrated circuit 100 includes a semiconductor substrate 110, a surface mount resistor R formed on the semiconductor substrate 110, a passive RF circuit including a capacitor C and an inductor L, (Radio Frequency) device.

A surface mount resistor R may be formed in the resistance region R-R. Specifically, the first portion 132-Ra and the second portion 132-Rb of the first conductive layer 132 function as both terminals with the resistance material layer 210 therebetween, (R) can be made. The resistance terminal insulating film 222 can be made such that the both terminals of the surface mount resistor R, that is, the first portion 132-Ra and the second portion 132-Rb of the first conductive layer 132 are insulated from each other . The resistance terminal insulating film 222 covers the exposed upper surfaces of the opposing sidewalls of the first portion 132-Ra and the second portion 132-Rb of the first conductive layer 132 and the resistance material layer 210 . A portion of the passivation layer 226 formed in the resistance region RR is electrically connected to the first portion 132-Ra and the second portion 132-Rb of the first conductive layer 132, The portions of layer 134 may be insulated from each other. A portion of the passivation layer 226 formed in the resistance region RR is electrically connected to the first portion 132-Ra and the second portion 132-Rb of the first conductive layer 132, To cover the exposed opposite side walls of the portions of the layer 134 and the exposed upper surface of the resistance terminal insulating layer 222. [

A capacitor C may be formed in the capacitor region C-R. Specifically, a portion of the second dielectric material pattern 224 becomes the capacitor dielectric layer 224C, and the third portion 132-Ca and the fourth portion 132-Cb of the first conductive layer 132 are electrically connected to the electrodes So that the capacitor C can be formed. Thus, the capacitor C may be a surface mount capacitor.

One electrode of the capacitor C is electrically connected to the third portion 132-Ca of the first conductive layer 132 and the second conductive layer 132-Ca electrically connected to the third portion 132-Ca of the first conductive layer 132. [ And the other electrode may correspond to the portion of the second conductive layer 134 and the fourth portion 132-Cb of the first conductive layer 132 and the first portion 134-C of the second conductive layer 134 . The first portion 134-C of the second conductive layer 134 constituting the other electrode of the capacitor C is connected to the third portion 132-Ca of the first conductive layer 132 and the fourth portion 132- Cb) extending over the first air bridge space (AS2C) which is a space defined by the second dielectric material pattern (224C) and the first portion (134C) of the second conductive layer (134) -bridge structure. The first portion 134C of the second conductive layer 134 constituting the other electrode of the capacitor C is electrically connected to the first conductive layer 132 from the upper side of the third portion 132- To an upper side of the fourth portion 132-Cb of the first portion 132a.

The portion of the passivation layer 226 formed in the capacitor region CR is formed by the third portion 132-Ca of the first conductive layer 132, the first portion 134C of the second conductive layer 134, May be formed conformally on the sidewalls of the capacitor dielectric layer 224C interposed in the capacitor dielectric layer 224C.

An inductor L may be formed in the inductance region L-R. The inductor L includes a second conductive layer 134 electrically connected to the fifth portion 132-L1 of the first conductive layer 132 and the fifth portion 132-L1 of the first conductive layer 132, And a second portion 134L of the second portion 134L. The inductor L may also be a conductive line forming a coil through the sixth portion 132-L2 of the first conductive layer 132. [

The second portion 134L of the second conductive layer 134 is between the fifth portion 132-L1 of the first conductive layer 132 and the sixth portion 134-L2 of the first conductive layer 134 May have an air bridge structure extending over the second air bridge space AS2L which is a space defined by the second dielectric material pattern 224L and the second portion 134L of the second conductive layer 134. [ The second portion 134L of the second conductive layer 134 and the sixth portion 134-L2 of the first conductive layer 134 located on the second air bridge space AS2L are spaced apart from each other by a first distance S1 , And they can be vertically overlapped. In exemplary embodiments, the first spacing S1 may be from about 1 to about 5 占 퐉, but is not limited thereto.

A portion of the passivation layer 226 formed in the inductance region L-R may conformally cover the upper surface of the second portion 134L of the second conductive layer 134. [ The passivation layer 226 protects the surface mount resistance R, the capacitor C and the inductor L from moisture or unwanted oxidation reactions or from the external impact of mechanical shock to the surface mount resistance R, the capacitor C ) And the inductor (L). In the exemplary embodiments, the passivation layer 226 may comprise an SU-8 photoresist material. SU-8 photoresist materials can have excellent adhesion with various lower layer materials such as silicon, gallium arsenide, indium phosphide, and metal materials, and can also have excellent insulating properties. Moreover, the process of fabricating the passivation layer 226 including the SU-8 photoresist material is easy and the physical and chemical damage to the substrate 110 or underlying components in the manufacturing process of the passivation layer 226 The electrical performance of the RF integrated circuit 100 can be improved.

Although not shown, a peripheral circuit that receives a signal from a passive RF device including a surface mount resistor R, a capacitor C, and an inductor L may be implemented on the semiconductor substrate 110.

The planar layout of the RF integrated circuit 100 will be described below.

Figs. 4A to 4C are plan layouts of the surface mount resistor R, the capacitor C and the inductor L of the RF integrated circuit 100 according to the exemplary embodiments. Fig.

4A, the surface-mount resistor R has a first portion 132-Ra and a second portion 132-Rb of the first conductive layer sandwiching the layer of resistive material 210 between both terminals Function. The surface mount resistance R is determined by the width W1 of the resistive material layer 210 and the length L1 between the first portion 132-Ra and the second portion 132-Rb of the first conductive layer, The resistance value can be determined by the resistivity of the layer 210.

4B, the capacitor C may have a capacitor dielectric layer 224-C disposed between the third portion 132-Ca of the first conductive layer and the first portion 134C of the second conductive layer . The capacitor C has a width W2 and a length L2 of the capacitor dielectric layer 224-C disposed between the third portion 132-Ca of the first conductive layer and the first portion 134C of the second conductive layer. And the thickness and permittivity of the capacitor dielectric layer 224-C.

4C, the inductor L includes a second portion 134L of the second conductive layer, a fifth portion 132-L1 of the first conductive layer and a fifth portion 132- And the sixth portion 132-L2 of the first conductive layer extending from the first conductive layer -L1 may be formed in a coil shape. The inductance value of the inductor L can be determined by the width W3 of the second portion 134L of the second conductive layer and the interval S2 between the second portion 134L of the adjacent second conductive layer.

In exemplary embodiments, the inductor L may have a width W3 of about 5 to 30 microns and may be disposed such that the second spacing S2 from the adjacent disposed metal lines is about 5 to 30 microns have. Also, as described above, the first spacing S2, which is the vertical spacing distance between the sixth portion 132-L2 of the first conductive layer and the second portion 134L of the second conductive layer, is about 1 to 5 [ Lt; / RTI > However, the width W3 of the inductor L, the second gap S2, and the first gap S1 are not limited thereto.

For example, in the structure shown in Fig. 2A, the inductor L may be spirally arranged to have a width W3 of about 15 [mu] m and be spaced by an interval S2 of about 15 [mu] m from adjacent metal lines, , The first spacing S1 between the sixth portion 132-L2 of the first conductive layer and the second portion 134L of the second conductive layer may be 2 [mu] m. This configuration allows a good Q-factor of about 28.5 at a driving frequency of 2.4 GHz. The Q-index of the RF integrated circuit 100 will be described later in detail with reference to FIG.

According to the RF integrated circuit 100 described with reference to Figs. 2A to 4C, the surface mount resistance R may be composed of a single layer of the first conductive layer 132 without a seed metal layer. Thus, the etching process of the seed metal layer and the subsequent cleaning processes can be omitted, so that the mechanical and chemical damage to the surface mounting resistance R can be minimized. Therefore, the precision of the resistance value of the surface mount resistor R can be improved.

The capacitor C also includes portions 132-Ca and 132-Cb of the first conductive layer 132 and the first conductive layer 132 is formed by an electron beam evaporation process to have a smooth surface morphology . Thus, the capacitor dielectric layer 224C formed on the first conductive layer 132 may have excellent coverage characteristics, so that the capacitor C may have a high breakdown voltage.

In addition, a passivation layer 226 comprising an SU-8 photoresist material is formed on the surface mount resistor R, the capacitor C, and the inductor L. [ The passivation layer 226 can be fabricated without physical or chemical damage to the underlying components while having good insulating properties and protecting underlying components from moisture or unwanted oxidation reactions. Therefore, the electrical performance and reliability of the RF integrated circuit 100 can be improved.

5A to 5H are cross-sectional views illustrating a method of manufacturing the RF integrated circuit 100 according to exemplary embodiments. 5A to 5H illustrate sections of portions corresponding to areas where the surface mount resistor R, the inductor L, and the capacitor C are formed in FIG. 2A in accordance with the process order.

Referring to FIG. 5A, a substrate 110 is defined in which a resistance region R-R, a capacitor region C-R, and an inductance region L-R are defined. The substrate 110 may be a semiconductor substrate such as gallium arsenide (GaAs), indium arsenide (InAs), indium phosphide (InP), or a semiconductor substrate such as silicon (Si), germanium have. For example, when the substrate 110 includes a compound semiconductor such as GaAs, parasitic capacitance or parasitic inductance can be prevented as compared with the case where a conductive substrate is used.

The device isolation layer 120 may be formed on the substrate 110. The device isolation layer 120 may be formed to have a thickness of several nm to several tens nm using, for example, silicon oxide or silicon nitride. The device isolation layer 120 may be formed by a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, a sputtering process, or the like. For example, a device isolation layer 120 having a thickness of about 200 nm can be formed by a plasma enhanced CVD process using silicon nitride. The device isolation layer 120 provides a flat upper surface for components to be formed on the substrate 110 even if the substrate 110 has a defect on the surface of the substrate 110 or the roughness of the substrate 110 is relatively large It can act as an intermediate layer that can be formed.

A resistive material layer 210 may be formed on the element isolation layer 120 on the resistance region R-R. After forming a mask pattern covering the upper surface of the semiconductor substrate 110, exposing the position where the resistive material layer 210 is formed, a resistive material covers the substrate 110 to form the resistive material layer 210 A lift-off method of removing the mask pattern can be used. Alternatively, a resist material covering the upper surface of the substrate 110 may be formed, and then a mask pattern may be formed to cover a position where the resistive material layer 210 is formed. Then, the exposed portion of the resistive material may be removed by an etching process, (210) can be formed.

Resistive material layer 210 is, for example, nickel-chromium (NiCr), tantalum nitride (TaN), oxide ruthenium (RuO 2), lead oxide (PbO), Lucero nyumsan bismuth (Bi 2 Ru 2 O 7) iridium Bismuth (Bi 2 Ir 2 O 7 ), or the like. The resistance material layer 210 may be formed to have a thickness of, for example, several tens to several hundreds of nanometers and a length of several to several tens of micrometers. The resistance value of the resistance formed in the resistance material layer 210 can be determined in consideration of the sheet resistance, the width, and the length of the resistance material layer 210. [ Illustratively, when the resistive material layer 210 is formed to a thickness of 75 nm and has a sheet resistance of 250 OMEGA / & squ &, the length of the resistive material layer 210 is formed in the range of 10 mu m to 25 mu m, When the width of the layer 210 is adjusted in the range of several 占 퐉 to several tens 占 퐉, a resistance having a resistance value of 50 Ω to 500 Ω can be formed. 5A, the width of the resistive material layer 210 in the horizontal direction may correspond to the length of the resistive material layer 210. In FIG. The resistive material layer 210 may be formed, for example, by an e-beam evaporation process.

Referring to FIG. 5B, a first mask 192 is formed on the upper surface of the semiconductor substrate 110 on which the device isolation layer 120 is formed. The first mask 192 may expose portions of the resistive material layer 210 except for at least a portion of the top surface of the resistive material layer 210 in the resistive region R-R. The first mask 192 may cover the entire upper surface of the resistance material layer 210 of the resistance region R-R and may be formed to expose all of the isolation layers 120 on the side surfaces of the resistance material layer 210. However, considering the process margin, as shown in FIG. 5B, the first mask 192 is formed so that a portion adjacent to both ends of the upper surface of the resistance material layer 210 of the resistance region RR (both ends in the left and right direction in FIG. 4B) And may be formed to cover an intermediate portion of the upper surface of the resistive material layer 210.

The first mask 192 may be formed to partially cover the middle portion of the capacitor region C-R and expose a portion adjacent to both ends of the capacitor region C-R. The first mask 192 may be formed to cover a portion of the inductance region L-R and to expose the remaining portion. The inductance region L-R exposed by the first mask 192 may be formed with an inductor, that is, a conductive line for constituting the coil.

In addition, the first mask 192 may be formed so as to cover the region where the first conductive layer 132 (FIG. 6) to be formed in the subsequent process is not formed. The first mask 192 may be, for example, a photoresist pattern.

Referring to FIG. 5C, a first conductive layer 132 is formed on the device isolation layer 120 exposed by the first mask 192. The first conductive layer 132 may be conformally formed to a predetermined thickness.

In the exemplary embodiments, the process for forming the first conductive layer 132 may be an electron beam evaporation process. In this case, portions (not shown) of the first conductive layer formed on the first mask 192 may be removed together by a lift-off method when removing the first mask 192. The first conductive layer 132 may be formed using, for example, copper, nickel or gold, or a combination thereof.

In an exemplary process using an electron beam evaporation process to form the first conductive layer 132, a source metal (not shown) wiping step is performed prior to performing the forming step of the first conductive layer 132, A pre-melting step of the source metal, and an evaporation rate adjusting step of the source metal may be further performed. Accordingly, the flatness of the first conductive layer 132 can be improved. In the exemplary embodiments, the first conductive layer 132 may have a root mean square roughness of about 30 nm or less. The flatness improving characteristics of the first conductive layer 132 formed by the above process will be described later in detail with reference to FIGS. 7A and 7B.

Alternatively, an adhesive metal layer (not shown) having a predetermined thickness may be further formed using titanium, tantalum, and / or gold by an electron beam evaporation process before forming the first conductive layer 132.

In the resistance region R-R, at least a pair of first conductive layer 132 portions 132-Ra and 132-Rb that are in contact with both sides of the resistance material layer 210 and are spaced apart from each other may be formed. The portions 132-Ra and 132-Rb of the first conductive layer 132 formed in the resistance region RR are respectively connected to the first portion 132-Ra of the first conductive layer 132 and the first conductive layer 132- (132-Rb). The first portion 132-Ra and the second portion 132-Rb of the first conductive layer 132 may be spaced apart from each other across the portion of the first mask 192 formed in the resistance region RR .

At least a pair of first conductive layer 132 portions 132-Ca and 132-Cb spaced apart from each other may be formed in the capacitor region C-R. The portions 132-Ca and 132-Cb of the first conductive layer 132 formed in the capacitor region CR are electrically connected to the third portion 132-Ca of the first conductive layer 132 and the first conductive layer 132- (132-Cb). The third portion 132-Ca and the fourth portion 132-Cb of the first conductive layer 132 may be spaced apart from each other across the portion of the first mask 192 formed in the capacitor region CR .

Portions 132-L1 and 132L2 of the first conductive layer 132 may be formed in the inductance region L-R to form conductive lines for forming coils constituting the inductor. The portions 132-L1 and 132-L2 of the first conductive layer 132 formed in the inductance region LR are shown as being spaced apart from each other, but they may extend to other portions to form coils, have. However, a portion 132-L2 of the portion of the first conductive layer 132 formed in the inductance region L-R may be a portion electrically connected to the second conductive layer, which will be described later.

After forming the first conductive layer 132, the first mask 192 may be removed.

Referring to FIG. 5D, a dielectric material layer 220 is formed on a substrate 110 on which a first conductive layer 132 is formed. The dielectric material layer 220 may be formed to have a predetermined thickness so as to cover the inner wall of the first conductive layer 132 without covering the space between the first conductive layers 132.

A portion of the dielectric material layer 220 formed in the resistance region R-R is formed to cover the resistance material layer 210 exposed by the first conductive layer 132. Specifically, a portion of the dielectric material layer 220 formed in the resistance region RR includes a first portion 132-Ra of the first conductive layer 132 spaced apart from each other in contact with the resistance material layer 210, Is formed to fill a space defined by the resistive material layer 210 between portions 132-Rb.

The dielectric material layer 220 may be made of a material having a larger dielectric constant than silicon oxide. The dielectric material layer 220 may be formed of a material such as, for example, silicon nitride (SiN x ), barium titanium oxide (BaTiO), hafnium oxide (HfO), hafnium silicate (HfSiO), hafnium oxide nitride (HfON), hafnium silicon oxynitride ), Lanthanum oxide (LaO), lanthanum aluminum oxide (LaAlO), zirconium oxide (ZrO), zirconium silicate (ZrSiO), zirconium oxide nitride (ZrON), zirconium silicon oxynitride (ZrSiON), tantalum oxide (Ta), barium strontium titanium oxide (BaSrTiO), strontium titanium oxide (SrTiO), yttrium oxide (YO), aluminum oxide (AlO), or lead scandium tantalum oxide (PbScTaO) .

After forming the dielectric material layer 220, a second mask 194 is formed in a portion of the resistance region R-R, the capacitor region C-R, and the inductance region L-R. The second mask 194 may be, for example, a photoresist pattern.

The portion of the second mask 194 that is formed in the resistance region RR is formed between the first portion 132-Ra and the second portion 132-Rb of the first conductive layer 132, And may be formed to fill a space defined by the material layer 220.

A portion of the second mask 194 formed in the capacitor region CR is divided into a third portion 132-Ca and a fourth portion 132- Cb may be formed to fill a space defined by the dielectric material layer 220. The portion of the second mask 194 formed in the capacitor region CR may include at least one of the portions 132-Ca and 132-Cb of the first conductive layer 132 formed in the capacitor region CR, , It may be formed so as to cover a part of the upper portion of the third portion 132-Ca. A portion of the second mask 194 covering a portion of the third portion 132-Ca of the first conductive layer 132 formed in the capacitor region CR among the portions formed in the capacitor region CR is subjected to a subsequent process A capacitor can be formed.

A portion of the second mask 194 formed in the inductance region L-R may be formed to cover a portion of the dielectric material layer 220 for covering the conductive line for forming the coil constituting the inductance. For example, the portion of the second mask 194 formed in the inductance region LR is formed so that both ends of the conductive line for forming the coils constituting the inductor are exposed, and the intermediate portion where the conductive line is extended is formed .

5D and 5E, the second mask 194 is used as an etch mask to remove portions of the dielectric material layer 220 exposed by the second mask 194 to form dielectric material patterns 222 and 224, . For example, the process for removing portions of the exposed dielectric material layer 220 may be a reactive ion etching process.

The dielectric material patterns 222 and 224 include a first dielectric material pattern 222 formed in the resistance region RR and a second dielectric material pattern 224 formed in the capacitor region CR and the inductance region LR can do.

The first dielectric material pattern 222 may isolate between the terminals of the resistor to be formed through a subsequent process and may be referred to as a resistance terminal insulating film 222. [ The resistance terminal insulating film 222 has a first portion 132-Ra and a second portion 132-Rb of the first conductive layer 132 which are in contact with both sides of the resistance material layer 210 in the resistance region RR As shown in FIG. A space defined by the resistance terminal insulating film 222 is formed between the first portion 132-Ra and the second portion 132-Rb of the first conductive layer 132 formed in the resistance region RR .

A portion 224C of the dielectric material pattern formed on one portion 132-Ca of the first conductive layer 132 formed in the capacitor region CR of the second dielectric material pattern 224 is formed through a subsequent process Which may be referred to as a capacitor dielectric layer 224C, disposed between both electrodes of the capacitor to be desired.

The second dielectric material pattern 224 is formed between the portions 132-Ca, 132-Cb, 132-L1, 132-L2 of the first conductive layer 132 formed in the capacitor region CR and the inductance region LR But it can be formed so as not to fill. A second dielectric material pattern 224 is formed between the portions 132-Ca, 132-Cb, 132-L1, and 132-L2 of the first conductive layer 132 formed in the capacitor region CR and the inductance region LR Is formed.

The portion 224L formed in the inductance region LR of the second dielectric material pattern 224 is formed by the portion 132-L2 of the first conductive layer that is an extended portion of the conductive line for forming the coil constituting the inductor, It is possible to cover both the upper surface and the side surface.

Referring to FIG. 5F, a first dummy mask 240 is formed to fill a space defined by the second dielectric material pattern 224 in the capacitor region C-R and the inductance region L-R. The first dummy mask 240 includes a first portion 240a that protrudes in a convex shape and fills a space defined by the second dielectric material pattern 224 in the capacitor region CR and a second portion 240b that extends in the inductive- And a second portion 240b protruding in a convex shape to fill a space defined by the dielectric material pattern 224. [ For example, the first dummy mask 240 may form a mask pattern (not shown) in the spaces defined by the second dielectric material pattern 224 in the capacitor region CR and the inductance region LR, The mask pattern can be formed by a reflow process by heat treatment or the like. The mask pattern may be a photoresist pattern.

A second dummy mask 242 filling a space defined by the resistance terminal insulating film 222 is formed between the first portion 132-Ra and the second portion 132-Rb of the first conductive layer 132, Can be further formed. The second dummy mask 242 may be performed in the same process as the first dummy mask 240 forming process. Therefore, the second dummy mask 232 can also protrude in a convex shape.

A spare seed layer 184a is formed to cover the upper surface of the semiconductor substrate 110 on which the first and second dummy masks 240 and 242 are formed. The spare seed layer 184a may be formed to cover the upper surfaces of the first and second dummy masks 240 and 242. [ The spare seed layer 184a may be formed by a sputtering process using, for example, titanium and / or gold.

Referring to FIG. 5G, a third mask 196 may be formed on the pre-seed layer 184a. A third mask 196 may be formed on the second dummy mask 242 in the resistive region R-R. The third mask 196 may be formed to further cover a portion of the first conductive layer 132 in the capacitor region C-R. A portion of the second conductive layer 134 corresponding to both electrodes of the capacitor may be formed on both sides of the portion of the third mask 196 covering the portion of the first conductive layer 132 in the capacitor region C-R.

However, the third mask 196 is formed so as not to cover the upper side of the first dummy mask 240 and the upper side of the capacitor dielectric layer 224C.

Referring to FIG. 5H, a second conductive layer 134 is formed on the pre-seed layer 184a exposed by the third mask 196. As shown in FIG. In the exemplary embodiments, the second conductive layer 134 may be formed using copper, nickel, gold or silver, or a combination thereof. For example, the second conductive layer 134 may have a two-layer structure of copper and gold. The process for forming the second conductive layer 134 may be an electrolytic plating process using the preliminary seed layer 184a as a seed, or an electroless plating process.

Thereafter, the first and second dummy masks 240 and 242 and the third mask 196 may be removed together. The first dummy mask 240 is removed so that a second dielectric material pattern 140 is formed between the third portion 132-Ca and the fourth portion 132-Cb of the first conductive layer 132 in the capacitor region CR. A first air bridge space AS2C defined by the first air bridge space 224 may be formed. Also, a second air bridge space AS2L defined by the second dielectric material pattern 224 may be formed between the first conductive layers 132 in the inductance area L-R. The second air bridge space AS2L may be a space between the inductors, i.e., the conductive lines for constructing the coil. On the other hand, the second dummy mask 242 is removed so that a first dielectric material 132 is formed between the first portion 132-Ra and the second portion 132-Rb of the first conductive layer 132 in the resistance region RR. A first recess AS2R defined by the pattern 222 may be formed.

Thereafter, the portion of the pre-seed layer 184a exposed by the removal of the third mask 196 may be removed to form the seed layer 184. The conductive pattern 130 including the first conductive layer 132 and the second conductive layer 134 can be formed. The sides of the seed layer 184 may be aligned with the sides of the second conductive layer 134. Accordingly, each of the plurality of conductive patterns 130 can be electrically separated from the adjacent conductive patterns 130. For example, the process for removing the exposed portion of the pre-seed layer (184a in Figure 5G) may be a reactive ion etching process.

Referring again to FIG. 3, a passivation layer 226 may be formed on the semiconductor substrate 110 on which the conductive pattern 130 is formed. The portion of the conductive pattern 130 that is not covered by the passivation layer 226 may be used as a pad connected to a bonding wire, an electric wire, or the like.

In the exemplary embodiments, the passivation layer 226 may comprise an SU-8 photoresist material. The SU-8 photoresist material may have good adhesion to silicon, gallium arsenide, gallium nitride, indium phosphide, glass or metal materials, and may have high electrical insulating properties. Thus, the passivation layer 226 can effectively protect the components (i.e., surface mount resistor R, capacitor C, and inductor L) from moisture or unwanted oxidation reactions.

In an exemplary process for forming the passivation layer 226, a SU-8 photoresist material layer is applied or deposited on the semiconductor substrate 110 with the conductive pattern 130 formed thereon by spin coating, and the SU-8 The photoresist material layer may be soft baked. The passivation layer 226 may then be patterned by performing an exposure and development process on the applied SU-8 photoresist material layer. In particular, a portion of the passivation layer 226 may be removed and the top surface of the conductive pattern 130 exposed.

Alternatively, the SU-8 photoresist material may be thermally treated at a predetermined temperature (for example, at a temperature of 40 to 80 DEG C) for several to several tens of minutes before applying or depositing the SU-8 photoresist material layer. Pre-treatment of the resist material may be performed.

Optionally, a room temperature cooling process for several to several tens minutes may be further performed after soft-baking the SU-8 photoresist material layer. The room temperature cooling process may be performed to prevent stress in the passivation layer 226 or cracks caused thereby. Alternatively, a curing or hard baking process may be performed after the developing process.

The RF integrated circuit 100 can be completed by performing the above-described process.

According to the manufacturing method of the RF integrated circuit 100, the first conductive layer 132 having excellent flatness can be formed by the electron beam evaporation process. Thus, the coverage characteristics of the capacitor dielectric layer 224C formed on the first conductive layer 132 can be improved, and the electrical short circuit or the like caused by the poor coverage can be prevented, so that the capacitor C can have a high breakdown voltage have.

In addition, since the first conductive layer 132 is formed of a single layer formed by the electron beam evaporation process without the seed metal layer, the seed metal layer and the etching process and / or the cleaning process of the seed metal layer may be omitted . Accordingly, the size distribution of the surface mount resistance R caused by the processes for forming the seed metal layer can be reduced, and the resistance accuracy of the surface mount resistor R can be improved.

On the other hand, as the passivation layer 226 includes SU-8 photoresist material, a direct exposure and development process can be performed on the passivation layer 226 without additional mask formation. Thus, instead of performing the deposition process of the insulating layer, the formation of the photoresist mask, and the etching process using the photoresist mask as an etch mask, as generally performed to form the passivation layer 226, The passivation layer 226 may be formed by an application process of the material layer, followed by an exposure and development process. Thus, the process for manufacturing the passivation layer 226 can be facilitated, and the manufacturing cost can be reduced. In addition, since the formation and etching processes of the insulating layer are omitted, mechanical and chemical damage to the lower components in the process of forming and etching the insulating layer can be prevented.

Hereinafter, an experimental example of the RF integrated circuit 100 manufactured by the manufacturing method of FIGS. 5A to 5H will be described.

FIG. 6 is focused ion beam (FIB) images representing the respective portions of the RF integrated circuit 100. Particularly, FIG. 6A is an image showing the entire upper surface of the RF integrated circuit 100, and FIGS. 6B and 6C are enlarged images of the inductor portion.

Referring to FIG. 6, the RF integrated circuit 100 has a chip area of 800 μm × 610 μm and includes a lower metal layer and an upper metal layer of the inductor (eg, the first conductive layer 132 and the second conductive layer Layer 134) is spaced apart by an interval of about 1.8 [mu] m.

FIGS. 7A and 7B are AFM (atomic force microscopy) images showing the surface morphology of the first conductive layer according to Experimental Examples and Comparative Examples, respectively.

Referring to FIGS. 7A and 7B, the first conductive layer (FIG. 7A) according to the experimental example has a root mean square roughness of about 1.790 nm, while the first conductive layer (FIG. 7B) Has an RMS roughness of about 14.297 nm. It can be seen that the first conductive layer according to the experimental example has a flat surface morphology because it includes the metal material layer obtained by the electron beam evaporation process without forming the seed metal layer. On the other hand, the first conductive layer according to the comparative example forms a seed metal preliminary layer, and after the seed metal preliminary layer is patterned by a photomask process to form a seed metal layer, the seed metal layer is subjected to an electrolytic plating process To form a metal layer. It can be confirmed that the first conductive layer according to the experimental example formed by the optimized electron beam evaporation process has remarkably flat and smooth surface characteristics compared to the first conductive layer formed by the seed metal layer and the electrolytic plating process .

8 is a graph showing the Q-factor of the inductor according to the experimental example and the comparative example.

Referring to FIG. 8, the inductor 810 according to the experimental example showed a better Q-index than the inductor 820 according to the comparative example. Although not shown, the inductor 810 according to the experimental example has a value closer to the Q-index according to a designed value corresponding to about 28.5 at 2.4 GHz, as compared with the inductor 820 according to the comparative example.

Here, the RF integrated circuit according to the comparative example includes a seed metal layer and a first conductive layer formed by an electroplating process, and further includes a passivation layer including silicon nitride. An RF integrated circuit according to an experimental example includes a first conductive layer formed by an electron beam evaporation process and includes a passivation layer including an SU-8 photoresist material. Particularly, the inductor according to the experimental example is a coil type inductor composed of a metal line having an inner diameter of 150 mu m, a line width of 15 mu m, a lane spacing of 15 mu m, a number of revolutions of 5, and a line height of 7.5 mu m, The distance between the layer and the second conductive layer is 1.8 [mu] m.

9 is a graph showing resistance values of surface mount resistances and breakdown voltages of capacitors according to Experimental Examples and Comparative Examples.

Referring to FIG. 9, it can be seen that the surface mount resistor 910 according to the experimental example exhibits a significantly lower resistance than the surface mount resistor 920 according to the comparative example. This is because as the seed metal layer and its etching and cleaning processes are omitted in the step of forming the first conductive layer constituting the surface mounting resistance as described above, the size dispersion of the first conductive layer is reduced and the resistance precision is improved .

Also, it can be seen that the capacitor 930 according to the experimental example shows a significantly higher breakdown voltage than the capacitor 940 according to the comparative example. The capacitor 930 according to the experimental example shows a breakdown voltage as high as about 20V on average. In addition, the capacitor 930 according to the experimental example has no electrical short-circuiting sample among the 30 test samples, while the capacitor 940 according to the comparative example has electrical short circuit in four test samples out of 30 test samples. Lt; / RTI > This is because, as described above, the surface morphology of the first conductive layer is flat, so that the coverage characteristic of the capacitor dielectric layer over the first conductive layer can be excellent, so that electrical shorting that may occur during the formation of the capacitor dielectric layer can be prevented .

10 is a graph showing a reliability test result of an RF integrated circuit according to an experimental example.

Referring to FIG. 10, a highly accelerated stress test (HAST) results in a low leakage current even when exposed to a long time harsh environment of an RF integrated circuit according to an experimental example.

Accelerated stress testing was performed by storing test samples at a temperature of 120 DEG C, a humidity of 85%, and a pressure of 2 atm. Samples 1 (C1) and 2 (C2) are capacitors having a 200 占 퐉 占 200 占 퐉 area, and samples 3 (C3) and 4 (C4) are capacitors having a 50 占 퐉 占 50 占 퐉 area. The samples C1, C2, C3 and C4 exhibited a low leakage current value of approximately 1 x 10 < -8 > A even after exposure to the harsh environment for 720 hours, indicating that the passivation layer comprising SU- The RF integrated circuit 100 acts as a protective layer that effectively prevents moisture penetration or an undesirable oxidation reaction even in an environment. Thus, it can be confirmed that the RF integrated circuit 100 has improved reliability.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, but, on the contrary, This is possible.

100: RF integrated circuit 110: substrate
120: element isolation layer 130: conductive pattern
132: first conductive layer 134: second conductive layer
184: Seed layer 192, 194, 196: mask
222, 224: dielectric material pattern 226: passivation layer
240, 242: dummy mask

Claims (8)

A semiconductor substrate in which a resistance region, a capacitor region, and an inductance region are defined;
A conductive pattern disposed on the semiconductor substrate and including a first conductive layer and a second conductive layer on the first conductive layer; And
And a passivation layer covering the upper surface of the second conductive layer, the passivation layer being made of an SU-8 photoresist material,
Wherein the first conductive layer includes a first portion and a second portion that are spaced apart from each other in the resistance region, and the first portion, the second portion, and the semiconductor portion The layer of resistive material disposed on the substrate constitutes a surface mount resistance,
Wherein the first conductive layer further comprises a third portion disposed in the capacitor region and the second conductive layer includes a first portion disposed on the third portion of the first conductive layer in the capacitor region A first portion of the first conductive layer, a second portion of the second conductive layer, and a second portion of the first conductive layer, the third portion of the first conductive layer, the first portion of the second conductive layer, The dielectric layer constitutes a capacitor,
Wherein the first conductive layer further comprises a fourth portion disposed in the inductance region and the second conductive layer further comprises a second portion disposed on the fourth portion of the first conductive layer in the inductance region And the fourth portion of the first conductive layer and the second portion of the second conductive layer constitute an inductor. The method according to claim 1,
Wherein the surface mount resistor, the capacitor, and the inductor constitute a passive RF device. The method according to claim 1,
And an element isolation layer formed between the semiconductor substrate and the conductive pattern, the element isolation layer including an inorganic insulating material. The method according to claim 1,
Wherein in the inductance region, the first conductive layer further includes a fifth portion disposed at the same level as the fourth portion of the first conductive layer,
Wherein the second portion of the second conductive layer is spaced apart in a direction perpendicular to the fifth portion of the first conductive layer and the second portion of the second conductive layer and the fifth And an air bridge space is disposed between the parts. 5. The method of claim 4,
And the portion of the passivation layer formed in the inductance region conformally covers the upper surface of the second portion of the second conductive layer. The method according to claim 1,
Wherein the first conductive layer has a planar surface morphology. The method according to claim 1,
Wherein the first conductive layer has a root mean square roughness (RMS) roughness of 30 nm or less. The method according to claim 1,
Further comprising an active RF device including a transistor disposed on the semiconductor substrate.
KR1020150034543A 2015-03-12 2015-03-12 Radio Frequency Integrated Circuit KR101680282B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020150034543A KR101680282B1 (en) 2015-03-12 2015-03-12 Radio Frequency Integrated Circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020150034543A KR101680282B1 (en) 2015-03-12 2015-03-12 Radio Frequency Integrated Circuit

Publications (2)

Publication Number Publication Date
KR20160109682A KR20160109682A (en) 2016-09-21
KR101680282B1 true KR101680282B1 (en) 2016-11-28

Family

ID=57080423

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020150034543A KR101680282B1 (en) 2015-03-12 2015-03-12 Radio Frequency Integrated Circuit

Country Status (1)

Country Link
KR (1) KR101680282B1 (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007142109A (en) 2005-11-17 2007-06-07 Tdk Corp Electronic part

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007142109A (en) 2005-11-17 2007-06-07 Tdk Corp Electronic part

Also Published As

Publication number Publication date
KR20160109682A (en) 2016-09-21

Similar Documents

Publication Publication Date Title
US20220384113A1 (en) Capacitor
KR20000053364A (en) Beol decoupling capacitor
CN109599391B (en) Semiconductor structure and manufacturing method thereof
US8022503B2 (en) Anti-fusse structure and method of fabricating the same
US11217395B2 (en) Capacitor
US7169684B2 (en) Device having inductors and capacitors and a fabrication method thereof
US20190074348A1 (en) Capacitor
US8760843B2 (en) Capacitive device and method for fabricating the same
JP2009010114A (en) Dielectric thin-film capacitor
CN107045913B (en) Electronic component
US7745280B2 (en) Metal-insulator-metal capacitor structure
CN109923630B (en) Capacitor with a capacitor body
US11158456B2 (en) Trench capacitor
KR101146225B1 (en) Method for manufacturing a semiconductor device
KR101680282B1 (en) Radio Frequency Integrated Circuit
JP6764658B2 (en) Electronic components
JP2006005309A (en) Capacitor device
KR101680283B1 (en) Surface-mounted inductors and radio frequency integrated circuit including the same
KR100865760B1 (en) Multi layer capacitor device and multi layer varistor device and method for manufacturing the same
KR101598203B1 (en) Radio Frequency Integrated Circuit
WO2024004985A1 (en) Electronic component
US11574996B2 (en) High-voltage capacitor, system including the capacitor and method for manufacturing the capacitor
JP2017208419A (en) Semiconductor device and manufacturing method of the same
CN117178360A (en) Integrated circuit structure including metal-insulator-metal (MIM) capacitor module and Thin Film Resistor (TFR) module
CN117337487A (en) Integrated inductor comprising a multipart via layer inductor element

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20191104

Year of fee payment: 4