KR101675851B1 - Liquid crystal display device - Google Patents

Abstract

The present invention relates to a liquid crystal display device in which an aperture ratio can be increased, and a liquid crystal display device according to the present invention includes a first substrate and a second substrate facing each other; A liquid crystal layer filled between the first substrate and the second substrate; A first gate line and a first data line formed on an upper surface of the first substrate facing the second substrate, the first gate line and the first data line intersecting with each other, and a plurality A first transistor array including a first transistor of the plurality of first pixels and controlling a light transmittance of each of the plurality of first pixels; And a second gate line and a second data line overlapping the first transistor array and formed on the back surface of the second substrate facing the first substrate so as to cross each other, And a second transistor array including a plurality of second transistors formed in a region where data lines intersect and controlling light transmittance of each of a plurality of second pixels alternating with the plurality of first pixels in one direction.

Description

[0001] LIQUID CRYSTAL DISPLAY DEVICE [0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly to a liquid crystal display device in which an aperture ratio can be increased.

In recent years, as the information age has come to a full-fledged information age, a display field for visually expressing electrical information signals has been rapidly developed. In response to this, various flat panel display devices having excellent performance of thinning, light weight, Flat Display Device) has been developed to replace CRT (Cathode Ray Tube).

Specific examples of such flat panel display devices include a liquid crystal display device (LCD), an organic light emitting display (OLED), an electrophoretic display (EPD) A plasma display panel (PDP), a field emission display (FED), an electroluminescence display (ELD), and an electro-wetting display (EWD) And the like. In general, a flat panel display panel, which realizes images, is an essential component. The flat panel display panel has a structure in which a pair of substrates are bonded together with a unique light emitting material or a layer of polarizing material therebetween. Among them, a liquid crystal display device is a device for displaying an image by adjusting the light transmittance of a liquid crystal by using an electric field as a typical example of a flat panel display device.

1 is a cross-sectional view of a conventional liquid crystal display device. FIG. 2 is an equivalent circuit diagram of a transistor array in the liquid crystal display device shown in FIG. 1, and FIG. 3 is a plan view showing a black matrix layer in the liquid crystal display device shown in FIG.

1, a conventional liquid crystal display device 10 includes a lower substrate 11 and an upper substrate 12 opposed to each other, a liquid crystal layer 12 filled between the lower substrate 11 and the upper substrate 12, (TFT) 13 for controlling the light transmittance of the liquid crystal layer 13 corresponding to a plurality of pixel regions on the upper surface of the lower substrate 11, A black matrix layer 15 formed on the back surface of the upper substrate 12 to prevent light leakage from a plurality of pixel regions, and a black matrix layer 15 formed on the back surface of the upper substrate 12 so as to be overlapped with the black matrix layer 15 And a color filter layer (CF) 16 that transmits light in a wavelength region corresponding to a plurality of pixel regions, respectively.

2, the transistor array includes a gate line GL and a data line DL, and a gate line GL and a data line DL, which are cross- And a plurality of transistors (14) each disposed in an intersecting region. In each of the plurality of transistors, the gate electrode is connected to a gate driver (gate driver) 21, which generates a gate signal according to a control signal of the controller 20, through a gate line GL, The drain electrode is connected to a source driver 22 for generating a data signal in accordance with a control signal of a controller and a drain electrode is connected to a region corresponding to a plurality of pixels Quot; region "). Each transistor turns on and off in response to a gate signal applied through a gate line GL. When turned on, each transistor receives a data signal through a data line DL and applies a pixel voltage to the pixel electrode. When a pixel voltage is applied to the pixel electrode, an electric field is generated between the pixel electrode and the common electrode to which the common voltage is applied, and the light transmittance of the pixel region is adjusted, so that the pixel displays a predetermined luminance. That is, when a pixel voltage is applied to the pixel electrode, a voltage is applied to a liquid crystal capacitor (LC) (hereinafter referred to as a "liquid crystal capacitor") of the liquid crystal layer 13 corresponding to the pixel electrode and the common electrode, An electric field is generated. With such an electric field, the light transmittance of the pixel region is adjusted while the cell direction of the liquid crystal cell provided in the liquid crystal layer (13, LC) corresponding to the pixel region is changed, thereby controlling the brightness of each of the plurality of pixels . At this time, a storage capacitor (Cst) is connected in parallel with the liquid crystal capacitor (LC) in order to maintain the electric field of the liquid crystal capacitor for a predetermined time even after the transistor is turned off.

On the other hand, the gate line GL and the data line DL and the plurality of transistors 14 (TFTs) arranged on the display region are regions corresponding to the outline of the pixel region, not the pixel region through which light is transmitted, Is covered by the layer (15), so that light leakage is prevented. That is, the remainder obtained by subtracting the outer region of the pixel region covered by the black matrix layer 15 in the display region becomes the pixel region.

Generally, if the ratio of the area occupied by the pixel area in the display area (hereinafter referred to as "aperture ratio") is increased, the image quality of the liquid crystal display device can be improved. The gate lines GL and the data lines DL and the plurality of transistors 14 are formed on the lower substrate 11 and the gate lines GL and the data lines DL, (14, TFT) has an area that can be stably driven. Therefore, in the conventional liquid crystal display device, the maximum opening ratio is limited by the region where the gate line GL, the data line DL, and the plurality of transistors 14 (TFT) are arranged, There is a problem that it can not be improved beyond this limit.

An object of the present invention is to provide a liquid crystal display device capable of reducing the area of an area corresponding to the outline of the pixel area in the display area and increasing the maximum aperture ratio as compared with the prior art.

According to an aspect of the present invention, there is provided a plasma display panel comprising: a first substrate and a second substrate facing each other; A liquid crystal layer filled between the first substrate and the second substrate; A first gate line and a first data line formed on an upper surface of the first substrate facing the second substrate, the first gate line and the first data line intersecting with each other, and a plurality A first transistor array including a first transistor of the plurality of first pixels and controlling a light transmittance of each of the plurality of first pixels; And a second gate line and a second data line overlapping the first transistor array and formed on the back surface of the second substrate facing the first substrate so as to cross each other, And a second transistor array including a plurality of second transistors formed in a region where data lines intersect and controlling a light transmittance of each of a plurality of second pixels alternating with the plurality of first pixels in one direction, Device.

As described above, the liquid crystal display device according to the present invention is a liquid crystal display device that displays an image by pixels composed of a plurality of first pixels and a plurality of second pixels, and controls the light transmittance of each of the plurality of first pixels And a second transistor array formed on the upper substrate so as to overlap the first transistor array and controlling a light transmittance of each of the plurality of second pixels. Accordingly, the plurality of first pixels and the plurality of second pixels are individually controlled by the first transistor array and the second transistor array, and the pixel array region and the second transistor array in the display region are controlled by the region where the first transistor array and the second transistor array overlap, And the maximum aperture ratio is increased, so that the image quality of the liquid crystal display device can be improved.

1 is a cross-sectional view of a conventional liquid crystal display device.
Fig. 2 is an equivalent circuit diagram of a transistor array in the liquid crystal display shown in Fig. 1. Fig.
3 is a plan view showing a black matrix layer in the liquid crystal display device shown in Fig.
4 is an equivalent circuit diagram of a liquid crystal display according to an embodiment of the present invention.
5 is a cross-sectional view of a liquid crystal display device according to an embodiment of the present invention.
6 is a detailed sectional view of the liquid crystal display shown in Fig.
7 is a schematic view illustrating a connection mode of the first transistor array and the second transistor array shown in FIG. 6 and the gate pad.
8 is a schematic diagram showing a connection mode of the first transistor array and the second transistor array shown in FIG. 6 and the data pad.
Fig. 9 is a perspective view of the connection block shown in Figs. 7 and 8. Fig.
10 is a cross-sectional view of a liquid crystal display device according to another embodiment of the present invention.
11 is a plan view showing a black matrix layer in the liquid crystal display shown in Figs. 4 to 10. Fig.

Hereinafter, a liquid crystal display device according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

First, a liquid crystal display according to an embodiment of the present invention will be described with reference to FIGS. 4 to 6. FIG.

4 is an equivalent circuit diagram of a liquid crystal display according to an embodiment of the present invention. 5 is a cross-sectional view of a liquid crystal display device according to an embodiment of the present invention, and FIG. 6 is a detailed sectional view of the liquid crystal display device shown in FIG.

4, the liquid crystal display 100 according to the embodiment of the present invention includes pixels P1 and P2 whose respective brightnesses are determined so that an image can be displayed, A plurality of first pixels P1 controlled by a transistor array, and a plurality of second pixels P2 controlled by a second transistor array. At this time, among the display areas in which an image is displayed, the plurality of first pixels P1 correspond to the plurality of first pixel areas, respectively, and the plurality of second pixels P2 correspond to the plurality of second pixels. In the display area, the plurality of first pixels P1 and the plurality of second pixels P2 are alternately arranged in one direction or two mutually perpendicular directions.

5 and 6, the liquid crystal display 100 according to the embodiment of the present invention includes a lower substrate 110, an upper substrate 120, a lower substrate 110, A liquid crystal layer (LC) 130 filled between the substrates 120, a first supporting substrate 111 supporting the lower substrate 110, a first supporting substrate 111 facing the upper substrate 120 A first transistor array 112 formed on the upper surface of the first transistor array 112 for controlling the light transmittance of each of the plurality of first pixels 142 and 144 (corresponding to "P1" in FIG. 4) A color filter CF formed on the upper surface of the support substrate 111 to emit light in a specific wavelength range, a second support substrate 121 supporting the upper substrate 120, The first transistor array 112 is formed so as to overlap with the first transistor array 112 on the backside of the second supporting substrate 121 facing the first transistor array 112, A black matrix layer 122 for preventing leakage is formed on the black matrix layer 122 to control the light transmittance of each of the plurality of second pixels 141 and 143 (corresponding to "P2" in FIG. 4) And a second transistor array 123 connected to the second transistor array.

The first transistor array 112 and the second transistor array 123 are formed on the lower substrate 110 and the upper substrate 120 so as to overlap each other. The black matrix layer 122 is formed between the second support substrate 121 and the second transistor array 123 and corresponds to the first transistor array 112 and the second transistor array 123 formed to overlap with each other And blocks the light leakage in the region where the light is emitted.

The color filter layer CF is formed on the upper surface of the first supporting substrate 111 in correspondence with the plurality of first pixel regions 142 and 144 and the plurality of second pixel regions 141 and 143, And emits light in the wavelength region corresponding to the first pixel 142 or 144 and the second pixel 141 or 143, respectively. The color filter layer CF includes a dye or a pigment that transmits light in a specific wavelength range corresponding to the plurality of first pixels 142 and 144 and the plurality of second pixels 141 and 143 in white light . For example, the color filter layer CF has a region 113a that transmits red light, a region 113b that transmits green light, and a blue light that transmits blue light, And a plurality of first pixel regions 142 and 144 and a plurality of second pixel regions 141 and 143 are divided into red (RED), green (GREEN), and green BLUE and 113c and emits light corresponding to one of the three wavelengths of red, green and blue, and represents a white light by a combination of three first pixels or second pixels corresponding to red, green and blue. One unit pixel can be defined.

4 and 5, the first transistor array 112, which controls the light transmittance of each of the plurality of first pixels P1, is formed on the upper surface of the first supporting substrate 111 so as to be cross- The first data line DL and the first gate line GL1 intersect with the first data line DL to form the first gate line GL1 and the first data line DL, And a plurality of first transistors 1121 and 1122 each having a gate electrode and a source electrode connected to one data line DL. The second transistor array 123 for controlling the light transmittance of each of the plurality of second pixels P2 includes a second gate line GL2 formed on the back surface of the second support substrate 121 so as to cross each other, The data line DL is formed in the second gate line GL2 and the gate line GL2 is formed in the second gate line GL2 in the region where the second gate line GL2 and the second data line DL intersect. And a plurality of second transistors 1231 and 1232 to which a source electrode is connected.

6, each of the plurality of first transistors 1121 and 1122 includes a first gate line (not shown in FIG. 4, corresponding to GL1) and a second gate line A gate insulating layer GI formed on the entire upper surface of the first supporting substrate 111 including a first gate line GX and a gate electrode GX, A semiconductor layer which is formed on the semiconductor layer to overlap with the gate electrode GX on the gate electrode GI and a source which overlaps on both sides of the gate electrode GX on the semiconductor layer Active and which are spaced from each other to form a channel therebetween, And includes an electrode (S) and a drain electrode (D). Here, the source electrode S of each of the plurality of first transistors 1121 and 1122 is connected to a first data line (not shown in FIG. 4, corresponding to DL).

The lower substrate 110 includes a first passivation layer Passi1 formed between the first transistor array 112 and the color filter layer CF to cover the first transistor array 112 to be electrically stable, The overcoat layer OC is formed on the entire surface of the first passivation layer Passi1 including the color filter layer CF and the overcoat layer OC is formed on the entire surface of the first passivation layer Passi1 including the color filter layer CF, Are formed in the plurality of first pixel regions 142 and 144 on the contact hole CH and the overcoat layer OC formed in the passivation layer Passi1 and the overcoat layer OC, A plurality of first pixel electrodes PX connected to the drain electrodes D of the first transistors 1121 and 1122 and a plurality of first pixel regions 142 and 144 on the overcoat layer OC And a plurality of first common electrodes CX formed so as to alternate with the first pixel electrodes PX of the first pixel electrodes PX. The pixel voltage corresponding to each of the plurality of first pixels 142 and 144 is applied to the plurality of first pixel electrodes PX in accordance with whether each of the plurality of first transistors 1121 and 1122 is turned on, A common voltage corresponding to all of the pixels P1 and P2 is applied to the first common electrode CX of the pixel PX. The first passivation layer Passi1 is formed on the entire surface of the gate insulating layer GI including the source and drain electrodes S and D and the semiconductor layer Active of each of the plurality of first transistors 1121 and 1122 do.

Accordingly, when the first transistors 1121 and 1122 turn on in response to the gate signal of the first gate line GL1, the plurality of first pixels 142 and 144 turn on the data signal of the first data line DL A pixel voltage is applied to the first pixel electrode PX corresponding to the first pixel electrode PX and a predetermined electric field generated between the first pixel electrode PX and the first common electrode CX under the liquid crystal layer 130, The light transmittance is adjusted while the direction of the liquid crystal cell of the liquid crystal layer 130 corresponding to one pixel region 142 or 144 is varied to display the luminance controlled by the first transistor array 112.

Each of the plurality of second transistors 1231 and 1232 included in the second transistor array 123 is connected to a second gate line (not shown) on the upper surface of the second supporting substrate 121, A gate electrode GX formed on the upper surface of the second supporting substrate 121 including a second gate line (not shown) and a gate electrode GX, A semiconductor layer Active formed so as to overlap with the gate electrode GX on the gate insulating layer GI and the semiconductor layer Active formed on both sides of the gate electrode GX on the semiconductor layer Active, And includes a source electrode S and a drain electrode D which form a channel therebetween. Here, the source electrode S of each of the plurality of second transistors 1231 and 1232 is connected to a second data line (not shown in FIG. 4, corresponding to DL).

The upper substrate 120 may include a second protection layer 121 formed on the front surface of the second supporting substrate 121 including the second transistor array 123 to cover the second transistor array 123 to be electrically stable, (D) of the plurality of second transistors 1231 and 1232, each of which is formed in each of the plurality of second pixel regions 141 and 143 on the second passivation layer (Passi2) and the second passivation layer (Passi2) The second pixel electrodes PX and the plurality of second common electrodes PX are formed in the second pixel regions 141 and 143 on the second pixel electrode PX and the second passivation layer Passi2, (CX). Here, the pixel voltages corresponding to the plurality of second pixels 141 and 143 are applied to the plurality of second pixel electrodes PX depending on whether the plurality of second transistors 1231 and 1232 are turned on, respectively, A common voltage corresponding to all of the pixels is applied to the second common electrode CX of the pixel TFT. The second passivation layer Passi2 is formed on the entire surface of the gate insulating layer GI including the source electrode, the drain electrode S and the semiconductor layer Active of each of the plurality of second transistors 1231 and 1232, do.

Accordingly, when the second transistors 1231 and 1232 turn on in response to the gate signal of the second gate line GL2, the plurality of second pixels 141 and 143 turn on the data signal of the second data line DL A pixel voltage is applied to the second pixel electrode PX corresponding to the first pixel electrode PX and a predetermined electric field generated between the second pixel electrode PX and the second common electrode CX on the liquid crystal layer 130, The light transmittance is adjusted while changing the direction of the liquid crystal cell of the liquid crystal layer 130 corresponding to the two pixel regions 141 and 143 to thereby display the luminance controlled by the second transistor array 123. [

The liquid crystal display device 100 according to the embodiment of the present invention includes the lower substrate 110 and the upper substrate 120 facing each other and the lower substrate 110 and the upper substrate 120 that are filled between the lower substrate 110 and the upper substrate 120 A first gate line GL1 and a first data line DL and a first gate line GL1 and a first data line DL formed in a liquid crystal layer 130 and a lower substrate 110, A first transistor array 112 for controlling the light transmittance of each of the plurality of first pixels P1, 142, and 144, including a plurality of first transistors 1121 and 1122 formed in intersecting regions, A plurality of second gate lines GL1 and GL2 formed in the region where the second gate lines GL2 and the second data lines DL and the second gate lines GL2 and the second data lines DL cross each other, A second transistor array 123 for controlling the light transmittance of each of the plurality of second pixels P2, 141, and 143, including the second transistors 1231 and 1232, It comprise. Here, the first transistor array 112 and the second transistor array 123 are arranged so as to overlap with each other, and substantially the light due to the arrangement of the first transistor array 112 and the second transistor array 123 in the display region By minimizing the decrease in the area of the pixel region that can be emitted, the maximum aperture ratio is increased.

The liquid crystal display device 100 according to the embodiment of the present invention can prevent the light leakage in the region corresponding to the first transistor array 112 and the second transistor array 123 overlapping with each other, A black matrix layer 121 formed between the upper substrate 120 and the second transistor array 123 and a first protection formed on the entire surface of the first supporting substrate 111 including the first transistor array 112. [ (Passi1), a plurality of first pixels (142, 144), and a plurality of second pixels (141, 143) The plurality of first pixels 142 and the plurality of first pixels 142 respectively corresponding to the first pixels 142 and 144 on the overcoat layer OC and the overcoat layer OC formed on the filter layer CF and the color filter layer CF, And a plurality of first common electrodes CX and a second transistor array 123 including the first pixel electrode PX, A plurality of second pixels 141 and 143 corresponding to the plurality of second pixels 141 and 143 on the second passivation layer Passi2 and the second passivation layer Passi2 formed on the front surface of the substrate 121, And further includes an electrode PX and a plurality of second common electrodes CX.

As described above, according to the embodiment of the present invention, all pixels of the liquid crystal display device are divided into a plurality of first pixels P1 and a plurality of second pixels P2.

4, the liquid crystal display according to the exemplary embodiment of the present invention includes first and second data lines DL formed to overlap each other on a lower substrate 110 and an upper substrate 120, And applying different gate signals to the first gate line GL1 and the second gate line GL2 formed to overlap each other on the lower substrate 110 and the upper substrate 120, All of the pixels can be driven individually.

That is, in response to the control signal of the controller 200, the gate driver 210 drives the first transistor array 112 formed on the lower substrate 110 through the first gate line GL1 And applies a second gate signal to the second transistor array 123 formed on the upper substrate 120 through the second gate line GL2. The source driver 220 applies the first and second data signals DL to the first transistor array 112 and the second transistor array 123 according to a control signal of the controller 200 do.

Although not shown in detail, the gate driver 210 is connected to a gate pad (not shown) formed with the first gate line GL1 on the lower substrate 110, and the source driver 2200 is connected to the lower substrate (Not shown) corresponding to the first gate pad corresponding to the first transistor array 112 and the second transistor array 123 corresponding to the data pad (not shown) formed on the first transistor array 110. At this time, The first and second gate pads and data pads (not shown) connected to the gate driver 210 and the source driver 220 are all formed on the lower substrate 110 .

The liquid crystal display according to the embodiment of the present invention includes a second gate pad (not shown) and a data pad (not shown) formed on the lower substrate 110 and a data pad And a connection block for connection with the two-transistor array 123. [

FIG. 7 is a schematic view showing a connection form of the first transistor array and the second transistor array shown in FIG. 6 and the gate pad, FIG. 8 is a cross-sectional view of the connection between the first transistor array and the second transistor array, Fig. 9 is a perspective view of the connection block shown in Figs. 7 and 8. Fig.

7, among the entire gate pads 211 formed on the lower substrate 110 and connected to the gate driving unit 210, the first gate array 211, which corresponds to the first transistor array 112, The gate pad 2111 is formed so as to be connected to the first gate line DL1. Of the entire gate pads 211, a second gate pad 2112 corresponding to the second transistor array 123 is connected to an extension line that contacts the conductor 310 of the connection block 300. 7, the conductor 310 of the connection block 300 and the second gate line GL2 corresponding to the second transistor array 123 are connected to each other. That is, the conductor 310 of the connection block 300 contacts the extended line of the second gate pad 2112 on the lower substrate 110 and contacts the second gate line GL2 on the upper substrate 120, The second gate pad 2112 and the second gate line GL2 are connected to each other through the conductor 310 of the connection block 300. The second transistor array 123 formed on the upper substrate 120 is connected to the second gate pad 2112 formed on the lower substrate 110 by the connection block 300, The second gate signal can be supplied to the gate line GL2. The connection block 300 includes a plurality of conductors 310 corresponding to the plurality of second gate lines GL2, and the plurality of conductors 310 includes a plurality of conductors 310 Are insulated from each other by the nonconductor (320).

8, the data pad 221 formed on the lower substrate 110 and connected to the source driver 220 is connected to the first data line (not shown) of the first transistor array 112 DL1, and the conductor 310 of the connection block 300 is in contact with the first data line DL1. 8, the conductor 310 of the connection block 300 and the second data line DL2 corresponding to the second transistor array 123 are connected. That is, the conductor 310 of the connection block 300 contacts the first data line DL1 on the lower substrate 110 and contacts the second data line DL2 on the upper substrate 120, The first data line 221 and the second data line DL2 are connected through the conductor 310 of the connection block 300. The connection block 300 includes a plurality of conductors 310 corresponding to the plurality of data lines and the plurality of conductors 310 are connected to the plurality of nonconductors 320 disposed therebetween Are insulated from each other.

As described above, the connection block 300 (300) is provided to be connected to the second gate pad 2112 / data pad 221 and the second gate line GL2 / second data line DL2 formed on the lower substrate 110, A rectangular parallelepiped shape having a height corresponding to the interval between the lower substrate 110 and the upper substrate 120 as a whole is formed by alternating the rectangular parallelepiped conductor 310 and the nonconductor 320 as shown in FIG. Respectively. At this time, the distance between adjacent conductors 310, that is, the thickness of the nonconductor 320 with the nonconductor 320 between the second gate pads 2112 or between the data pads 221, .

5 and 6, the color filter layer CF is formed on the lower substrate 110, but it is also possible that the color filter layer CF is formed on the upper substrate 120. As shown in FIG.

10 is a cross-sectional view of a liquid crystal display device according to another embodiment of the present invention.

10, except that the color filter layer CF is formed on the upper substrate 120, not on the lower substrate 110, the liquid crystal display device 101 according to another embodiment of the present invention , And the liquid crystal display device shown in FIG. 5 and FIG. 6, and thus a description thereof will be omitted below.

That is, the liquid crystal display device 101 according to another embodiment of the present invention includes a lower substrate 110 and an upper substrate 120 opposed to each other, a liquid crystal layer (not shown) filled between the lower substrate 110 and the upper substrate 120, (Not shown), a first data line (not shown), a first gate line (not shown), and a first data line (not shown) formed to intersect with each other on the lower substrate 110, A first transistor array 112 for controlling the light transmittance of each of the plurality of first pixels 142 and 144 including a plurality of first transistors 1121 and 1122 formed in the regions where the first and second transistors 142 and 144 intersect, (Not shown) and a second data line (not shown) and a second gate line (not shown) and a second data line And a second transistor (1231, 1232) for controlling the light transmittance of each of the plurality of second pixels (141, 143) It comprises a transistor array 123. Here, the first transistor array 112 and the second transistor array 123 are formed to overlap with each other.

The liquid crystal display device 101 according to another embodiment of the present invention includes a first transistor array 112 and a second transistor array 123, The second transistor array 123 is formed on the black matrix layer 122 and the second support substrate 121 formed between the first pixel array 121 and the second transistor array 123 to overlap the second transistor array 123, , And a color filter layer (CF) that emits light in a wavelength region corresponding to each of the plurality of second pixels (141, 143).

6, the liquid crystal display device 101 according to another embodiment of the present invention may include a first protection formed on the front surface of the lower substrate 110 including the first transistor array 112, A plurality of first pixel electrodes PX and a plurality of first common electrodes PX1 and PX2 corresponding to the plurality of first pixels 142 and 144 on the first passivation layer Passi1 and the first passivation layer Passi1, A black matrix layer 122 and a second transistor array 123 formed between the back surface of the second support substrate 121 and the second transistor array 123 to overlap with the first transistor array 112, A second passivation layer Passi2 formed on the front surface of the upper substrate 120 and a plurality of first pixels 142 and 144 and a plurality of second pixels 141 and 143 on the second passivation layer Passi2, A color filter layer CF formed to emit light in a corresponding wavelength region, an overcoat layer OC formed flat on the color filter layer CF, A plurality of second pixel electrodes PX and a plurality of second common electrodes CX are formed on the overcoat layer OC so as to correspond to the plurality of second pixels 141 and 143, . A plurality of second pixel electrodes PX formed on the overcoat layer OC correspond to a part of the drain electrode D of the second transistors 1231 and 1232 and are respectively connected to a second passivation layer Passi2, Are connected to the drain electrodes D of the second transistors 1231 and 1232 through contact holes (not shown) formed in the overcoat layer OC.

As described above, according to the embodiment and the other embodiment of the present invention, the first transistor array 112 for controlling the plurality of first pixels 142 and 144 and the plurality of second pixels 141 and 143, respectively, Two transistor arrays 123 are formed to overlap with each other. A black matrix layer 122 is formed on the first transistor array 112 and the second transistor array 123 in order to shield the light leakage in the regions corresponding to the first transistor array 112 and the second transistor array 123 disposed on the display region. And is formed overlying the second transistor array 123.

11 is a plan view showing a black matrix layer in the liquid crystal display shown in Figs. 4 to 10. Fig.

11, the solid line indicates a part of the black matrix layer 122 covering the first and second gate lines GL1 and GL2 and the first and second data lines DL1 and DL2 and is arranged in a region where the solid lines cross The rectangular portion representing the first transistor 1121, 1122 and the other portion of the black matrix layer 122 covering the two transistors 1231, 1232. The dotted lines indicate the first pixel region P1 and the second pixel region P1 which are not defined as the first and second gate lines GL1 and GL2 and the first and second gate lines GL1 and GL2 are overlapped with each other, P2).

As shown in FIG. 3, the conventional black matrix layer 15 is formed to correspond to the total area of each of the gate lines, the data lines, and the transistors, while, as shown in FIG. 11, The black matrix layer 122 is formed so as to correspond to half of the total area of the first and second gate lines and the first and second transistors. Therefore, according to the embodiment of the present invention, the area of the black matrix layer 122 is reduced by the area where the first transistor array 112 and the second transistor array 123 overlap, and the maximum aperture ratio is increased.

As a result, the area occupied by the first transistor array 112 and the second transistor array 123 in the display area is reduced, and the region where the light leakage is blocked by the black matrix layer 122 is reduced, The area occupied by the pixel region in which the light is emitted is increased, so that the maximum aperture ratio is increased and thus the image quality can be improved.

The present invention described above is not limited to the above-described embodiment and the accompanying drawings, and various substitutions, modifications, and changes may be made without departing from the technical spirit of the present invention.

100: liquid crystal display device 110: lower substrate
112: first transistor array 120: upper substrate
122: black matrix layer 123: second transistor array
P1, 142, 144: first pixel P2, 141, 143: second pixel

Claims (9)

A first substrate and a second substrate facing each other;
A liquid crystal layer filled between the first substrate and the second substrate;
A first gate line and a first data line formed on an upper surface of the first substrate facing the second substrate, the first gate line and the first data line intersecting with each other, and a plurality A first transistor array including a first transistor of the plurality of first pixels and controlling a light transmittance of each of the plurality of first pixels; And
A second gate line and a second data line formed on the back surface of the second substrate facing the first substrate, the second gate line and the second data line intersecting with the first transistor array, A second transistor array including a plurality of second transistors formed in regions where lines cross each other and controlling a light transmittance of each of a plurality of second pixels alternating with the plurality of first pixels in one direction; And
And a black matrix layer formed on the rear surface of the second substrate so as to overlap with the first transistor array and preventing light leakage in a region where the first transistor array and the second transistor array are disposed,
And the second transistor array is formed on the black matrix layer. delete The method according to claim 1,
A plurality of first gate pads formed on the upper surface of the first substrate to correspond to the plurality of first gate lines;
A plurality of second gate pads formed on the upper surface of the first substrate to correspond to the plurality of second gate lines; And
And a connection block disposed between the first substrate and the second substrate, the connection block connecting the plurality of second gate pads and the plurality of second gate lines, respectively. The method of claim 3,
The connection block includes:
A plurality of conductors and a plurality of non-conductors are alternately formed,
Wherein each of the plurality of conductors is arranged so as to be in contact with an extension line and a second gate line corresponding to each other among a plurality of extension lines respectively extending from the plurality of second gate pads and the plurality of second gate lines. The method according to claim 1,
A plurality of data pads formed on the upper surface of the first substrate to correspond to the plurality of first data lines and the plurality of second data lines;
And a connection block disposed between the first substrate and the second substrate and connecting the plurality of data pads and the plurality of second data lines to each other. 6. The method of claim 5,
Wherein a first data line and a second data line overlapping one another among the plurality of first data lines and the plurality of second data lines share one data pad. 6. The method of claim 5,
The connection block includes:
A plurality of conductors and a plurality of nonconductors having a height corresponding to an interval between the first substrate and the second substrate are alternately formed,
Wherein each of the plurality of conductors is arranged to be in contact with a first data line and a second data line overlapping each other among a plurality of first data lines and a plurality of second data lines each extending from the plurality of data pads Liquid crystal display device. The method according to claim 1,
A first protective layer formed on the entire upper surface of the first substrate including the first transistor array;
A plurality of first pixel regions respectively corresponding to the plurality of first pixels and a plurality of second pixel regions respectively corresponding to the plurality of second pixels, A color filter layer that emits light in a wavelength region corresponding to each of the plurality of first pixels and the plurality of second pixels;
An overcoat layer formed flat on the entire surface of the first protective layer including the color filter layer;
A plurality of contact holes formed in the first passivation layer and the overcoat layer respectively corresponding to a partial region of the plurality of first transistors;
A plurality of first pixel electrodes respectively formed in the plurality of first pixel regions on the overcoat layer and connected to the plurality of first transistors through the plurality of contact holes;
A plurality of first common electrodes formed on the plurality of first pixel regions on the overcoat layer so as to be alternated with the plurality of first pixel electrodes;
A second protective layer formed on the entire rear surface of the second substrate including the second transistor array;
A plurality of second pixel electrodes respectively formed in the plurality of second pixel regions on the second passivation layer and connected to the plurality of second transistors, respectively; And
Further comprising a plurality of second common electrodes formed in the plurality of second pixel regions on the second protective layer so as to be alternated with the plurality of second pixel electrodes. The method according to claim 1,
A first protective layer formed on the entire upper surface of the first substrate including the first transistor array;
A second protective layer formed on the entire rear surface of the second substrate including the second transistor array;
A plurality of first pixel regions respectively corresponding to the plurality of first pixels and a plurality of second pixel regions respectively corresponding to the plurality of second pixels, A color filter layer that emits light in a wavelength region corresponding to each of the plurality of first pixels and the plurality of second pixels;
An overcoat layer formed flat on the entire surface of the second protective layer including the color filter layer;
A plurality of contact holes formed in the second passivation layer and the overcoat layer respectively corresponding to a part of the plurality of second transistors;
A plurality of first pixel electrodes respectively formed in the plurality of first pixel regions on the first passivation layer and connected to the plurality of first transistors, respectively;
A plurality of first common electrodes formed in the plurality of first pixel regions on the first protective layer so as to be alternated with the plurality of second pixel electrodes;
A plurality of second pixel electrodes respectively formed in the plurality of second pixel regions on the overcoat layer and connected to the plurality of second transistors through the plurality of contact holes; And
And a plurality of second common electrodes formed on the plurality of second pixel regions on the overcoat layer so as to be alternated with the plurality of second pixel electrodes.

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