KR101667772B1 - Translation look-aside buffer with prefetching - Google Patents

Abstract

The system TLB accepts conversion prefetch requests from initiators. Misses generate external conversion requests on the worker port. The state of the TLB as well as the attributes of the request, such as ID, address, and class, affect the assignment policy of transformations within multiple levels of translation tables. Conversion tables are implemented in SRAM and organized into groups.

Description

[0001] TRANSLATION LOOK-ASIDE BUFFER WITH PREFETCHING [0002]

Related Applications

Further, the present application is related to US generic patent applications ___ (ART-024US1), filed as ___ and entitled SYSTEM TRANSLATION LOOK-ASIDE BUFFER WITH REQUEST-BASED ALLOCATION AND PREFETCHING, United States Patent Application Serial No. ______ (ART-024US2), entitled SYSTEM TRANSLATION LOOK-ASIDE BUFFER INTEGRATED IN INTERCONNECT, entitled " DMA ENGINE WITH STLB PREFETCH CAPABILITIES AND TETHERED PREFETCHING " (ART-024US3), filed as " STLB PREFETCHING FOR A MULTI-DIMENSION ENGINE ", each of which is assigned to the assignee of the present application, Which is incorporated herein by reference.

Technical field

The invention disclosed herein is in the field of computer system design, particularly system-on-chip semiconductor devices.

Memory Management Units (MMUs) are typically used in microprocessors to provide virtual memory capabilities. When virtual memory is enabled, software running on the processor only observes and uses virtual addresses (VA). The MMU is tasked to convert the VA into a physical address (PA) that can be used later in and out of the processor. Using virtual memory can give illusion of having more memory than is available, access to a physical memory system with more address bits than is supported by software And protecting the physical memory through altering the access rights. ≪ Desc / Clms Page number 2 >

Some modern systems that support virtualization have two levels of address translation between VAs and PAs. The first level is similar to that found on a non-virtualized system, but PA is not the final PA. This may be referred to as an Intermediate Physical Address (IPA) or a Guest Physical Address (GPA). The second level maps the intermediate address to the final PA. In such systems, for any software running on the processor, the first level or the second level, or both, may be enabled.

Generally, the virtual address space is divided into pages. Pages are usually several kilobytes, but other page sizes can be used. Systems often support multiple page sizes of several kilobytes to several megabytes or even gigabytes to increase conversion efficiency. All addresses in a page are converted in the same manner, and all access right information is the same. Conversions between VAs and PAs are made through (often multi-level) page tables. The process that proceeds through the page table to convert VA to PA is often referred to as walking, since this process includes a sequence of page table lookups.

The MMU often includes two parts. The first part is referred to as a translation look-aside buffer (TLB). The first part caches the transformations so that the transformations are very quickly accessible to the processor so that for the cached transformations, the processor can be executed with little delay. The second part is a walker that walks the page tables when the TLB does not contain a translation. In some systems, there is more caching between the TLB and the worker. For example, the TLB has two levels of caching. A worker can itself include a cache.

The system MMU (SMMU) mirrors the functionality of the MMU, but applies to initiators other than microprocessors. Some such initiators are GPUs, DSPs, and DMA engines. In the case of SMMU, these initiators can take advantage of the benefits of virtual memory and virtualization. Similar to the MMU, the SMMU operates on pages and calculates transformations using page tables. In some cases, the SMMU uses the same page table formats as the MMU of the processor to which the initiator of the SMMU is connected. In that case, the page table can be shared between MMU and SMMU.

Since the MMU includes a TLB and a worker, the SMMU accordingly includes a system TLB (STLB) and a worker. STLB acts as a cache for transforms to help maintain the peak performance of initiators. In some cases, multiple STLBs may share a single worker for efficiency reasons. In some cases, multiple initiators may share the STLB.

In most cases, the TLBs within the processors are tightly integrated with the processor, which requires physical addresses within the processor (e.g., in the case of caches viewed as cache coherency) . In contrast, STLBs need not be integrated within the initiator. The STLB may be located outside the initiator without any negative impact. In many cases, multiple initiators share a single STLB. The STLB only needs to be between the source and destination of the request to provide transformation services. Most chip designs have interconnects that provide access by initiators to targets. The STLBs may be located between the initiators and the interconnect, or within the interconnect, near the initiators.

Adding virtual memory to the initiator may have serious negative impacts on the initiator's performance. In addition to increasing the latency due to excessive logic, whenever the STLB misses (i.e., the translation required to process requests from the initiator will not be cached), the translation is resolved by another level or work in the cache , The request must be stalled. This will affect the performance of the request and may also affect subsequent requests. Since the one page table walk typically takes 1 to 20 sequential accesses and each access typically takes between 10 and 100 clock cycles, the initiator request can be stopped for a large amount of time, The performance of the reader can be significantly degraded.

Reducing STLB misses can be done by increasing the size of the STLB cache and by reducing the work delay. However, this is insufficient. Some misses are compulsory misses (e.g., when the page is first seen and the cache is not likely to already contain the translation), and they are not improved by cache size. In some dramatic examples, a large amount of data with bad page locality is requested by the initiator to trigger a number of mandatory misses.

There is thus a need for a mechanism for prefetching transformations into the STLB so that the probability of a missed request in the STLB is reduced or eliminated. This is particularly applicable to system TLBs because it tends to have predictable memory access patterns so that it can also be enhanced to generate advanced prefetch patterns that predict future memory access patterns in most cases Because.

Each STLB has a target-side interface that makes memory requests using a protocol. Different I / O devices require different protocols. This makes the design of the different STLBs inconsistent and thus more complex. Address decoding involving redundant logic that utilizes the silicon region and limits the operating speed is performed in the STLB and on the interconnect. The interface protocol for transporting requests from STLBs to their workers is different from the protocol used to transport requests from initiators to targets within the interconnect. This increases the complexity of verification and system level modeling. In addition, when using subsystem interconnects to integrate separately designed logic blocks, there is no way to transfer the translation information and translation prefetch requests from the initiators to the TLBs via the interconnect. In addition, multiple STLBs accessing shared transforms also have no benefit from the shared localization of their requests.

Some I / O devices, such as some microprocessors, perform prefetch operations to cause data to move from a backing store to a cache so that potential future requests may miss in the cache, It will hit without doing it. Prefetching generally sacrifices auxiliary storage bandwidth for the benefit of lower average memory access latency.

In a system with TBL, any access may cause a miss in the TLB translation table. Although less frequent than cache misses in most operating conditions, TLB misses can still cause significantly longer delays than normal cache misses.

In many data processing applications it is common to access data sets in a manner that does not follow their memory organization. In particular, two-dimensional arrays are typically placed in memory such that accesses along one of the two dimensions are sequential in memory. However, accessing that same array along a different dimension requires non-sequential accesses to the memory. The fields in which this type of access occurs include video and image capture and display, 2D processing, as well as other fields with matrix-based data processing. To represent an array having two or more dimensions (e.g., a 2D surface) in a system having memory organized as a linear address space, the address space is divided into converted pages and the array dimensions are divided into pages If not much smaller than the size, certain serious performance-inhibition problems arise. Every individual data element or atomic unit (e.g., pixel) of the surface data will access different pages in either the read or write phase of rotation. This, at least, causes a flurry of STLB misses at the beginning of the surface. If the number of rows being accessed exceeds the number of mappings in the STLB cache, every pixel on the entire surface will cause an STLB miss.

The present invention is a mechanism for prefetching transformations into the STLB such that the probability of a missed request in the STLB is reduced or eliminated. Requests are entered into the STLB. The request may be a normal request (data read or write) or prefetch. Prefetch is a request that does not cause data to be transferred between the initiator and the target. Prefetch causes the STLB to request a read of the translation from the page table prior to a time when translation is likely to be requested.

Note that STLB prefetch is different from CPU prefetch. CPU prefetch is typically initiated by a specific instruction. CPU prefetch moves data from memory to CPU data or instruction cache to improve the probability of CPU reads hitting in the cache. STLB prefetch moves the mapping from a page table in memory to an STLB translation table that acts as a cache to improve the probability of initiator transaction request address translation hitting in the STLB translation cache. It should be understood that the remainder of this disclosure relates to STLB prefetches, and the term prefetch refers to what has already been mentioned above.

The disclosed invention is an improved STLB and a system including the same. The STLB is located close to the I / O devices in the interconnect. It uses a generic interface on the initiator side and the target side to be reusable between the I / O devices of different interface protocols. It is connected to the shared walker using a universal transport protocol over the data path transport topology.

The disclosed invention allows transform assignment information and transform prefetch commands to be transmitted from initiators to interconnected SLTBs located on the target side of the interconnect. In addition, multiple STLBs may use a shared mid-level translation cache to take advantage of the localization of requests between different I / O devices.

The invention disclosed herein is an efficient system for initiating TLB transform prefetches for I / O devices. This can provide a significant reduction in the average memory access latency. The present invention is employed in a DMA engine connected to a TLB. A DMA engine is any device other than a central processing unit that moves blocks of data from memory, into memory, or both. DMA engines can be connected to I / O interfaces, integrated within processing engines, stand alone, or otherwise integrated into chips.

Prefetching occurs as a result of requests being sent with certain VAs. The key to the effectiveness of prefetching is the function of the prefetch virtual address generator in the DMA engine.

The disclosed invention is a multidimensional engine that can be connected to memory via SMMUs with STLBs. The multidimensional engine accesses data for surfaces or other types of data arrays. It can access data in a non-linear manner. The multidimensional engine sends requests for translations of addresses in pages prior to subsequent requests for accessing data elements within the page, thereby causing a stop for conversion fetching when a data element access request is sent minimizing or avoiding stalling. Requests for such data-less transforms are known as STLB prefetch requests. The multi-dimensional engine accesses groups of data elements that use only a number of mappings that can be included in the capacity of the STLB, thereby reducing the total number of translation cache misses.

Figure 1 illustrates a simple STLB in accordance with various aspects of the present invention.
Figure 2 illustrates an STLB with allocation logic in accordance with various aspects of the present invention.
Figure 3 illustrates an STLB that performs clear pre-fetching in accordance with various aspects of the present invention.
Figure 4 illustrates an SMMU that includes an STLB and a walker in accordance with various aspects of the present invention.
Figure 5 illustrates a conventional system of system TLBs and interconnects in accordance with the present invention.
Figure 6 illustrates an interconnect in which system TLBs are integrated into initiator network interface units in accordance with the present invention.
Figure 7 illustrates a system of two interconnects in which translation requests of one interconnect are supported by system TLBs integrated into another interconnect in accordance with the present invention.
Figure 8 illustrates system TLBs sharing an intermediate-level translation cache in accordance with the present invention.
Figure 9 illustrates a simulation environment for an interconnect in accordance with the present invention.
10 illustrates a system of a DMA engine having a virtual address generator, STLB, and target, in accordance with the present invention.
11 illustrates a system of DMA engines having normal and prefetch virtual address generators, STLBs, and targets in accordance with the present invention.
12 illustrates a process for generating a pre-fetch virtual address stream and a normal virtual address stream.
13 illustrates the rotation of one surface.
Figure 14 shows the correspondence of the addresses of the data in the rotated line.
15 illustrates reading groups of pixels from a source and writing them to a destination.
Figure 16 shows the mapping of the rows of surfaces to memory pages.
Figure 17 illustrates the arrangement of a rotating engine, SMMU, and memory.
Figure 18 illustrates another such arrangement with separate channels for data requests and prefetch requests.
Figure 19 illustrates two possible arrangements of address generators in a rotation engine.
Figure 20 shows an application of a prefetch window of an access area having lines spread over different pages.

Referring now to FIG. 1, STLB 100 receives input requests over input port 110, translates addresses, and sends one or more corresponding output requests through output port 120. The requests may include portions of the request associated with the conversion, including but not limited to address, operation (read / write), size, security indication, privilege level and general purpose sideband information Lt; / RTI > With these parts, the context logic creates at least a combination of context identifier and address looked up in translation table 160. [

The translation table 160 includes one or more entries, each of which corresponds to a range of addresses and a set of contexts. When the input request address and the context match the entry, the translation table returns a number of parameters including the translated address and permissions. The translation table 160 may be implemented in a number of ways, e.g., in the form of a CAM (Content-Addressable Memory) that is fully associative or set-related. According to some aspects, the STLB 100 may be configured to have a lower number of entries but a lower latency translation table first, then a higher number of entries, but a multi-level And a conversion table of a plurality of levels arranged in a manner of a cache.

Based on the results of the context lookup performed in the context logic 150 and the translation table lookup in the translation table 160, the control logic 170 takes one of the following actions:

A) If the context logic 150 using information from the request and some internal configuration state determines that the request does not require a transformation, it is allowed to pass through with no or only a few modifications, The table 160 is not interrogated.

B) If the lookup hits in the translation table 160 and the permission is valid, the request is translated. At least the address field is modified to use the translated address. Typically, the most significant bits are replaced by the translated address obtained from the translation table 160, where the number of bits is derived from the page size corresponding to the entry in the translation table 160. In some cases, other attributes of the request are also modified.

C) If the authorization fails, the request is not allowed to proceed or is marked as error.

D) If the lookup misses in the translation table 160 (i.e., there is no corresponding entry), the STLB 100 places an external translation request through the worker port 130 and the same worker port 130 , The request is not processed. While the external conversion request pending, the original request is stalled in STLB 100. [ This stops all traffic going through the STLB 100. Some STLBs have a buffer 180 that is used to temporarily store missed requests in the TLB. This may be a Hit-Under-Miss (HUM) and / or a Miss-Under-Miss (MUM) because it allows subsequent requests to keep progress through the STLB 100 (until the buffer 180 is full) ) Buffer. After the external conversion request via the worker port 130 receives the response, the suspended request is converted and processed according to A), B), or C).

When an external translation request is sent through the worker port 130, a new translation is added to the translation table 160 when the response comes back. There are a number of different types of algorithms that can be used to select the entry to put a new transform (and discard the previously saved transform). This includes in particular common cache allocation replacement policies such as Least Recently Used (LRU), Pseudo-LRU, Not-recently-Used (NRU), and First-In-First-Out (FIFO).

According to some aspects of the present invention, external conversion requests include one type. This type indicates whether the external conversion request was initiated in response to a normal input request or in response to a prefetch request. According to some aspects of the invention, this type is in-band encoded within the protocol of the worker port 130. [ According to other aspects of the invention, this type is represented by a sideband signal.

According to some aspects of the invention, the conversion table 160 is fully related. According to some aspects of the invention, the conversion table 160 is set-related. According to some aspects of the present invention, the conversion table 160 is constructed with a plurality of levels of conversion tables. According to some aspects of the present invention, the conversion table 160 is constructed with a first-level fully associated conversion table and a second-level fully-associated or set-associated conversion table. According to some aspects of the present invention, portions of the translation table 160 are constructed with one or more static random access memory (SRAM) arrays.

Referring now to FIG. 2, in accordance with the present invention, allocation logic 261 determines, based on a replacement policy, whether an entry should be allocated for a request in translation table 160 and, if so, Some features of the request derived from the input port 110 are used to determine if an entry should be used. According to some aspects of the present invention, the replacement policy can be changed on the fly. According to another aspect of the invention, the replacement policy is selected per transaction, as indicated by the transaction request.

According to some aspects of the invention, the conversion table 160 is set related and subdivided into a plurality of groups, where each group includes one or more ways. According to some aspects of the invention, the groups are only one entry. According to other aspects of the invention, the groups are relatively larger and stored in SRAMs.

According to some aspects of the present invention, the attributes of the incoming request from the input port 110 are used to determine the groups to which the request will assign the entry. These attributes include the source of the request, the identifier (ID) of the request (often referred to as a tag), or special sidebands dedicated to allocation, or any combination thereof.

According to some aspects of the invention, allocation logic 261 includes a configurable or programmable register array that is used to determine allowable allocation groups based on attributes of the request used for the determination. The configurable array is set up at system hardware design time. The programmable array is set up by software and can be changed during chip operation.

According to some aspects of the invention, the classes of requests are determined using attributes of the requests. According to some aspects of the invention, a class assigns a maximum number of entries to the translation table 160. According to some aspects of the present invention, a class assigns a minimum number of entries to the translation table 160.

According to some aspects of the invention, when the number of pending requests to a worker (through the worker port 130) is limited, the pending request entries are assigned to groups of multiple entries that are regulated and used classwise. An external conversion request made while reaching the limit on the number of pending requests causes the external conversion request to be temporarily blocked until the response returns the number of pending external conversion requests below the threshold again. According to other aspects of the present invention, the threshold is applied to all pending external conversion requests of a type that are the result of a prefetch input request. According to other aspects of the invention, the threshold is applied to the entire group of pending external conversion requests. According to other aspects of the invention, the threshold applies to all pending external conversion requests of a particular class.

According to an aspect of the invention, when the number of pending requests to the worker reaches the limit, requests resulting from the prefetches are temporarily blocked until the number of pending requests becomes less than the limit. According to another aspect of the invention, when the number of pending requests to the worker reaches a limit, requests resulting from prefetches are discarded.

Referring now to FIG. 3, additional functions support explicit prefetching. According to an aspect of the invention, prefetch identification logic 355 identifies prefetch requests. Prefetch requests are identified using various attributes. According to some aspects of the present invention, prefetch requests are identified using the transmitted sideband signal also through input port 310 with requests. According to other aspects of the present invention, prefetch requests are identified using the identity of the request. According to other aspects of the invention, the prefetch requests are identified using the address bits of the requests. Other fields or a combination of fields are used to identify prefetch requests. According to other aspects of the invention, the prefetch requests have a dedicated prefetch port separate from the input port 310. [

According to some aspects of the present invention, prefetch requests are legitimately formed in use in accordance with standard transaction protocols. Some standard transaction protocols are AMBA (Advanced Microcontroller Bus Architecture) AXI (Advanced Extensible Interface) and OCP (Open Cores Protocol). According to some aspects of the invention, the normal requests are for a full cache line, while the prefetch requests are for a small amount of data, such as zero bytes or one byte. A 0 byte request is illegal according to some protocols, but can be used as an indication of prefetch. A one-byte request is legal according to most protocols and can be used as a prefetch size. A one-byte request (the byte is the minimum atomic unit of the data request) indicates that the requested data does not exceed the defined address ranges of the access restrictions or any boundaries between the cadences, e.g., It will have the advantage of ensuring that it will not. In addition, a one byte request requires exactly one cycle of data transfer on the interface. Alternatively, input requests can be forced to page align, such as by discarding lower address bits. According to some aspects of the invention, prefetch requests must not contain any data. According to some aspects of the present invention, the prefetch request must be aligned to a specific boundary, such as 4 KB. According to other aspects of the invention, prefetch requests take special forms that are not anticipated by the protocol. According to some aspects of the present invention, the prefetch request ID must differ from the IDs of normal requests. According to some aspects of the invention, pending prefetch requests must all have different IDs. According to some aspects of the present invention, the prefetch identification logic 355 is incorporated into the context logic 350.

According to some aspects of the present invention, prefetch requests are also sent to the worker through port 330 as well. According to some aspects of the present invention, the request protocol used on this port 330 includes a prefetch indication that causes the walker to behave differently in certain cases. According to some aspects of the invention, when a request is identified as a prefetch request, it is considered speculative by the worker and no side effects, such as interrupts, are triggered. According to some aspects of the invention, the response protocol on port 330 includes an indication that the walker would normally have triggered side effects if the request was not prefetch. According to some aspects of the invention, this response indication is used in STLB 300 to not add a corresponding entry to translation table 360 or prefetch table 390. According to other aspects of the present invention, this response indication may include a translation table (e.g., a translation table) such that when a non-prefetch request matches this entry, a new request is sent to the worker through port 330 having a disabled prefetch indication 360 or in the prefetch table 390 to mark the entry specifically.

According to some aspects of the present invention, prefetch table 390 is used to store pending prefetch requests. According to some aspects of the present invention, the prefetch table 390 may include prefetch requests that were not sent to the worker. According to other aspects of the present invention, the prefetch table 390 may include prefetch requests that have been transmitted to the worker through port 330. According to other aspects of the present invention, the prefetch table 390 may include prefetch requests that have been sent to the worker through port 330 and received a response through the worker through port 330. According to some aspects of the present invention, when a response to the prefetch request is received by the STLB 300, a translation transformation is assigned to the translation table 360.

In addition to the four possible operations described in FIG. 1 for the control logic 170 (A, B, C, D), according to various aspects of the present invention, the control logic 370 may also be implemented as a prefetch request And to send the identified request to prefetch request termination logic 395. [ According to some aspects of the present invention, the prefetch request termination logic 395 automatically responds to the prefetch requests without sending prefetch requests over the port 320. According to some aspects of the present invention, the prefetch request termination logic 395 is operable only after the prefetch requests have received a response from the walker (via the communication through port 330) Lt; / RTI > The prefetch requests hitting in the translation table 360 are immediately responded by the prefetch request termination logic 395. According to some aspects of the present invention, the prefetch request termination logic 395 responds directly to prefetch requests that match the page of the pending prefetch request. Thus, the agent using the STLB 300 connected through the input port 310 continues to be aware of the number of pending prefetch requests and is likely to have a greater number of prefetch requests than can be tracked by the STLB 300. [ Ensuring that no fetch requests are sent. According to some aspects of the present invention, when a prefetch request is received but the prefetch table 390 does not have an available entry, the prefetch request does not trigger a request to the worker through port 330, And is immediately answered by prefetch request termination logic 395. [ According to some aspects of the present invention, when a prefetch request is received but the prefetch table 390 does not have an available entry, the prefetch request is made when a space is available in the prefetch table 390 . According to some aspects of the present invention, the selection between the above two behaviors (ignore, stop) is made by the indication in the prefetch request. According to other aspects of the invention, the selection is made by a configurable bit.

According to some aspects of the present invention, the STLB 300 includes allocation logic as described in FIG. The assignment of the prefetch table 390 includes a plurality of entries or groups regulated by the class. In addition, the prefetch indication is also used to determine the allowable allocation groups in the translation table 360 and the prefetch table 390.

According to some aspects of the invention, when the number of pending requests to the worker (through port 330) is limited, the pending request entries are assigned to a number of entries or groups that are regulated and used by the class, The prefetch indication of the request on the requestor 310 is used in determining the group or class.

According to some aspects of the invention, a separate port is provided for prefetch requests. In this case, the prefetch request need not be distinguished from the normal requests. However, according to some aspects, they are still required to be specific ID, size, and alignment.

According to some aspects of the present invention, the STLB 300 includes logic to automatically generate pre-fetches based on the patterns observed at the input port 310. According to some aspects of the present invention, automatic pre-fetching automatically pre-fetches pages following (based on page size including current page size, programmed page size, or minimum page size). According to some aspects of the invention, the automatic pre-fetching logic detects strides or two-dimensional accesses and the prefetch accordingly. While other common prefetching techniques may be used, they are adapted to page-granularity and avoid performing multiple automatic pre-fetches on the same page. According to some aspects of the present invention, the prefetches sent to the worker through port 330, which are incoming from the automatic prefetching logic, may be used to prevent guessing based on speculation to prevent a walker from enabling side effects of a work such as interrupts Display.

Referring now to FIG. 4, in accordance with some aspects of the present invention, an STLB 100 is included in an SMMU 400. The STLB 100 is coupled to the walker 410. The worker 410 receives external conversion requests from the STLB 100 and provides responses through the worker port 130. The STLB 100 and the worker 410 share the output port 120.

An interconnect 5100 with STLBs is shown in FIG. Interconnect 5100 includes initiator network interface unit ports 5110 and 5120, a central interconnection network 5140, and target ports 5150. Initiator network interface port 5110 uses the AXI protocol and initiator network interface port 5120 uses the AHB interface protocol. Initiator IP interfaces are connected to initiator network interface ports 5110 and 5120 through each of STLBs 5112 and 5122. The STLBs 5112 and 5122 are connected to the walker via the walker interface port 5160.

Figure 6 illustrates an interconnect 6200 in accordance with the present invention, including initiator network interface units (network interface units) 6210 and 6220. [ The network interface unit 6210 includes a general-purpose unit 6211 that adapts the initiator AXI transaction interface to an internal general purpose interface protocol. Network interface unit 6220 includes a specific-to-generic unit 6221 that adapts the initiator AHB transaction interface to an internal general purpose interface protocol.

Each of the initiator network interface units 6210 and 6220 further includes a generic to transport (G2T) unit 6212. The G2T unit converts each transaction into one or more transport packets and transmits the transport packets onto a data path transport network 6240 that carries transactions to target network interface unit ports 6250. [

According to an aspect of the present invention, each initiator network interface unit further includes an STLB 6213 arranged between the general-purpose unit and the G2T unit. STLBs 6213 include a generic protocol interface on its initiator side data request interface and on its target side data request interface. Each of the STLBs 5112 and 5122 is adapted to its own separate protocols (AXI for STLB 5112 and AHB for STLB 5122), while STLBs 6213 are the same, . The complexities of protocol adaptation are performed in the specific-general purpose units 6211 and 6221, and thus the general purpose protocol is designed for simplicity. According to some aspects of the invention, the general purpose protocol does not support the complex features of unaligned accesses or complex ordering requirements. Accordingly, the design of the STLB 6213 is greatly simplified. In addition, due to simplification, the logic paths in STLB 6213 are shorter and the latency is lower.

G2T 6212 decodes the transaction addresses to determine a set of one or more target interfaces 6250 to which the transaction is directed. STLB 6213 must also decode its address to look up the translation. According to another aspect of the present invention, unlike that performed in G2T 6212, address decoding is performed in STLB 6213 instead. This provides the advantage of reduced transaction latency.

Naturally, each STLB has a worker interface to send worker requests to the worker 6230. According to another aspect of the present invention, the walker interfaces of the STLBs 6213 are connected to the walker 6230 via the transport network 6260. [ The transport network 6260 utilizes the same transport unit libraries and protocols as the transport network 6240. This not only reduces the amount of required unit level logic design verification, but also reduces the complexity in building a performance estimation simulation model. The library of transport units is:

Serialization adapters to allow trade-offs in bandwidth and wiring within the chip floor plan;

Separate clock trees and clock domain adapters for frequency scaling;

Power adapters to allow power domain management;

Observation probes;

Security filters; And

Other conventional on-chip-interconnect units. In contrast, the interface port 5160 to the worker does not use a standard protocol and thus has a different set of interconnect logic inevitably.

FIG. 7 illustrates interconnect 6200, initiator network interface unit 6210, and STLB 6213 of FIG. 6, in accordance with the teachings of the present invention. Subsystem interconnect 7300 is connected to initiator network interface unit 6210 via its own target network interface unit 7310. [ Subsystem interconnect 7300 includes a plurality of initiator ports 7320 and an internal network 7330.

In accordance with an aspect of the invention, subsystem interconnect 7300 includes units from the same library as interconnect 6200. [ According to some aspects of the present invention, the interface protocol between the target network interface unit 7310 and the initiator network interface unit 6210 is a standard protocol. Some standard protocols are AXI, ACE, and OCP. According to other aspects of the present invention, the protocol between the target network interface unit 7310 and the initiator target interface unit 6210 is a NETWORK ON A CHIP SOCKET PROTOCOL, filed September 25, 2012, Such as the network-on-a-chip socket protocol described in U. S. Patent Application Serial No. 13 / 626,766, incorporated by reference in its entirety. One feature that makes some protocols low-latency protocols is to have a transaction identifier signal that eliminates the need for masters to perform an indirect lookup to associate responses with requests.

According to an aspect of the present invention, TLB allocation information is transmitted by initiators connected to initiator network interface units 7320 and transmitted via subsystem internal network 7330 to target network interface unit 7310 The information is conveyed to the initiator network interface unit 6210 provided to the STLB 6213. [ The STLB 6213 uses the allocation information to perform the allocation policy.

According to some aspects of the present invention, the TLB allocation information is encoded in initiator network interface units 7320, using the ordering of the ID fields of the transaction protocol. According to other aspects of the present invention, the TLB allocation information is encoded into protocol sideband signals carried from the initiator network interface units 7320 to the target network interface unit 7310. According to other aspects of the invention, the TLB allocation information is encoded into network interface unit identifier fields of the transport protocol.

According to some aspects of the present invention, STLB prefetch requests are sent from initiator network interface units 7320 to STLB 6213. [ Prefetch requests are described in US patent application serial no. ______ filed as ____, the title of the invention being SYSTEM TRANSLATION LOOK-ASIDE BUFFER WITH REQUEST-BASED ALLOCATION AND PREFETCHING ART-024US1, Lt; / RTI > Subsystem interconnect 7300 is configured such that prefetch requests are sent or regenerated such that STLB 6213 can identify prefetch requests. According to other aspects of the present invention, initiator network interface units 7320 utilize ordering ID bits to distinguish normal requests from prefetch requests. According to other aspects of the present invention, prefetch requests are represented by sideband signals.

According to an aspect of the present invention, initiator network interface units 7320 are programmable to distinguish between a normal request and a prefetch request.

According to an aspect of the present invention, the TLB allocation information and the prefetch identification information may be transmitted from the initiator network interface units 7320 to unaltered target network interface units 7310 so that any number of Subsystem interconnects 7300 may be cascaded and still provide allocation information to STLB 6213. [

8, in accordance with an aspect of the present invention, STLBs 8400 share an intermediate-level translation cache 8410. In FIG. FIG. 8 shows an initiator 8420 connected to two STLBs 8400. Each of STLBs 8400 is connected to a mid-level translation cache 8410 connected to a worker via a worker interface 8430. Translation requests that are missed in both the STLB 8400 and the intermediate-level translation cache 8410 are forwarded to the worker through port 8430.

Level translation cache 8410 is larger than the caches in the STLBs 8400 and the STLBs 8400 are used to store extra capacities of the mid-level translation caches 8410 Share.

In accordance with an aspect of the present invention, requests received by STLBs 8400 have cross-locality, i.e., different STLBs 8400 require some of the same transforms. The mid-level cache holds these conversions because the conversions are returned by the worker so that the second requesting STLB 8400 instead of causing a delay of the worker request is sent in the mid-level cache 8410 You will be able to find the transformations you need.

According to an aspect of the invention, an initiator 8420 is an initiator having a plurality of interfaces. Initiator 8420 distributes traffic between the ports. This distribution increases the requested bandwidth without increasing the width of the link. According to some aspects of the present invention, the distribution is determined by interleaving of the address range based on some address bits, and the particular address bits or a hash of the address bits are determined by a request, To be used. According to other aspects of the invention, each port is driven by a cache dedicated to a portion of the address space. According to an aspect of the invention, a multiport initiator is a multimedia engine such as a 3D (GPU) engine, a 2D engine, a video engine, an image processing engine, or a signal processing engine.

Traffic from multiple ports of the same engine tends to have good page localization, especially if the distribution of requests among the ports is made based at least in part on interleaving based on low address bits. In this case, long contiguous bursts will be split between the ports, and the STLB latency is significantly reduced by the use of a shared mid-level translation cache.

The simulation environment is presented in FIG. 9 in accordance with various aspects of the present invention. The simulation environment is implemented with computer-executable instructions that are run by a computer. Many types of computers, such as a local computer or a cloud computer, may be used. The simulation starts by invocation of execution of instructions.

In accordance with an aspect of the invention, an interconnect 9510 is simulated within a simulation environment 9520. Interconnect 9510 includes STLB 9530. The same simulation environment can be used for an interconnect without STLB or for an interconnect such as interconnect 9510 that includes a TLB. This avoids the enormous complexity and difficult task required to integrate separate simulation environments for interconnects and separate STLBs.

According to some aspects of the present invention, the simulation environment 9520 includes translators, monitors, various other verification intellectuals, and a scoreboard. This scorecard is designed to support interconnects. The simulation environment including the scoreboard can be reused for interconnects with internal STLBs or interconnects without internal STLBs. The simulation environment is implemented in a register transfer level language such as Verilog or System Verilog.

According to other aspects of the invention, this simulation is a performance simulation. The simulation environment is implemented in system level modeling languages such as SystemC. The common transaction socket modeling protocol is OSCI (Open SystemC Initiative) TLM (Transaction Level Modeling) 2.0 standard.

10 illustrates a system that includes a DMA engine 10110 that sends requests to STLB 10120 where the virtual addresses of requests are translated. Examples of DMA engines include not only I / O-based engines such as Ethernet, wireless, USB, SATA controllers, but also camera image signal processing engines, video engines, 2D and 3D engines, and TCP / And cryptography accelerators. ≪ RTI ID = 0.0 > DMA engine 10110 and STLB 10120 are communicating. DMA engine 10110 includes a virtual address generator 10140 that generates sequences of virtual addresses to be transmitted in requests. According to some aspects of the present invention, DMA engine 10110 and STLB 10120 are directly connected. According to other aspects of the present invention, the DMA engine 10110 and the STLB 10120 are connected through different modules. Supplemental storage requests are made to interconnect 10130. Alternatively, a target such as a next-level cache or a secondary storage DRAM controller may be an alternative to interconnect 10130.

STLB 10120 may cache the address translations and send translation requests for translations that are not in cache via worker interface 10160. Alternatively, the walker can be integrated with STLB to make it a complete SMMU. In this case, the conversion table memory interface will be connected instead of the worker interface 10160. In this case, alternatively, the worker interface 10160 may not be present and the page table memory requests will be sent directly to the interconnect 10130.

STLB 10120 adds a modest latency to all requests sent by DMA engine 10110 as a result of logic to perform translation look-ups and address translation. However, when the request misses at STLB 10120 (i.e., when the page translation corresponding to the virtual address is not present in the translation cache), STLB 10120 issues a long process (lengthy) to retrieve the translation from the page table memory process. This causes a significant delay in requests with TLB misses.

Depending on the buffering capabilities of the STLB 10120 and the ordering constraints of the request stream, multiple misses may be processed simultaneously. However, when their buffering capabilities are exhausted, STLB 10120 has to process only one miss at a time, which adds a lot more misses to the request latency.

Simple block-based DMA engines can have good page localization. For example, for a common page size of 4 KB, a simple block-based DMA engine could place 64 consecutive 64B requests. The first request to the page will miss and delay the transmission of the request. However, when the transform is received by the STLB, this transform can be efficiently reused for the following 63 requests. While the first request generates a significant latency penalty, subsequent requests can go fast and, if a conversion is received, cause an overall performance penalty that is significant due to the presence of STLB but does not usually cause crippling. The performance penalty depends on the latency of the conversion retry and the rate of requests.

However, many DMA engines have request patterns with much poorer page localization. For example, a 2D DMA engine that reads the array vertically can send all respective requests to a different page than the previous page. If the number of accessed pages is greater than the number of transformations that can be stored in the TLB, the misses can severely impair performance. When the cache is large enough, when the 2D engine fetches the next column, the pages may still be in its cache, which reduces the penalty.

Within microprocessors, the addresses of requests are not easily computed previously. However, many DMA engines have some dependency between the fetched data and their addresses. These DMA controllers can easily generate an accurate stream of expected requests.

This is used naturally by decoupling the virtual address generator from the data buffer management so that the virtual address generator is limited only when the data management is exhausting the space or when the number of outstanding requests supported is reached. This property can be used to reduce the performance penalty of STLB misses.

11 shows a system that includes a DMA engine 11210 connected to STLB 11220 connected to a target 10130. Fig. DMA engine 11210 generates two virtual address streams. One virtual address stream is the normal virtual address stream generated by the normal virtual address generator 11240. The other virtual address stream is a stream of prefetch virtual addresses generated by prefetch virtual address generator 11250, similar to but preceded by a virtual address stream generated by normal virtual address generator 11240.

According to some aspects of the present invention, prefetch virtual address generator 11250 is identical to normal virtual address generator 11240. According to some aspects of the present invention, the prefetch virtual address generator 11250 shares some logic with the normal virtual address generator 11240. Some types of possible sharing logic are part of the configuration registers and state machines.

According to some aspects of the present invention, prefetch virtual address generator 11250 sends a prefetch request corresponding to each normal request to be subsequently transmitted by normal virtual address generator 11240. [ According to other aspects of the present invention, prefetch virtual address generator 11250 avoids requesting prefetches through redundant contiguous virtual addresses in the range of pages that were accessed in a previous or recent request. One way to do so is to define a derived stream of prefetches in only one request address that corresponds to a particular address within a page. Usually, this can be the first address in a page.

According to some aspects of the present invention, prefetch requests are legitimately formed in use in accordance with standard transaction protocols. Some standard transaction protocols are AMBA (Advanced Microcontroller Bus Architecture) AXI (Advanced Extensible Interface) and OCP (Open Cores Protocol). According to some aspects of the invention, the normal requests are for the entire cache line, while the prefetch requests are for a small amount of data, such as zero bytes or one byte. A 0 byte request is illegal according to some protocols, but can be used as an indication of prefetch. A one-byte request is legal according to most protocols and can be used as a prefetch size. A one-byte request (where the byte is the minimum atomic unit of the data request) indicates that the requested data is within the defined bounds of access constraints or ranges bounded by any boundaries between the cadences, e.g., page size It will have the advantage of ensuring that it will not be. In addition, a one-byte request requires exactly one cycle of transfer of data on the interface. Alternatively, input requests can be forced to page align, such as by discarding lower address bits. According to some aspects of the invention, prefetch requests must not contain any data. According to some aspects of the present invention, the prefetch request must be aligned to a specific boundary, such as 4 KB. According to other aspects of the present invention, prefetch requests take special forms that are not expected by the protocol. According to some aspects of the present invention, the prefetch request ID must differ from the IDs of normal requests. According to some aspects of the invention, pending prefetch requests must all have different IDs. According to some aspects of the invention, the STLB interface limits the number of pending prefetch requests to a specific number. The number of pending prefetch requests is dynamic, which means that it can be changed in the fabricated chip, such as by software programming the number or by software selecting from a possible number of choices.

In accordance with some aspects of the present invention, STLB 11220 receives both normal and prefetch request streams from DMA engine 11210. [ According to some aspects of the invention, normal requests and prefetch requests are transmitted on different physical or virtual request channels. According to other aspects of the present invention, normal requests and prefetch requests are transmitted on the same channels, and prefetch requests are identifiable by the STLB 11220. [

Essentially, but not all, of the following methods:

By using sideband signals transmitted on each request;

By using the ID of the request;

By using the address bits of the requests;

By using a combination of other fields or fields that are part of the request; And

By using a dedicated prefetch port that is separate from the port used for normal requests

Identifiable.

According to some aspects of the present invention, the pre-fetch virtual address generator 11250 is operable to determine the current state of the normal virtual address generator 11240, the buffer availability in the DMA engine 11210, Lt; RTI ID = 0.0 > 11250 < / RTI >

According to some aspects of the present invention, the pre-fetch virtual address generator 11250 is tiled to the normal virtual address generator 11240 so that only the N virtual addresses < RTI ID = 0.0 >Lt; RTI ID = 0.0 > of < / RTI > Typically, the normal address for calculating this distance is the most recently-generated normal address. According to some aspects of the invention, the tether is based on the filtered pre-fetch virtual address stream such that the pre-fetch virtual address stream only generates virtual addresses that are M filtered virtual addresses before the normal stream (I.e., the prefetch virtual address is not generated if the request meets certain criteria, such as a request with an address in the same page as another recent request). This is useful for controlling the number of new pages requested by the prefetch stream, in order to avoid thrashing the TLB cache with too much prefetching. According to some aspects of the present invention, N and M may be hard coded, dynamically programmable, or may be part of a table of possible values.

According to some aspects of the present invention, STLB 11220 supports allocation policies in its cache and structures. By limiting the tether to N or M to ensure that the allocated resources available at the STLB 11220 are not exceeded, the DMA engine 11210 can take advantage of the available resources and cache or request Ensuring that it does not disturb the behavior of the stream.

According to some aspects of the present invention, STLB 11220 uses responses to prefetch requests as a way to indicate that a cache miss has occurred and that a slot has been taken in the tracking structure within STLB 11220. In particular, if the prefetch request already exists in the translation cache or is already received at the pending virtual address as a miss, the STLB 11220 immediately returns a response. If the prefetch request misses and the worker request for the page is not already pending, STLB 11220 returns a response only when the transformation is returned by the worker. According to some aspects of the present invention, prefetch virtual address generator 11250 can be programmed to ping only P prefetch requests. With prefetch virtual address generator 250, with STLB 11220 returning a response to the misses only after the transformation is obtained, the prefetch virtual address generator 250 sends more requests to the STLB 11220 than it can process And that This avoids backpressure from STLB 11220 or dropping of prefetch requests by STLB 11220 (both undesirable). According to some aspects of the invention, P may be hard-coded, dynamically programmable, or part of a table of possible values.

According to some aspects of the present invention, STLB 11220 also supports assignment policies. Some assignment policies applicable to STLB pre-fetches are the US generic patent application ___ (ART-024US1), filed as ___ and entitled SYSTEM TRANSLATION LOOK-ASIDE BUFFER WITH REQUEST-BASED ALLOCATION AND PREFETCHING, U.S. Provisional Patent Application Serial No. 61/684705 (Attorney Docket No. ART-024PRV), filed on January 18, and entitled SYSTEM TRANSLATION LOOK-ASIDE BUFFER WITH REQUEST-BASED ALLOCATION AND PREFETCHING, Both of which are incorporated herein by reference in their entirety. Using the allocation policy, the DMA engine 11210 may reserve a certain number of entries in the STLB 11220. [ By limiting the number of its significant prefetches to that number, DMA engine 11210 ensures that it does not cause prefetch overflows in STLB 11220 at all.

According to some aspects of the present invention, STLB 11220 supports selectable or programmable allocation policies. Prefetch requests from DMA engine 11210 include an indication of the allocation policy that STLB 11220 should use.

According to some aspects of the present invention, the DMA engine 11210 includes a plurality of normal virtual address generators. The pre-fetch virtual address generator is coupled to a plurality of normal virtual address generators to enable a plurality of normal virtual address generators to take advantage of STLB pre-fetching.

A TLB, such as any cache, has an eviction policy. The eviction policy determines which stored conversions are to be replaced when a new transformation is fetched from the worker. Prefetches can be used to bias this eviction policy. According to an aspect of the invention, the TLB utilizes a least recently used (LRU) replacement policy, and prefetching has the effect of "using" the entry transformation, thereby lowering the probability of the eviction of the transformation.

Reference is now made to the flow chart of FIG. According to an aspect of the invention, the prefetch request stream is tiled. The prefetch request stream is the same as the normal request stream, but precedes it. After the start 12300 of the process of generating virtual address streams, the DMA engine generates a normal virtual address 12310. Next, and based on the normal virtual address 12310, the DMA engine generates a prefetch virtual address 12320. The prefetch virtual address is transferred to STLB 12330 either directly or through an intermediate module. After a short time (ideally, this is the minimum amount of time STLB takes to fetch transitions), the DMA sends a normal virtual address to STLB 12340 either directly or through an intermediate module.

A "use counter" is associated with each conversion entry. The "usage counter" is incremented for each prefetch request and decremented for each normal request. A non-null usage counter prevents an entry from being evicted. Miss prefetch requests require eviction. If the eviction is prevented, the prefetch request is stopped. This mechanism automatically adjusts the length of the tether as a function of the localization of the request flow and the number of entries available in the STLB.

A multidimensional engine, such as a rotating engine, takes a 2D surface and records it with the inverted x-y coordinates. Figure 13 shows an array of surface data in memory. Source surface 13110 has its coordinates reversed to create destination surface 13120.

According to an aspect of the invention, the memory address of each pixel of the surface based on its coordinates is provided by the following formula:

Addr = BASE + y * WIDTH + x * PIX_SIZE

here:

x and y are the coordinates of the pixels in the surface;

BASE is the base address of the surface;

WIDTH is the distance (in bytes) between the beginning of the row and the beginning of the next row; And

PIX_SIZE is the size of one pixel in bytes (typically 2 or 4 bytes).

According to other aspects of the present invention, other formulas describe the arrangement of pixels at memory addresses.

The source surface 13110 and the destination surface 13120 need not have the same parameters (BASE, WIDTH, PIX_SIZE).

The problem with conventional multidimensional engines is that one surface can be stepped through at incremental addresses of contiguous data (potentially at the end of the row), while the other surface has relatively large steps in the addresses It must be stepped through. This is illustrated in FIG. 14, where the mapping of pixel addresses,

Source surface (0) => Destination surface (0)

Source surface 32 = destination surface 4

Source surface 64 = destination surface 8

Source surface 96 => destination surface 12

Source surface 128 => destination surface 16

to be.

The destination surface is written with incremental addresses of contiguous data (where PIX_SIZE = 4 bytes), while the SRC surface is read with large jumps between pixels.

Memories, such as dynamic random access memories (DRAMs), whose surfaces may be shared between the recording agent and the read agent, are inefficient when accessing small units of data. In the example of Fig. 14, the recording of the destination surface can be performed efficiently, but the reading of the source surface can not be performed efficiently.

This traditionally involves two steps:

(1) fetching from the source surfaces in the larger blocks

(2) adding some intermediate storage to the multidimensional engine so that unnecessary data from the large block fetch is held for a sufficient time to still remain in the intermediate storage when the multidimensional engine needs it.

In Fig. 15, the multi-dimensional engine reads from SRCs in groups of adjacent pixels (in this example, two groups). Then, while this engine is used to write directly to the DST, the rest is temporarily stored. The width and height of the blocks may be selected to maximize the use of the DRAM while minimizing the required buffer.

The DRAMs typically behave almost optimally for 64-256 byte bursts, so the rectangular access area may be 16-128 pixels on one side. To reduce buffering, one dimension of the rectangle can be reduced.

Another problem arises when the addresses accessed by the multidimensional engine are virtual addresses.

In a virtual addressing system, the memory consists of pages (the typical size is 4 KB). The mapping of virtual addresses VA to physical addresses PA tends to be irregular so that pixels in adjacent VAs across the page boundary may be far from physically-addressed memory.

Surfaces rotated in chips may exceed 4KB WIDTH with PIX_SIZE of 4B. In the case of 4 KB of virtually addressed page sizes, this means that a single row of pixels within a surface extends beyond one page. As a result, the pixels in the column are not on the same pixel. Even in the case of a WIDTH smaller than the page size, the page localization of the pixels in the column may be low enough to cause significant performance problems due to STLB misses.

16 shows a surface 16410 with a 3200 pixel width and 4B PIX_SIZE. Each row 16420 of the surface uses WIDTH = 3200 * 4B = 12.8kB. For 4KB pages, each row uses 3.125 pages. The pixels in the first column are on pages 0, 3, 6, and so on.

In a virtual memory system, the multidimensional engine is connected to memory via a system memory management unit (SMMU). The SMMU takes the VAs and converts them into PAs suitable for memory.

According to one aspect of the present invention, as shown in Fig. 17, a multidimensional engine 17510 is connected to the memory 17530 through an SMU 17520. Fig. The SMMU 17520 includes a system conversion index buffer (STLB) 17522 and a worker 17524. STLB 17522 is aware of recent VA-PA conversions. Worker 17524 computes or looks up a transformation from the translation table in memory when the translation for the requested VA is not present in STLB 17522. [

Worker 17524 takes more than two to twenty memory accesses to resolve the translation. Two memory accesses are sufficient for small VA space. Due to the excessive virtualization layer, 20 or more memory accesses are required for large VA spaces such as "nested paging" and those that can be represented by 64 bits.

Because of this, the memory access traffic generated by the walker 17524 during the traversal of the surface 410 in the vertical direction far exceeds the traffic for accessing its own pixels, and the duration of stalls due to STLB misses Can drastically lower the throughput. Accordingly, it is important to cache transitions in STLB 17522.

The appropriate number of entries for caching in the STLB is the number of pages that are touched by the vertical traversal of the surface. When the memory used by the rows of pixels exceeds VA page sizes, one entry must be cached for each row in its surface.

Sizing the STLB by the number of entries equal to the height of the access area still raises the following problems:

(A) The flow of rotation readings and writes is interrupted when a row access reaches a new page (often for a long period of time), resulting in a STLB miss.

(B) For well-aligned surfaces such as surfaces where WIDTH is an integer page, STLB misses cause a back-to-back for every row every time a row access reaches a new page . This creates a large burst of traffic from the SMMU worker and delays the pixel traffic for an extended period of time.

According to an aspect of the present invention, a transform prefetching mechanism is used with the STLB to reduce or eliminate delays due to STLB misses. The STLB receives prefetch commands from the multidimensional engine (or other coordinated agent) to trigger the walker to fetch the transformations in the prediction of its near future usage. The walker places a new transform in the STLB so that the STLB is available in advance or at a reduced amount of time after the transformation is requested by the multidimensional engine.

18 shows a multidimensional engine 18610 according to some aspects of the present invention connected to memory 17530 via SMMU 18620. [ Multidimensional engine 18610 performs data requests over physical channel 18640 and makes prefetch requests over physical channel 18650. [ According to other aspects of the present invention, pixel and prefetch requests are transmitted on a shared physical channel and are distinguished by the attributes of the request (e.g., bit or command type or reserved request size).

According to some aspects of the present invention, as shown in Figure 19A, the multidimensional engine 18610 includes an address generator 19720 that generates the addresses needed to access the pixels in memory. Address generator 19720 is duplicated so that each generator is enabled to generate addresses of the same stream, but earlier as prefetch requests on channel 18650 and data on channels 18640 Requests will generate them later.

19B, the multidimensional engine 19710 includes an address generator (not shown) that generates an advanced stream of prefetch requests for addresses, prior to data requests of the same addresses 19730).

According to another aspect of the invention, the pre-fetch generator is constrained to stay within a certain range of addresses of the regular stream.

According to another aspect of the invention, the distance is one page, so that for any row being accessed, the translation for the next page to be encountered can be pre-fetched, but not for subsequent pages.

According to other aspects of the invention, the distance may be set to less than one page or more than one page, depending on the latency and buffering required to cover the working time of the prefetch requests.

Referring now to FIG. 20, in accordance with an aspect of the present invention, surface 20800 has a row of data (row contains 3.125 pages of data). Surface 20800 is accessed eight rows at a time where the sequential accesses are directed to the right directional data. The raw prefetch address stream is accompanied by all the addresses to be accessed by the regular stream, which are then one page-worth of addresses. At certain times, data requests are sent for the data in column 20810. [ The raw prefetch stream is transmitted on the data in the prefetch request column 20820.

The raw stream is filtered to transmit only one prefetch per page. In particular, the addresses are filtered out if they are not perfectly aligned on the page boundary. Thus, the prefetch of the next page is sent immediately after the last data element of the previous page is accessed, and needs to be available for exactly two transforms per row.

At the right edge of surface 20800, the data access column warps from the left edge of the surface 20830 to the beginning of the next group of eight rows. At the time of wrapping, each access will cause a conversion miss. According to another aspect of the invention, prefetch requests of addresses corresponding to the left edge 20830 are sent, despite the fact that some (most) are not perfectly aligned to the page boundary. This corresponds to the start condition for the new access area to be transferred when the data on the start edge of the access area is not aligned to the page boundary.

According to some aspects of the present invention, prefetch traffic is limited such that this traffic does not overwhelm the walker or memory system. That is, the multi-dimensional engine discards or delays the issuance of prefetch requests based on its state. In particular, limitations based on the bandwidth of the prefetch requests, the current number of critical prefetch requests, and the maximum latency are possible.

According to some aspects of the invention, the STLB is sized with a number of transforms equal to twice the height of the fetch access area when the prefetch window is limited to one page of width. This is because the entire prefetch window may only contain two pages (current, next) per row.

According to other aspects of the present invention, the STLB is sized with a number of transforms equal to 1+ (prefetch window width / page size) for the largest page size supported by the system.

These settings are optimal when in a steady state (i.e., when the prefetch window does not touch the edges of the surface). However, when the prefetch window is at the start edge or straddle over the access areas, there is discontinuity in the pages for prefetching because the new access area typically uses completely different pages .

According to some aspects of the invention, the STLB is sized by tripling the fetch height (for the page-width prefetch window) or the fetch height by 2+ (prefetch window size / page size) for other sizes . This allows the prefetch window to cover two different access areas without any interruption in prefetching.

In unaligned cases, the partially used pages to the left of the fetch access area are also used on the previous row to the right of the access area. On a surface with sufficient width, the page will be replaced in the TLB by the time the prefetch window size reaches the right side of the access area, so the page will have to be prefetched again. Increasing the size of the raw prefetch stream filter or adding special logic may make repeating fetching unnecessary.

According to some aspects of the present invention, the STLB may be sized 3 times the fetch height (for the page-width prefetch window) or 2+ (prefetch window size / page size) times the fetch height for other sizes , The TLB is filtered to fix the page entries at the beginning of the access area until it reaches the end of the access area.

As will be apparent to those skilled in the art upon reading this disclosure, each of the aspects described and illustrated herein may be readily separated from the features and aspects to form embodiments without departing from the scope or spirit of the invention Or discrete components and features that can be combined with them. Any of the mentioned methods may be performed in the order of the events mentioned or in any other order possible logically.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Moreover, although any methods and contents similar or equivalent to those described herein can be used in the practice or testing of the present invention, exemplary methods and content are presently exemplary.

All publications and patents cited in this specification are incorporated herein by reference, as if each individual publication or patent was specifically and individually indicated to be incorporated by reference, and that publications are cited Methods and / or systems are incorporated herein by reference for disclosing and describing. The citation of any publication shall be for its commencement prior to the filing date and shall not be construed as admission that the present invention is not entitled to precede such publication by prior invention. In addition, the dates of the publications provided may differ from the actual publication dates, which may need to be individually verified.

Additionally, such equivalents are intended to include both currently known equivalents and equivalents developed in the future, i.e., any elements developed that perform the same function regardless of structure. Accordingly, the scope of the present invention is not intended to be limited to the exemplary embodiments described and illustrated herein.

According to the teachings of the present invention, computers and computing devices are articles of manufacture. Other examples of articles of manufacture include: computer readable program code (e.g., computer program code) for receiving a motherboard, server, mainframe computer or data, transmitting data, storing data, (E. G., A central processing unit, a graphical processing unit, or a microprocessor) configured to execute one or more programs (e. G., Hardware, firmware, and / or software) .

An article of manufacture (e.g., a computer or computing device) includes non-transitory computer readable media or storage that includes a series of instructions, such as computer readable program steps or encoded code therein. In certain aspects of the invention, the non-transitory computer readable medium comprises one or more data stores. Thus, in certain embodiments according to certain aspects of the present invention, the computer readable program code (or code) is encoded into a non-transient computer readable medium of the computing device. As a result, the processor executes the computer readable program code to cause the computer to create or modify an existing computer-aided design using the tool. In other aspects of embodiments, the creation or modification of a computer-aided design is implemented as a web-based software application, wherein portions of the data associated with the computer-aided design or tool or computer readable program code are communicated Received or transmitted.

An article of manufacture or system according to various aspects of the present invention may be implemented on one or more separate processors or microprocessors, volatile and / or non-volatile memory and peripherals or peripheral controllers; Through an integrated microcontroller with a processor, local volatile and non-volatile memory, peripherals and input / output pins; Through separate logic implementing a fixed version of the article of manufacture or system; And programmable logic implementing a version of the article of manufacture or system that can be reprogrammed via a local or remote interface. Such logic may implement the control system through a set of commands executed by logic or by a soft-processor.

Accordingly, the foregoing merely illustrates the various aspects and principles of the present invention. Those skilled in the art will recognize that, while not explicitly described or shown herein, it is possible to implement the principles of the invention and to contemplate various arrangements that fall within the spirit and scope of the invention. In addition, all examples and conditional language mentioned herein are intended to aid the reader in understanding the concepts and inventive principles taught by the inventors, and are incorporated by reference to such specifically recited examples and conditions It is understood that the present invention is not limited thereto. Moreover, all statements herein reciting principles, aspects, and embodiments of the present invention, as well as specific examples thereof, are intended to encompass both structural and functional equivalents thereof. Additionally, such equivalents are intended to include both currently known equivalents and currently developed equivalents and equivalents developed in the future, i.e., any elements developed that perform the same function regardless of structure. Accordingly, the scope of the present invention is not intended to be limited to the various aspects described and discussed herein. Rather, the scope and spirit of the invention is embodied by the appended claims.

Claims (112)

A translation look-aside buffer (TLB)
A translation table storing address translations;
An input port enabled to receive an input request from an initiator; And
And an output port enabled to transmit an output request corresponding to the input request,
If the input request is a prefetch, the output port does not send an output request,
If the input request matches an entry in the translation table, the translation table returns the translated address,
An address field is modified to use the translated address,
At least some bits of the address field being replaced by the translated address obtained from the translation table, and
Wherein the number of bits in the address field replaced by the translated address is derived from a page size corresponding to the entry in the translation table,
System conversion index buffer. The method according to claim 1,
Further comprising a prefetch port dedicated to receive prefetch requests,
System conversion index buffer. The method according to claim 1,
Further comprising a sideband signal indicating whether the input request is a prefetch,
System conversion index buffer. The method according to claim 1,
Wherein the input request includes an ID indicating a value, the value indicating whether the input request is a prefetch,
System conversion index buffer. The method according to claim 1,
The input request including an address, the address indicating whether the input request is a prefetch,
System conversion index buffer. The method according to claim 1,
Wherein the input request is made according to a standard transaction protocol, whether the input request is a prefetch or not,
System conversion index buffer. The method according to claim 1,
Wherein the input request includes a magnitude indicating an amount of data requested by the input request,
The size being indicative of the amount of data that is less than the size of the entire cache line,
System conversion index buffer. 8. The method of claim 7,
Wherein the size is 0,
System conversion index buffer. 8. The method of claim 7,
Wherein the size is one byte,
System conversion index buffer. The method according to claim 1,
The input request may be page aligned,
System conversion index buffer. The method according to claim 1,
Wherein the conversion table is set associative,
System conversion index buffer. 12. The method of claim 11,
Wherein the conversion table comprises a static random access memory array,
System conversion index buffer. The method according to claim 1,
Wherein the conversion table includes a first conversion table and a second conversion table, the first conversion table having a smaller number of entries than the second conversion table,
System conversion index buffer. The method according to claim 1,
Further comprising allocation logic arranged to use a replacement policy,
System conversion index buffer. 15. The method of claim 14,
The replacement policy used may be changed to on the fly,
System conversion index buffer. 15. The method of claim 14,
Wherein the replacement policy for a given request is based on an attribute of the input request,
System conversion index buffer. The method according to claim 1,
Wherein the conversion table comprises a first group and a second group,
System conversion index buffer. 18. The method of claim 17,
Further comprising a configurable register array for determining whether allocation to the first group is allowed.
System conversion index buffer. 18. The method of claim 17,
Further comprising a programmable register array for determining whether allocation to the first group is allowed,
System conversion index buffer. 18. The method of claim 17,
Wherein the attribute of the input request is a value indicating whether the input request is to assign an entry to the first group,
System conversion index buffer. 21. The method of claim 20,
Wherein the attribute is an indication of a source of the input request,
System conversion index buffer. 21. The method of claim 20,
The attribute is an identifier,
System conversion index buffer. 21. The method of claim 20,
Wherein the attribute is a sideband,
System conversion index buffer. The method according to claim 1,
The input request including an input request class;
The conversion table including a plurality of conversion table entries each including an entry class,
System conversion index buffer. 25. The method of claim 24,
If the number of conversion table entries having an entry class matching the input request class exceeds a maximum number, the system conversion index buffer replaces a conversion table entry having an entry class matching the input request class,
System conversion index buffer. 25. The method of claim 24,
If the number of translation table entries with a particular entry class is less than the minimum number, then the translation table entries with that particular entry class are invalid,
System conversion index buffer. The method according to claim 1,
Further comprising a walker port for transmitting external conversion requests,
Wherein the input request comprises an address,
If the translation table indicates a miss, the system translation index buffer transmits an external translation request,
System conversion index buffer. 28. The method of claim 27,
An external conversion request type,
Wherein the external conversion request type indicates whether the input request is a prefetch,
System conversion index buffer. 28. The method of claim 27,
Transmitting the outer translation request is temporarily blocked when the number of pending outer translation requests reaches a threshold,
System conversion index buffer. 28. The method of claim 27,
Transmitting the outer translation request is temporarily blocked when the number of pending outer translation requests due to prefetches reaches a threshold,
System conversion index buffer. 28. The method of claim 27,
Transmitting the external conversion request is discarded when the number of pending external conversion requests due to prefetches reaches a threshold,
System conversion index buffer. 28. The method of claim 27,
Wherein the conversion table comprises a first group and a second group; And
Wherein sending the external conversion request is temporarily blocked when the number of pending external conversion requests for the first group reaches a threshold,
System conversion index buffer. 28. The method of claim 27,
The input request including a class;
The class being associated with the external conversion request; And
Wherein sending the external conversion request is temporarily blocked when the number of pending external conversion requests of the class reaches a threshold,
System conversion index buffer. As a system memory management unit,
A walker;
System conversion index buffer,
The system translation index buffer comprising:
A translation table storing address translations;
An input port enabled to receive an input request from an initiator, the input request comprising an address; if the translation table indicates a miss, the buffer transmits an external translation request; And
An output port enabled to transmit an output request corresponding to the input request, the output port not transmitting an output request if the input request is prefetch;
If the input request matches an entry in the translation table, the translation table returns the translated address,
An address field is modified to use the translated address,
At least some bits of the address field being replaced by the translated address obtained from the translation table, and
Wherein the number of bits in the address field replaced by the translated address is derived from a page size corresponding to the entry in the translation table,
Wherein the system translation index buffer is coupled to the worker,
System memory management unit. 35. The method of claim 34,
Further comprising an external conversion request type indicating whether the input request is a prefetch,
System memory management unit. 36. The method of claim 35,
Wherein when the external request type indicates that the input request is a prefetch, the system memory management unit is prohibited from generating side effects,
System memory management unit. As an interconnect,
Initiator;
target;
Walker;
System conversion index buffer; And
A worker port for transmitting external conversion requests; transmitting said external conversion request is discarded when the number of pending external conversion requests due to prefetches reaches a limit value;
Lt; / RTI >
The system translation index buffer comprising:
A translation table storing address translations;
An input port enabled to receive an input request from an initiator, the input request comprising an address; if the translation table indicates a miss, the buffer transmits an external translation request; And
An output port enabled to transmit an output request corresponding to the input request, the output port not transmitting an output request if the input request is prefetch;
If the input request matches an entry in the translation table, the translation table returns the translated address,
An address field is modified to use the translated address,
At least some bits of the address field being replaced by the translated address obtained from the translation table,
Wherein the number of bits in the address field replaced by the translated address is derived from a page size corresponding to the entry in the translation table,
Wherein the input port of the system conversion index buffer is accessible by the initiator and the target is accessible by the output port of the system conversion index buffer and the worker is connected to the worker port of the system conversion index buffer Accessible by,
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