KR101629614B1 - Touch sensing driving circuit for time division driving type - Google Patents

Abstract

The present invention relates to a touch sensing driver circuit in which a source driver IC for displaying an image during a pixel driving period is operated and a readout IC for sensing a touch input during a touch sensor driving period is operated, A first driving power source control unit 400 for controlling a driving power source applied to the readout IC based on a time-division synchronous signal Tsync for discriminating a time-division synchronous signal Tsync for discriminating the time-division synchronous signal Tsync. And a second driving power supply control unit 80 for controlling the driving power applied to the source driver IC based on the EPI interface signals SHD and WUC.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a TOUCH sensing driving circuit,

The present invention relates to a time-division driving type touch sensing driving circuit.

A user interface (UI) enables a person (user) to easily control various electronic devices as he / she wants. Representative examples of such a user interface include a keypad, a keyboard, a mouse, an on screen display (OSD), a remote controller having infrared communication or radio frequency (RF) communication function, and the like. User interface technology has been developed to enhance the user's sensibility and ease of operation. Recently, the user interface has evolved into a touch UI, a voice recognition UI, a 3D UI, and the like.

The touch UI is essential for portable information devices. The touch UI is implemented by a method of forming a touch screen on the screen of a display element. Such a touch screen can be implemented in a capacitive manner. A touch screen having a capacitive touch sensor senses touch input by sensing a capacitance change, i.e., a charge variation of a touch sensor when a finger or a conductive material contacts the touch sensor.

A touch sensing driver circuit having a display device having a touch screen integrated therein senses a change in capacitance value of a touch sensor before and after a touch (or proximity) to judge whether or not the conductive material is in contact (or proximity) and its position. 1 frame period in the touch sensing driving circuit can be time-divided into a pixel driving period P1 in which data of the input image is written to the pixels of the display element and a touch sensor driving period P2 in which the touch sensors are driven have.

In this time-division-driven touch sensing driving circuit, there is a problem that power consumption is increased due to power consumption in an unused circuit block in each driving period (P1, P2).

The touch sensing driver circuit of the time division driving type is provided with a source driver integrated circuit (IC) which normally operates only during the pixel driving period P1 and a driver IC which operates normally only during the touch sensor driving period P2. Read-out < RTI ID = 0.0 > IC. ≪ / RTI > The source driver IC does not need to operate during the touch sensor driving period P2 and therefore is not used during this period P2. On the other hand, the lead-out IC does not need to operate during the pixel driving period P1 and therefore is not used during this period P1.

Meanwhile, when the touch sensing driving circuit is in operation, driving power is continuously supplied to each of the source driver IC and the lead-out IC. Therefore, an unnecessary current flows in the lead-out IC that is not used during the pixel driving period P1 and an unnecessary current flows in the unused source driver IC during the touch sensor driving period P2, thereby increasing the power consumption.

Accordingly, it is an object of the present invention to provide a time-division driving type touch sensing driver circuit capable of reducing power consumption.

In order to achieve the above object, according to an embodiment of the present invention, a source driver IC for displaying an image during a pixel driving period is operated, and a lead-out IC for sensing a touch input during a touch sensor driving period is operated A first driving power source control unit 400 for controlling a driving power source applied to the readout IC based on a time division synchronous signal Tsync for distinguishing the pixel driving period and the touch sensor driving period; And a second driving power supply control unit 80 for controlling the driving power applied to the source driver IC based on the EPI interface signals SHD and WUC.

The present invention shuts down the lead-out IC by shutting off the driving power applied to the lead-out IC during the pixel driving period, and shutting down the source driver IC by cutting off the driving power applied to the source driver IC during the touch sensor driving period. Accordingly, the present invention prevents an unnecessary current from flowing into the source driver IC and the lead-out IC, thereby effectively solving the problem of power consumption increase due to unnecessary current flow.

1 is a view showing an example in which one frame period is divided into a pixel driving period and a touch sensor driving period.
2 is a block diagram illustrating a touch sensing driver circuit of a time division driving type according to an embodiment of the present invention.
3 is a view showing an example of touch sensors built in a pixel array;
4 is a view showing another example of touch sensors built in a pixel array;
Fig. 5 is a waveform diagram showing the operation of the touch sensor shown in Fig. 4. Fig.
6 is a view showing a multiplexer installed between the touch sensor driving circuit and the touch sensors;
7 is a waveform diagram showing an example of a time-division driving method of a pixel driving period and a touch sensor driving period.
8 is a schematic diagram for explaining a concept for reducing power consumption in the touch sensing driver circuit of the present invention.
9 is a view showing EPI wirings connected between the timing controller and the source driver ICs;
10 is a diagram showing a clock recovery circuit of a timing controller and a source driver IC.
11 is a waveform diagram illustrating an EPI interface protocol for signal transmission between the timing controller and the source driver ICs.
12 is a waveform diagram showing an EPI interface signal transmitted to source driver ICs during a horizontal blank period;
13 is a view showing a first driving power control section for controlling a driving power source of the lead-out IC;
14 is a view showing a second driving power source control unit 80 for controlling the driving power source of the source driver IC.
15 shows an example in which a driving power control signal is encoded into an EPI data packet;

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. In the following description, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

The touch sensing driver circuit of the present invention includes a display device integrated with a touch screen. The display device may be implemented based on a flat panel display device such as a liquid crystal display (LCD), an organic light emitting display (OLED) display, an electrophoretic display (EPD), or a plasma display panel (PDP). In the following embodiments, the display device will be described mainly with respect to the liquid crystal display device, but it should be noted that the display device of the present invention is not limited to the liquid crystal display device.

The touch screen of the present invention is implemented with touch sensors, which may be embedded in a pixel array. The touch sensors may be implemented as capacitive touch sensors that sense a touch input based on a change in capacitance before and after a touch. The capacitive touch sensors can be divided into a mutual capacitive touch sensor and a self capacitive touch sensor. The mutual electrostatic capacitance is formed between two conductor wirings orthogonal to each other as shown in Fig. The self-electrostatic capacity is formed along a conductor wiring of a single layer formed in one direction as shown in Fig.

2 to 7, a touch sensor driving circuit with a touch sensor according to an embodiment of the present invention includes a display panel 100, display driving circuits 202, 204 and 104, touch sensor driving circuits 302, 304, 306, and 308, and the like.

The TFT array substrate of the display panel 100 includes a plurality of data lines D1 to Dm and m being positive integers and a plurality of gate lines G1 to Gn, n crossing the data lines D1 to Dm, A plurality of TFTs formed at intersections of the data lines D1 to Dm and the gate lines G1 to Gn, a plurality of pixels connected to the data lines through the TFTs to charge the data voltage, An electrode 11, a plurality of common electrodes to which a common voltage Vcom is supplied, and a plurality of touch sensors. The TFT array substrate further includes a storage capacitor (Cst) not shown. The storage capacitor is connected to the pixel electrode (11 in Fig. 2) to maintain the voltage of the liquid crystal cell.

In the one-frame period in the touch sensing driver circuit of the present invention, the pixel driving period P1 in which data of the input image is written to the pixels of the display element, the touch sensor driving period P2 in which the touch sensors are driven, ≪ / RTI > In this case, one frame of video data is written to all the pixels during the pixel driving period P1, and all the touch sensor lines are driven during the touch sensor driving period P2.

Meanwhile, the touch sensors may be implemented by mutual capacitance type touch sensors as shown in FIG. 3, or by self-capacitance type touch sensors as shown in FIG. 4 to FIG.

The mutual capacitive touch sensors are arranged such that Tx lines (T1 to Tj, j is a positive integer less than n), Rx lines (R1 to Ri, i is a positive integer less than m), and Tx lines Tj) and the mutual capacitance formed at the intersection of the Rx lines R1 to Ri, and the like. The mutual capacitance type touch sensor can be embedded in the pixel array with the electrode structure as shown in FIG. The Tx lines T1 to Tj may include common electrode division patterns T11 to T23 and link patterns L11 to L22. The first Tx line Tx1 includes a plurality of common electrode division patterns T11 through T13 that are connected in the lateral direction via the link patterns L11 and L12. The second Tx line Tx2 includes a plurality of common electrode division patterns T21 to T23 that are connected in the lateral direction via the link patterns L21 and L22. The size of each of the common electrode division patterns T11 to T23 may be patterned to a size larger than the pixel size so as to include two or more pixel regions. Each of the common electrode division patterns T11 to T23 may be formed of a transparent conductive material such as ITO (Indium Tin Oxide). The link patterns L11 to L22 electrically connect neighboring common electrode division patterns T11 to T23 in the lateral direction (or in the horizontal direction). The mutual capacitive touch sensor structure is not limited to Fig. For example, a mutual capacitive touch sensor embedded in a pixel array can be fabricated with the structure proposed in Korean patent application 10-2012-0143228 (December 12, 2012), which is filed by the present applicant.

The Tx lines T1 to Tj and the Rx lines R1 to Ri are connected to the common electrode to supply the common voltage Vcom to the common electrode during the pixel driving period P1. During the touch sensor driving period P2, a driving signal for driving the touch sensor is supplied to the Tx lines T1 to Tj, and an output of the touch sensors is received in the Rx lines R1 to Ri in synchronization with the driving signal do.

4 to 6, the touch sensors of the self-capacitance type may be formed of the common electrode division patterns COM1 to COMn. Each of the common electrode division patterns COM1 to COMn may be formed of ITO, and may be patterned to a size larger than a pixel. The driving circuit 308 may be connected to the common electrode division patterns COM1 to COMn through the sensing lines S1 to Sn at a ratio of 1: 1 as shown in FIG. The driving circuit 308 can supply the common voltage Vcom to the common electrode division patterns COM1 to COMn during the pixel driving period P1. The driving circuit 308 may supply a driving signal as shown in FIG. 5 to the sensing lines S1 to Sn during the touch sensor driving period P2 to sense a capacitance change of the touch sensors. A multiplexer 310 may be provided between the driving circuit 308 and the sensing lines S1 to Sn to reduce the number of pins of the driving circuit 308 as shown in FIG.

A pixel array of the display panel 100 displays an input image. The pixels of the pixel array are formed in a pixel region defined by the data lines D1 to Dm and the gate lines G1 to Gn and arranged in a matrix form. Each of the pixels is driven by an electric field corresponding to a voltage difference between a data voltage applied to the pixel electrode 11 and a common voltage Vcom applied to the common electrode to control the amount of incident light. The TFTs are turned on in response to gate pulses from the gate lines G1 to Gn to supply a voltage from the data lines D1 to Dm to the pixel electrode 11 of the liquid crystal cell. The common electrode is applied with the common voltage Vcom during the pixel driving period Pl to form the reference potential of the pixels. The common electrode may be divided as shown in FIGS. 3 and 4 and used as an electrode of the touch sensors during the touch sensor driving period.

A black matrix, a color filter, or the like may be formed on the color filter substrate of the display panel 100. On the TFT array substrate and the color filter substrate of the display panel 100, an alignment film for attaching a polarizing plate and setting a pre-tilt angle of liquid crystal on the inner surface in contact with the liquid crystal can be formed. A column spacer for maintaining a cell gap may be formed in the liquid crystal layer of the display panel 100.

The display driver circuits 202, 204, and 104 write data to the pixels. The display driver circuits 202, 204, and 104 include a data driver circuit 202, a gate driver circuit 204, and a timing controller 104.

The data driving circuit 202 includes a plurality of source driver ICs (SDIC). The source driver ICs (SDIC) are connected point-to-point to the timing controller 104 via the EPI wiring pair. The source driver ICs (SDIC) output the analog video data voltage during the pixel driving period Pl.

The applicant of the present application has pointed out that the timing controller 104 and the source driver ICs (SDIC) are connected in a point-to-point manner to minimize the number of wires between the timing controller 104 and the source driver ICs (SDIC) (Hereinafter, referred to as " EPI interface protocol "), US patent application no. 12 / 461,652 (2009-08-19), Korean patent application no. 10-2008-0132466 (2008-12-23), US application no. 12 / 537,341 (2009-08) -07).

The EPI interface protocol has the following features (1) to (3).

(1) The transmitting end of the timing controller 104 and the receiving end of the source driver ICs (SDIC) are connected in a point-to-point manner via signal wiring pairs (called "EPI wiring pairs") without wiring sharing.

(2) No separate clock wiring pair is connected between the timing controller 104 and the source driver ICs (SDIC). The timing controller 104 transmits the digital data to the source driver ICs (SDIC) together with the clock signal through the EPI wiring pair. The digital data is divided into video data of the input video and source control data for controlling the operation of the source driver IC (SDIC).

(3) Each of the source driver ICs (SDIC) incorporates a clock recovery circuit for CDR (Clok and Data Recovery). The timing controller 104 transmits a preamble signal, which is a clock training pattern signal, to the source driver ICs (SDIC) so that the output phase and frequency of the clock recovery circuit can be locked. The clock recovery circuit built in the source driver ICs (SDIC) generates an internal clock according to the preamble signal input through the EPI wiring pair and locks the phase and frequency of the internal clock.

When the phase and frequency of the internal clock are fixed, the source driver ICs (SDIC) supply a high logic level lock signal (LOCK) indicating the output stable state to the timing controller 104 ). A data link is established between the source driver IC (SDIC) and the timing controller 104 to transmit data of the input image when the phase and frequency of the internal clock are stably fixed. The timing controller 104 starts transmitting control data and video data to the source driver ICs (SDIC) after the lock signal received from the last source driver IC (SDIC) is received. If the output phase and frequency of the built-in clock recovery circuit are unlocked in any of the source driver ICs (SDIC), the lock signal is inverted to a low logic level and the last source driver IC (SDIC) And transmits the inverted lock signal to the timing controller 104. The timing controller 104 resumes clocking the source driver ICs (SDICs) by sending a preamble signal to the source driver ICs (SDIC) when the lock signal is inverted to a low logic level.

The source driver ICs SDICs sample and latch the digital video data RGB input from the timing controller 104 through the EPI wiring pair during the pixel driving period Pl. The source driver ICs SDIC convert the digital video data RGB to the analog positive / negative gamma compensation voltages during the pixel driving period Pl to output the data voltages. Positive / negative polarity data voltages (Fig. 7, +/-) are supplied to the data lines D1 to Dm. The source driver ICs SDIC output the data voltage during the low logic period of the source output enable signal SOE while the data voltage during the high logic period of the source output enable signal SOE Charge sharing can be performed without outputting.

The source driver ICs (SDIC) may perform clock training according to the preamble signal input from the timing controller 104 during the touch sensor driving period (P2).

The gate driving circuit 204 generates a gate pulse (or a scan pulse) synchronized with the data voltage under the control of the timing controller 104 during the pixel driving period P1 and shifts the gate pulse to generate gate lines G1 to Gn) sequentially. The gate drive circuit 204 is also known as a scan drive circuit. The gate drive circuit 204 includes one or more gate drive ICs. The gate drive IC sequentially supplies gate pulses synchronized with the data voltages to the gate lines G1 to Gn under the control of the timing controller 104 during the pixel driving period P1 to sequentially apply the gate pulses to the display panel 100) is selected. The gate pulse swings between the gate high voltage VGH and the gate low voltage VGL as shown in FIG.

The gate driving circuit 204 can supply the gate line voltage VGL to the gate lines G1 to Gn without generating the gate pulse during the touch sensor driving period P2. Thus, the gate lines G1 to Gn sequentially supply the gate pulse to the TFTs of the pixels during the pixel driving period P1 to sequentially select the lines to which data is to be written in the display panel 100, and the touch sensor driving period P2 The gate low voltage VGL is maintained to prevent the output fluctuation of the touch sensors.

The timing controller 104 uses a timing signal such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE and a main clock MCLK input from an external host system The source control data for controlling the operation timing of the data driving circuit 202 can be encoded and transmitted to the source driver ICs (SDIC) through the EPI wiring pair. The timing controller 104 can also transmit a timing control signal to the gate drive circuit 204 for controlling the operation timing of the gate drive circuit 204 using a timing signal input from an external host system. The timing control signal of the gate driving circuit 204 includes a gate start pulse (GSP), a gate shift clock (GSC), a gate output enable signal (GOE), and the like. The source control data includes a polarity control signal (POL), a source output enable signal (SOE), and option information for controlling the output channel of the source driver IC.

The timing controller 104 may generate an internal data enable signal iDE by compressing an external data enable signal input from the host system into a predetermined pixel driving period P1. The timing controller 104 generates a time division synchronizing signal for time dividing one frame period into the pixel driving period P1 and the touch sensor driving period P2 in accordance with the timings of the vertical synchronizing signal Vsyc and the internal data enable signal iDE, (Tsync). The timing controller 104 transmits the time division synchronous signal Tsync to the touch controller 306 to synchronize the operations of the display driver circuits 202, 204 and 104 and the touch sensor driver circuits 302, 304, 306 and 308 .

When the internal data enable signal iDE starts to be generated, the timing controller 104 can transmit the preamble signal, control data, and input image data to the source driver ICs (SDIC). The timing controller 104 transmits the preamble signal to the data driving circuit 202 based on the EPI interface protocol during the pixel driving period P1 and then supplies the EMI signal to the source driver IC 202 in the order of the control data and the digital video data of the input image. (SDIC). The timing controller 104 may not transmit the EPI interface signal to the source driver ICs (SDIC) during the touch sensor driving period (P2).

The host system converts the digital video data (RGB) of the input image into a format suitable for display on the display panel (DIS). The host system transmits timing signals to the timing controller 104 together with the digital video data of the input image. The host system is implemented with any one of a television system, a set-top box, a navigation system, a DVD player, a Blu-ray player, a personal computer (PC), a home theater system, and a phone system to receive an input image. The host system executes an application program associated with the touch input coordinates received from the touch controller 104. [

The touch sensor driving circuits 302, 304, 306, and 308 drive the touch sensors to sense the touch input during the touch sensor driving period P2. The touch sensor driving circuits 302, 304, 306, and 308 include a driving circuit 302 or 308, a sensing circuit 304, a touch controller 306, and the like. The sensing circuit 304 or the driving circuit 308 may be integrated in the lead-out IC.

The driving circuit 302 supplies the common voltage Vcom to the Tx lines T1 to Tj during the pixel driving period P1 and supplies the common voltage Vcom to the Tx lines T1 to Tj during the touch sensor driving period P2. . The driving signal swings between the touch driving voltage Vdrv and the reference voltage Vref.

The sensing circuit 304 supplies the common voltage Vcom to the Rx lines R1 to Ri during the pixel driving period P1 and receives the voltages of the touch sensors during the touch sensor driving period P2. The sensing circuit 304 amplifies the analog output of the touch sensors received through the Rx lines R1 to Ri and converts the analog output into digital data to generate touch raw data.

On the other hand, the driving circuit 308 supplies the common voltage Vcom to the common electrode division patterns COM1 to COMn during the pixel driving period P1, and applies the driving signal as shown in Fig. 5 to the touch sensor driving period P2 It is possible to supply the sensed data to the sensing lines S1 to Sn to sense the capacitance change of the touch sensors and output the data by touching.

The touch controller 306 analyzes the data with the touch received from the sensing circuit 304 or the driving circuit 308 using a preset touch recognition algorithm and judges the data as touch input data with a touch equal to or higher than a predetermined threshold voltage, Can be calculated. The coordinate information of the touch input position output from the touch controller 306 is transmitted to an external host system.

On the other hand, the source driver IC does not need to operate during the touch sensor driving period P2 and therefore is not used during this period P2. On the other hand, the lead-out IC does not need to operate during the pixel driving period P1 and therefore is not used during this period P1. However, when the touch sensing driving circuit is operated, when the driving power is continuously supplied to each of the source driver IC and the lead-out IC as in the conventional art, there is a problem that power consumption is increased due to unnecessary current.

The present invention includes the driving power source control unit (400 in FIG. 13, 80 in FIG. 14) to block the driving power from being applied to the unused lead-out IC during the pixel driving period P1, P2), thereby preventing power leakage due to unnecessary current flow in the lead-out IC and the source driver IC.

8 is a schematic diagram for explaining a concept for reducing power consumption in the touch sensing driver circuit of the time division driving type according to the embodiment of the present invention.

The driving power supply control unit of the present invention shuts down the lead-out IC (ROIC) by shutting off the driving power applied to the lead-out IC (ROIC) during the pixel driving period P1, The source driver IC (SDIC) is shut down by shutting off the driving power applied to the source driver IC (SDIC) during the power-on period of the source driver IC to prevent power leakage due to unnecessary current flow in the lead-out IC and the source driver IC can do.

The present invention can minimize the cost increase due to the application of the invention by using the time-division synchronous signal (Tsync) and the EPI interface signal already provided in the touch sensing driving circuit without separately generating a signal for controlling the driving power. The driving power source control unit of the present invention controls the driving power source of the lead-out IC (ROIC) based on the time-division synchronous signal (Tsync) and controls the driving power source of the source driver IC (SDIC) based on the EPI interface signal. The present invention can easily ensure stable operation by making the driving power control paths for the source driver IC (SDIC) and the lead-out IC (ROIC) different from each other.

9 to 12 show an EPI interface signal in which a driving power control signal is encoded. Specifically, FIG. 9 is a diagram showing EPI wirings (EPI) connected between the timing controller 104 and the source driver ICs (SDIC # 1 to SDIC # 8). 10 is a diagram showing a clock recovery circuit of the timing controller 104 and the source driver IC. 11 is a waveform diagram showing an EPI interface protocol for signal transmission between the timing controller 104 and the source driver ICs (SDIC # 1 to SDIC # 8). 12 is a waveform diagram showing an EPI interface signal transmitted to the source driver ICs (SDIC # 1 to SDIC # 8) during the horizontal blank period.

9, a solid line indicates an EPI wiring pair (EPI) in which signals such as a preamble signal, control data, and video data of an input video are transmitted. The dotted line represents the lock wirings LCS1 and LCS2 to which the LOCK signal is transmitted.

9 to 12, the timing controller 104 is connected in series to each of the source driver ICs (SDIC # 1 to SDIC # 8) via an EPI wiring pair (EPI).

The timing controller 104 sequentially outputs the EPI signals to the source driver ICs (SDIC # 1 to SDIC # 8) sequentially in the order of the preamble signal, control data, and video data through the EPI wiring pair (EPI) Lt; / RTI > The control data packet is transmitted in a bit stream including a clock bit, a control start bit (CTR_Start), source and gate control data, and the like. The video data packet is transmitted in a bitstream including a clock bit, an internal data enable bit, and an RGB data bit. Each of the source driver ICs (SDIC # 1 to SDIC # 8) restores the internal clock signal input through the EPI wiring pair (EPI).

The timing controller 104 transfers the lock start signal to the first source driver IC (SDIC # 1) through the lock line LCS1 in the first phase (Phase-I) and sends the preamble signal for clock training to the EPI wiring pair To the source driver ICs (SDIC # 1 to SDIC # 8). The source driver ICs (SDIC # 1 to SDIC # 8) generate an internal clock through clock training when a lock signal (LOCK) of a high logic level and a preamble signal are input from the source driver IC of the preceding stage, And the frequency is locked to stabilize the CDR function, the high logic level lock signal is transmitted to the next stage driver IC. When the CDR of all the source driver ICs (SDIC # 1 to SDIC # 4) is stabilized, the last source driver IC (SDIC # 8) outputs the lock signal LOCK of the high logic level through the lock feedback signal line LCS2 to the timing controller (104). The lock signal output terminal of the previous stage source driver IC is not connected to the lock signal input terminal of the first source driver IC (SDIC # 1). Therefore, the DC power supply voltage Vcc of the high logic level is input to the lock signal input terminal of the first source driver ICs (SDIC # 1).

After receiving the lock signal LOCK of the high logic level from the last source driver IC (SDIC # 8), the timing controller 104 outputs control data and video data in the second and third stages (Phase-II and Phase-III) And transfers the data to each of the source driver ICs (SDIC # 1 to SDIC # 8). The control data includes control data for controlling the output timing of the data voltage output from the source driver ICs (SDIC # 1 to SDIC # 8), the polarity of the data voltage, and the like. The control data may include gate control data for controlling the operation timing of the gate drive IC (GIC).

The timing controller 104 receives the digital video data RGB of the input image from the host system through the interface receiving circuit 21. [ The timing controller 104 can generate control data including source control data and gate control data based on an external timing signal input from the host system using the internal timing control signal generating circuit 22. [ The encoder 23 can embed a shutdown control signal SHD and a wake-up control signal WUC in a data packet in a format defined by the EPI interface protocol together with a clock CLK. The output of the encoder 23 is converted into a difference signal pair through the transmission buffer 24 and transmitted to the source driver ICs (SDIC # 1 to SDIC # 8).

The receiving buffer 25 of the source driver ICs (SDIC # 1 to SDIC # 8) receives the EPI signal from the timing controller 104 through the EPI wiring pair (EPI). The clock recovery circuit 26 of the source driver IC (SDIC) restores the received clock to generate an internal clock. The sampling circuit 27 samples each of the control data and the digital video data bit according to the internal clock timing.

11, the output of the clock recovery circuit of the source driver ICs (SDIC # 1 to SDIC # 8) is stable after the preamble signal starts to be transmitted to the source driver ICs (SDIC # 1 to SDIC # 8) And the time until the lock signal LOCK is inverted to the high logic level (H).

One data packet transmitted from the EPI interface protocol to the source driver ICs (SDIC # 1 to SDIC # 8) includes a plurality of data bits, clock bits allocated before and after data bits. The data bits are bits of control data or digital video data of the input video, and may include a shutdown control signal SHD and a wakeup control signal WUC.

In the EPI interface protocol, a first phase (Phase-I) signal and a second phase (Phase-II) signal have a horizontal blank period between pulses of the internal data enable signal iDE, To the source driver ICs (SDIC # 1 to SDIC # 8).

13 shows a first driving power control unit 400 for controlling the driving power of the lead-out IC (ROIC).

Referring to FIG. 13, the touch controller 306 can exchange information by communicating with a lead-out IC (ROIC) using a serial peripheral interface (SPI) method. The touch controller 306 receives the time division synchronous signal Tsync from the timing controller 104 and supplies the time division synchronous signal Tsync to the first driving power source control unit 400. The time division synchronous signal Tsync may have a first logic level corresponding to the pixel driving period P1 and a second logic level corresponding to the touch sensor driving period P2 as shown in Fig. The first driving power supply control unit 400 outputs driving power VCC, VDD applied to the lead-out IC (ROIC) when the time-division synchronous signal Tsync is input to the first logic level (i.e., during the pixel driving period Pl) . Accordingly, the lead-out IC (ROIC) is shut down during the pixel driving period P1, and unnecessary power consumption in this period P1 is reduced. Meanwhile, when the time-division synchronous signal Tsync is input to the second logic level (i.e., the touch sensor driving period P2), the first driving power supply control unit 400 normally supplies the driving power Vcc, VDD).

13, "VCC" designates a driving power applied to digital circuit blocks of a lead-out IC (ROIC) for sensing a touch input, "VDD" designates a lead-out IC (ROIC) To the analog circuit blocks. The first driving power source control unit 400 can control at least one of "VCC" and "VDD ".

14 shows a second driving power source control unit 80 for controlling the driving power source of the source driver IC (SDIC). 15 shows an example in which the driving power control signal is encoded into the EPI data packet.

The source driver IC (SDIC) supplies positive / negative data voltages to k (k is a positive integer of 2 or more) data lines (D1 to Dk). The source driver IC (SDIC) includes a data sampling and serial-to-parallel converter 71, a digital to analog converter (DAC) 72, an output circuit 73, can do.

The data sampling and deserialization unit 71 may include a receive buffer 25, a clock recovery circuit 26, and a sampling circuit 27 as shown in FIG. The data sampling and serial-to-parallel conversion unit 71 outputs the internal clocks using the clock recovery circuit 26 and outputs the RGB digital video data bits of the input image received via the EPI wiring pair (EPI) . The data sampling and serial-to-parallel conversion unit 71 latches the sampled data bits and outputs the sampled data bits at the same time to convert them into parallel data.

The data sampling and deserializing unit 71 restores the control data received through the EPI wiring pair (EPI) by a code mapping method to generate source control data. When the gate control data is encoded in the control data, the data sampling and serial / parallel conversion unit 71 restores the gate control data from the control data input through the EPI wiring pair and transmits it to the ICs of the gate driving circuit. The source control data may include a source output enable signal SOE, a polarity control signal POL, option information, and the like. The polarity control signal POL indicates the polarity of the positive / negative analog data voltage supplied to the data lines D1 to Dk. The source control data and the gate control data are encoded by the timing controller 104 and transmitted to the source driver IC (SDIC) through the EPI wiring pair (EPI) in the second stage (Phase-II). Methods of encoding and restoring control data in the EPI interface protocol have been proposed in domestic applications 10-2008-0132466 (2008.12.23), US patent application 12 / 537,341 (2009.08.07) filed by the present applicant .

The DAC 72 converts the video data input from the data sampling and serial-to-parallel converter 71 into a positive gamma compensation voltage GH and a negative gamma compensation voltage GL to generate a positive / . The DAC 72 inverts the polarity of the data voltage in response to the polarity control signal POL.

The output circuit 73 does not output the data voltage during the high logic period of the source output enable signal SOE but outputs the average voltage of the positive polarity data voltage and the negative polarity data through the charge sharing to the data lines D1 to Dk. During the charge sharing period, the output channels to which the positive data voltages are supplied and the output channels to which the negative data voltages are supplied are short-circuited in the source driver ICs (SDIC # 1 to SDIC # 8) And supplies an average voltage of the negative data voltages to the data lines D1 to Dk. The output circuit 73 supplies the positive / negative polarity data voltage to the data lines D1 to Dk through the output buffer during the row logic period of the source output enable signal SOE. Thus, the source driver IC (SDIC) outputs the data voltage during the low logic period of the source output enable signal SOE and inverts the polarity of the data voltage according to the polarity control signal POL.

On the other hand, the timing controller 104 additionally generates dummy data enable pulses 14 and 16 at the end and the beginning of the pixel driving period P1, and generates driving power control signals SHD , WUC) can be transferred to the source driver IC (SDIC) via an EPI wiring pair (EPI). In this case, the driving power control signals SHD and WUC are encoded in the dummy data packets 15 and 17 which are additionally generated at the end and the beginning of the pixel driving period P1 as shown in Fig. 15, and are transmitted to the source driver IC (SDIC) .

The data sampling and deserializing unit 71 restores the driving power control signals SHD and WUC received through the EPI wiring pair EPI and supplies the restored driving power control signals SHD and WUC to the second driving power control unit 80.

The second driving power supply control unit 80 responds to the shutdown control signal SHD input from the data sampling and serial-to-parallel conversion unit 71 to the source driver IC (SDIC), that is, the output circuit The driving power sources VCC and VDD applied to the power source lines 73 and 73 are cut off. Accordingly, during the touch sensor driving period P2, the source driver IC (SDIC) is shut down as shown in Fig. 15, and unnecessary power consumption in this period P2 is reduced. On the other hand, the second driving power supply control unit 80 normally operates to the source driver IC (SDIC) during the pixel driving period P1 in response to the wakeup control signal WUC input from the data sampling and serial- And the power source (VCC, VDD) is applied.

14, "VCC" indicates the driving power applied to the digital circuit blocks of the source driver IC (SDIC), "VDD" indicates the driving power applied to the analog circuit blocks of the source driver IC do. The second driving power source control unit 80 can control at least one of "VCC" and "VDD ".

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

104, TCON: timing controller
SDIC # 1 to SDIC # 8: Source drive IC
ROIC: Lead-out IC
202: Data driving circuit
204: Gate drive circuit
302: Driver circuit of mutual capacitance touch sensor
304: sensing circuit of mutual capacitance touch sensor
306: Touch controller
308: Drive circuit of the capacitive touch sensor
310: Multiplexer
80, 400: Driving power control unit

Claims (11)

A touch sensing driver circuit in which a source driver IC for image display is operated during a pixel driving period and a readout IC for sensing a touch input during a touch sensor driving period is operated,
A first driving power control unit 400 for controlling a driving power applied to the readout IC based on a time division synchronous signal Tsync for distinguishing the pixel driving period and the touch sensor driving period; And
And a second driving power supply control unit (80) for controlling driving power applied to the source driver IC based on the EPI interface signals (SHD, WUC) based on the time division synchronous signal (Tsync)
The first driving power supply control unit 400 shuts down the lead-out IC by interrupting driving power applied to the lead-out IC during the pixel driving period,
The second driving power source control unit 80 shuts down the source driver IC by shutting off driving power applied to the source driver IC during the touch sensor driving period. delete The method according to claim 1,
The time division synchronous signal Tsync has a first logic level corresponding to the pixel driving period and a second logic level corresponding to the touch sensor driving period;
The first driving power supply control unit 400 may be configured to turn off the driving power applied to the readout IC when the time division synchronous signal is input to the first logic level, The driving power is normally applied to the lead-out IC. The method according to claim 1,
Further comprising a timing controller (104) for generating the time division synchronous signal (Tsync) and the EPI interface signals (SHD, WUC);
The timing controller 104 additionally generates first and second dummy data enable pulses 14 and 16 at the end and initial stages of the pixel driving period, respectively, and outputs the first and second dummy data enable pulses 14 16, respectively, the shutdown control signal SHD and the wakeup control signal WUC to the source driver IC as the EPI interface signal;
The shutdown control signal SHD and the wakeup control signal WUC are encoded in the dummy data packets 15 and 17, which are additionally generated at the end and the beginning of the pixel driving period, respectively, in. 5. The method of claim 4,
The second driving power source control unit (80)
In response to the shutdown control signal SHD, the driving power applied to the source driver IC during the touch sensor driving period is shut off and the source driver IC is turned on during the pixel driving period in response to the wake- A touch sensing driver circuit that normally applies driving power. The method according to claim 1,
The driving power source
A first driving power source (VCC) applied to each of the digital circuit blocks of the readout IC and the source driver IC; And
And a second driving power source (VDD) applied to the analog circuit blocks of the read-out IC and the source driver IC, respectively. In a touch sensing driving circuit in which one frame period is divided into a pixel driving period and a touch sensor driving period in accordance with the time division synchronizing signal Tsync,
A source driver IC for charging a data voltage to pixels of the display element during the pixel driving period;
A lead-out IC for sensing a touch input of the touch sensors built in the display panel during the touch sensor driving period; And
And a first driving power source control unit (400) for controlling a driving power source applied to the readout IC based on the time division synchronous signal (Tsync)
The first driving power control unit 400 shuts down the lead-out IC by shutting off driving power applied to the lead-out IC during the pixel driving period. 8. The method of claim 7,
The time division synchronous signal Tsync has a first logic level corresponding to the pixel driving period and a second logic level corresponding to the touch sensor driving period;
The first driving power supply control unit 400 may be configured to turn off the driving power applied to the readout IC when the time division synchronous signal is input to the first logic level, The driving power is normally applied to the lead-out IC. In a touch sensing driving circuit in which one frame period is divided into a pixel driving period and a touch sensor driving period in accordance with the time division synchronizing signal Tsync,
A source driver IC for charging a data voltage to pixels of the display element during the pixel driving period;
A lead-out IC for sensing a touch input of the touch sensors built in the display panel during the touch sensor driving period; And
And a second driving power supply control unit (80) for controlling driving power applied to the source driver IC based on the EPI interface signals (SHD, WUC) based on the time division synchronous signal (Tsync)
The second driving power supply control unit 80 may be configured to turn off the driving power applied to the source driver IC during the touch sensor driving period in response to the shutdown control signal SHD among the EPI interface signals SHD and WUC, A touch sensing driver circuit that shuts down the driver IC. 10. The method of claim 9,
The second driving power supply control unit 80 is responsive to the wakeup control signal WUC among the EPI interface signals SHD and WUC to apply driving power to the source driver IC during the pixel driving period, in. 11. The method of claim 10,
Further comprising a timing controller (104) for generating the time division synchronous signal (Tsync) and the EPI interface signals (SHD, WUC)
The timing controller 104,
First and second dummy data enable pulses 14 and 16 are additionally generated at the end and at the beginning of the pixel driving period respectively and are synchronized with the first and second dummy data enable pulses 14 and 16 respectively The shutdown control signal SHD and the wakeup control signal WUC to the source driver IC as the EPI interface signal.

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