KR101624145B1 - A method for error correction using Reed Solomon - Convolutional Concactenated Code and an apparatus - Google Patents

Abstract

The present invention relates to a method and apparatus for error correction of a Reed-Solomon convolutional code scheme. The present invention relates to a method and apparatus for error correction of a Reed-Solomon convolutional code scheme, Generating an erasure locator polynomial having positional information to be corrected according to the erasure position, and performing error correction using the erasure locator polynomial using the Reed Solomon method. And an error correction method and apparatus of the Reed-Solomon convolutional code system.

Reed Solomon, viterbi

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an error correction method and apparatus for Reed Solomon and convolutional code,

The present invention relates to a method and apparatus for error correction of Reed Solomon and convolutional code systems, and more particularly to a method and apparatus for error correction of Reed-Solomon and convolutional code systems that can increase the error correction capacity.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus and method for channel coding an RS-CC concatenated code widely used as a forward error correction (FEC) technique in a communication system such as satellite and mobile communication and a digital storage medium.

Channel coding of the RS-CC concatenated code is a code that concatenates Reed Solomon code and Convolutional code.

The Viterbi decoder has excellent ability to correct for scattered errors occurring in the channel, but it has insufficient ability to correct for the burst error. To compensate for this error, the Reed Solomon decoder is used to process the cluster error .

The Viterbi decoder generally decodes the input signal in units of frames, which are cut to a length of 5 to 8 times the constraint length. In addition, the Viterbi decoder uses a Soft Decision Decoding (AMC) correction method to improve the scatter error correction capability.

The Reed-Solomon code code is composed of N bits of symbols, not a bit, and a parity symbol of 2t symbol length is added to K data symbols to generate N code data as a codeword, and the N code data is transmitted. The Reed-Solomon decoder has a characteristic that it can always correct for error symbols within 1 t symbol length in one code word.

In the RS-CC concatenated code decoder, the Viterbi decoder corrects the scatter error, and then the cluster error is corrected by the Reed Solomon decoder. The input codeword of the Reed-Solomon decoder is composed of output frames of a plurality of Viterbi decoders.

In the conventional RS-CC concatenated code decoder, the correction capability for the cluster error is limited by half of the parity length (1 t symbol length). If a cluster error of more than 1t occurs in the codeword, decoding becomes impossible and a CRC error is indicated.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and it is therefore an object of the present invention to provide a RS decoder for RS- Of the present invention is improved to a maximum of 2t.

According to another aspect of the present invention, there is provided a method of correcting an error of a Reed-Solomon convolutional code scheme, the method comprising the steps of: 2t symbol length, generating an erasure locator polynomial having positional information to be corrected according to the erasure position, and performing error correction using the erasure locator polynomial using the Reed Solomon method .

The step of performing the error correction includes the steps of calculating an error size and an error position using a value obtained by multiplying the error locator polynomial by the erasure locator polynomial and an error magnitude polynomial, And correcting the error signal.

Wherein the frame reliability is calculated by using at least one of reliability of a last state of a frame, sum of all state reliability of a frame, and sum of some state reliability among all states of a frame in one frame do.

According to another aspect of the present invention, there is provided an apparatus for correcting an error of a Reed-Solomon convolutional code system, the apparatus comprising: A Viterbi decoding unit for finding an erasure position of a 2t symbol length in order; And a Reed Solomon decoding unit which generates an erasure locator polynomial having positional information to be corrected according to the erasure position and performs error correction using the erasure locator polynomial using the Reed Solomon method.

Wherein the Reed-Solomon decoding unit comprises: an erasure locator polynomial generator for generating an erasure locator polynomial using the erasure locator; Wherein the step of performing the error correction includes: a parity operation unit for calculating an error size and an error position using a value obtained by multiplying an error locator polynomial by an erasure locator polynomial and an error magnitude polynomial; And an error correction unit for correcting the data using the error size and the error position.

The Viterbi decoding section calculates frame reliability using at least one of the reliability of the last state of the frame, the sum of all the state reliability of the frame, and the sum of some state reliability among all states of the frame in one frame And a frame reliability calculation unit.

According to the present invention, the error position is found using the frame reliability, and the error correction is performed using the erasure position of 2t symbol lengths, thereby increasing the capacity of error correction that can be performed at one time . Thus, reliability of error correction can be improved.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following description, only parts necessary for understanding the operation according to the present invention will be described, and the description of other parts will be omitted so as not to obscure the gist of the present invention.

FIG. 1 is a diagram for explaining a wireless communication system using RS-CC coding and decoding according to an embodiment of the present invention.

Referring to FIG. 1, a transmitter includes a CRC (Cyclic Redundancy Check) processing unit 10 for attaching a CRC code through a CRC operation, a Reed Solomon code unit 20 for performing Reed Solomon encoding, A convolutional code unit 30 for performing convolutional coding, and a modulation unit 40 for performing modulation. Signals having undergone CRC code attachment, Reed Solomon encoding, convolutional encoding, and modulation on the transmitting side are transmitted to the receiving side through the channel 1000.

The receiver includes a demodulator 100 for demodulating the received signal, a Viterbi decoder 200 for performing Viterbi decoding, a Reed-Solomon decoder 300 for performing Reed-Solomon decoding, and a CRC check And a CRC processing unit 400.

The Viterbi decoding unit 200, the Reed-Solomon decoding unit 300, and the CRC processing unit 400, which are components for error correction and verification in the above-described wireless communication system, will be described. In particular, the Viterbi decoding unit 200 according to the embodiment of the present invention uses a soft decision method and a tail biting method, and the Reed Solomon decoding unit 300 uses an erasure method Will be described as an example.

2 is a view for explaining an error correction apparatus according to an embodiment of the present invention.

The error correction apparatus according to an embodiment of the present invention mainly includes a Viterbi decoding unit 200, a Reed Solomon decoding unit 300, and a CRC processing unit 400.

The Viterbi decoding unit 200 outputs a Reed Solomon (RS) codeword (CW, CodeWord) and outputs a 2t symbol (CW, CodeWord) in descending order of reliability per frame in a plurality of error candidate frames, And outputs an erasure position (error position) of the length.

Then, the Reed-Solomon decoding unit 300 generates an error location polynomial using the erasure position of the 2t symbol length, and corrects the error using the generated polynomial.

The CRC processing unit 400 detects an error through CRC calculation on the error-corrected data.

In view of the fact that the error position stored in the parody of the RS code word is 1t symbol length in the related art, the capacity of error correction that can be corrected at one time increases.

Hereinafter, the Viterbi decoding unit 200 and the Reed Solomon decoding unit 300 according to the embodiment of the present invention will be described, respectively.

First, the Viterbi decoding unit 200 will be described. 3 and 4 are diagrams for explaining a Viterbi decoding unit 200 according to an embodiment of the present invention.

FIG. 3 is a diagram illustrating a trellis for detecting per-frame reliability according to an embodiment of the present invention. FIG. 4 is a diagram illustrating a Viterbi decoding unit in FIG.

Referring to FIGS. 3 (A) and 3 (B), the memory state processing method of the transmission side convolutional code unit 30 includes a tail zero method A and a tail- biting method (B). The tail zero method A initializes a state to 0 for each frame and inputs information bits and finally generates a tail bit that makes the state 0 tail bits. Meanwhile, the tail-biting method B is a method for making the information about the state in the tail different from zero in the state different from the tail zero method (A) Do not work. In the present invention, the tail-biting method (B) will be described as an example.

The Viterbi decoding method corresponding to the convolutional coding described above calculates all branch metrics existing on the trellis with respect to the received bits and generates a path metric generated according to the branch value, "Path value") is used to perform decoding along the least or large path. Here, the Viterbi decoding method differs depending on whether the path metric is selected as the largest or the smallest metric, and it is assumed that the Euclidean metric is used. The lowest value is selected and used. The examples described here will all be based on the assumption that euclidean metrics are used.

The soft decision output Viterbi decoding scheme does not output the decoded value as a hard decision value of 0 or 1 but outputs a value of 0 or 1 with a certain degree of reliability.

In the soft decision output Viterbi decoding algorithm, this reliability is determined by the difference between the path 303 having the smallest path metric and the path 305 having the largest path value among the various paths introduced into the arbitrary state 301 I decide. In this case, among the various paths that flow into any one state, the surviving path (solid line) is the most excellent path value, and the path which is ignored because it is not considered anymore is referred to as a competition path (Dotted line).

Hereinafter, the Viterbi decoding unit 200 according to the embodiment of the present invention will be described with reference to the above-described trellis.

4, a Viterbi decoding unit 200 according to an embodiment of the present invention includes a branch metric calculation unit 201, an ACS (Add-Compare-Select) calculation unit 203, a trace -back unit 205 and the output unit 207 and outputs a corrected error-corrected signal to the Reed-Solomon decoding unit 300. The Reed-

Also, the Viterbi decoding unit 200 derives candidate frames that are likely to cause an error through the state mismatch detection unit 209 and the candidate frame determination unit 211. [ On the other hand, the reliability storage unit 213, the state reliability detection unit 215, and the frame reliability calculation unit 217 of the Viterbi decoding unit 200 calculate the frame reliability based on the state reliability.

At this time, the erasure position specification unit 219 derives the erasure position of the symbol length of 2t per frame from the candidate frames.

The branch value operation unit 201 performs branch value operation on all branches on the trellis using the difference between the received bit stream and the branch coded word (BCW) on the Trellis of the transmitter convolutional encoder Compute the branch metric. The branch value operation unit 201 first calculates the distance value between the input value and the representative value. Here, the distance value is preferably an Euclidean distance value. Then, the branch value computing unit 201 generates all the branch values generated in the state transition process through the calculated distance value. The generated value is used to calculate the path metric.

The ACS operation unit 203 adds a branch metric calculated in the branch value calculation unit 201 and a path metric of a previous state to obtain a path metric from each branch to the current state 301, . Then, the ACS operation unit 203 compares the path values from each branch, finds the minimum path value 303, and selects a survivor path having the minimum path value 303. [

The ACS operation unit 203 receives two path values of the previous state that can reach the current state 301 and finally selects the smallest path value 303 among the path values 303 and 305 reaching the current state. In this manner, the ACS operation unit 203 creates the survival path 303 by connecting the paths having the minimum path value.

For this, the ACS operation unit 203 performs three operations. These are sum (ADD), compare (COMPARE) and select (SELECT).

The sum (ADD) is to add the branch values of the branch from the previous state to the current state to the path value of the previous state to generate a path value from each branch to the current state. COMPARE receives the path value from the generated branch to the current state, subtracts it, and outputs the result. The output value is information indicating a result of comparing two sizes of path values from each branch to the current state, and is information indicating a survival path. SELECT is to select and output the smaller of the path values from each branch to the current state. The survival path is selected. Here, a small value is selected according to the Euclidean metric, and when using another metric, a large value can be selected.

The generated path value is stored for reuse to generate the path value of the next state.

The ACS operation unit 203 outputs the reliability for all the paths to the reliability storage unit 213 while the reliability storage unit 213 stores the reliability Stores reliability for all paths.

As described above, the ACS operation unit 203 selects the minimum path value 303 among the path values 303 and 305 reaching the current state 301. [ At this time, the selected path is called a survivor path, and the unselected path is called a compete path. The ACS operation unit 203 can calculate the reliability that is the difference between the path value of the survival path and the path metric of the competition path. When the reliability value is high, the reliability of the error correction of the bit is high, and when the reliability value is low, the reliability of the error correction of the bit is low.

The tracing unit 205 performs decoding based on the survivor path on the trellis detected by the ACS operation unit 203 through a method of selecting a minimum path in a process of transition to each state.

This traceback process starts with state 0 and ends with state 0 in the case of a tail zero system, starts in any state in case of tail biting, and ends in operation in the same state. do.

At this time, there is a high possibility that the error correction is correctly performed when the start state and the last state are the same, and if not, the error correction is likely to fail.

The case where the start state and the last state are not the same will be referred to as "stste mismatch ". For example, the first state is 00, but the last state is not 00.

In addition, the backtrace unit 205 notifies the state reliability detection unit 215 of the state currently being traced back in tracking back the survival path.

On the other hand, the data decoded for each bit in the backward tracing unit 205 is output by the output unit 207 in units of bytes.

The state mismatch detection unit 209 detects the frame in which the start state and the last state do not coincide with each other, that is, the state mismatch frame, and notifies the candidate frame determination unit 211 of the detection of the backtrace unit 205.

At this time, the state mismatch detection unit 209 detects the start state and the last state of the rotor corresponding frame of the back tracking unit 205, and then detects the frames whose start and end states do not coincide with each other.

There is a high possibility that the error correction is correctly performed when the start state and the last state are the same, and if not, the error correction is likely to fail. Therefore, the candidate frame determination unit 211 determines the frames in which state inconsistency has occurred as an error candidate frame, and notifies the erasure location specification unit 219 of the frames.

On the other hand, the reliability storage unit 213 stores the reliability of the state according to all the paths, and stores the reliability of the state according to the operation result of the ACS operation unit 203, as described above.

The state reliability detection unit 215 recognizes the state that the current trailing unit 205 tracks backward and outputs the reliability for the current state. The reliability of the outputting state can be obtained from the reliability storage unit 213. [

The frame reliability calculation unit 217 receives the reliability of the state tracked by the current trailing unit 205 in each frame from the state reliability detection unit 215 and calculates the frame reliability (FQM, Frame Quality Metric).

Reliability of the error correction result of each frame can be confirmed by using reliability. There are several ways to measure the reliability of a frame, depending on the resource limitations.

That is, the method for calculating the frame reliability includes a method of using the reliability of the last state of the frame, a method of summing the reliability of each state of each frame, and a method of calculating the reliability of each state of the frame , And at least one of the above three methods is used.

The erasure position specification unit 219 designates a frame with low frame reliability as the erasure position in the candidate error frame received from the candidate frame determination unit 211. [

The erasure position specification unit 219 selects a position of a frame in order of low frame reliability (FQM) among the error position candidate frames, and selects the position of the frame with the 2t symbol length. Accordingly, the erasure position specification part 219 outputs the erasure position of the 2t symbol length.

Assuming that one frame processed by the Viterbi decoding unit 200 is 32 bits and one symbol length of the Reed Solomon code word is 8 bits, the data of the Reed-Solomon codeword is 255 symbols, and the pattern becomes 32 symbols. Therefore, an erasure position of 8 frames can be designated.

As described above, the Viterbi decoding unit 200 performs the decoding of the Reed-Solomon scheme and designates and outputs the erasure position of the 2t symbol length based on the reliability per frame among the frames in which state inconsistency has occurred.

Reed Solomon decoding unit 300 performs error correction on a symbol basis in an RS code word expressed by (N, K, t). The codeword structure of the Reed-Solomon code is such that the value of the N symbol obtained by adding the parity of the 2t symbol to the input K symbols becomes one codeword (N = K + 2t).

As the Viterbi decoding unit 200 outputs the erasure position (error position) of the 2t symbol length, the Reed Solomon decoding unit 300 performs error correction on the error position of the existing 1t symbol length, Error correction can be performed through the error position of the symbol length. Hereinafter, the Reed-Solomon decoding unit 300 will be described.

5 is a diagram for explaining a Reed Solomon decoding unit according to an embodiment of the present invention.

The Reed Solomon decoding unit 300 includes a buffer unit 401, an erasure position polynomial operation unit 403, a syndrome operation unit 405, a first multiplier 407, an error polynomial operation unit 409, a second multiplier unit 411, A parity calculation unit 413, and an error correction unit 415. [

The buffer unit 401 temporarily stores the input signal in units of RS codewords and outputs the signal to the error correction unit 415 in a first in first out (FIFO) manner.

The erasure locator polynomial calculator 403 receives the erasure position (error position) of the 2t symbol length of the erasure locator designation 219 and generates an erasure locator polynomial. The erasure locator polynomial is given by Equation (1) below.

The syndrome operation unit 405 computes a syndrome of a 2t symbol through a parity input symbol having a length of 2t in the input Reed-Solomon codeword, and outputs the syndrome.

In the embodiment of the present invention, the syndrome operation unit 405 processes the input value of the portion corresponding to the error position of the parity in the syndrome operation by processing it as 0.

After the syndrome operation, the first multiplier 407 multiplies the syndrome polynomial by the erasure locator polynomial and outputs the result.

The error polynomial operation unit 409 performs a modified Euclidean operation on the signal multiplied by the syndrome polynomial and the erasure locus polynomial to calculate an error position polynomial and an error magnitude polynomial expressing the error position of the 1t symbol length and the error magnitude of the 1t symbol length, And outputs it.

At this time, the second multiplier 411 multiplies the error locator polynomial by the erasure locator polynomial and inputs the result to the parity calculator 413. [

The parity calculator 413 receives the product of the error locator polynomial and the erasure locator polynomial and the error magnitude polynomial, calculates and outputs the error magnitude through the "Forney" algorithm, calculates the error location through the "Chien search & do. By taking the error locator polynomial and the erasure locator polynomial as its inputs, the parity operator 413 can know a larger number of error locations through known erasure locations (error locations) of 2 t symbol length. Accordingly, the parity calculating unit 413 can output the error position through a larger amount of known error positions.

The error correction unit 415 corrects the error of the RS code word by using the RS code word temporarily stored in the buffer unit 401 and the error position and the error size, which are the outputs of the parity operation unit 413.

Next, an error correction method using the error correction apparatus according to the embodiment of the present invention will be described. 6 is a diagram for explaining an error correction method according to an embodiment of the present invention.

According to the embodiment of the present invention, the error position (erase position) of 2t symbols can be stored. However, in a case where the error correction apparatus can sufficiently correct the error position through the error position of the 1t symbol length, that is, in general, the error correction apparatus performs Viterbi decoding in steps S601 and S603, To correct the error. Then, in step S605, the error correction apparatus checks the error correction result through the CRC check.

At this time, if the CRC check result is success, it is confirmed in step S607 that the error correction is performed on the 0 to 1t symbols, and the error correction process is terminated. On the other hand, if the CRC check result in step S605 is a failure, it may be a failure due to an error position (erasure position) of 1 t symbol length or more. Therefore, the error correction apparatus proceeds to step S615 and performs the Reed Solomon decoding using the erasure locator polynomial.

In order to use the erasure locator polynomial, the erasure position of the 2t symbol length must be known in advance. For this reason, when the Viterbi decoding in step S601 is started, the error correction apparatus calculates the frame reliability in step S609, detects a frame in which a state mismatch has occurred in step S611, and determines a frame reliability of frames in which state mismatch has occurred And finds the erasure position of the 2t symbol length. Accordingly, if a CRC error occurs in step S605, the error correction apparatus performs Reed Solomon decoding using the erasure locator polynomial in step S613. As described above, the erasure locator polynomial is generated using the erasure position of the 2t symbol length as shown in Equation (1).

Subsequently, the error correction apparatus performs a CRC check in step S617. If the CRC check result of step S617 is successful, the error correction device confirms that error correction has been performed for t + 1 to 2t symbols in step S619, and ends the error correction process. If not, the error correction device returns that the error correction has failed in step S621 and terminates the process.

The Reed-Solomon decoding section can always correct for error symbols of less than or equal to t, and for error symbols of t + 1 to 2t, only the presence or absence of errors is known, and error correction is impossible. However, according to the embodiment of the present invention, correction of up to 2t symbols is always possible when the positions (erase positions) of up to 2t error symbols are known. According to the embodiment of the present invention, by performing error correction by increasing the erase position (error position) by 2t symbol length, the cluster error correction capability of the RS-CC decoding apparatus can be increased up to 2 times. In addition, it is possible to selectively use the embodiment of the present invention only when the error correction is performed using the error position of the 1 t symbol length, and the correction can not be performed through the error position of the 1 t symbol length, that is, when the CRC error occurs.

Therefore, in the present invention, when error correction fails, the feature of the Viterbi decoding unit 200 that generates error bits continuously in the frame is used.

That is, after the erasure positions of the 2-t symbol length, that is, the error frames, are detected using the state mismatch and the state reliability in the Viterbi decoding section 200, the correcting ability can be improved by applying the error mismatching section 300 to the Reed- .

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, Therefore, the scope of the present invention should not be limited by the illustrated embodiments, but should be determined by the scope of the appended claims and equivalents thereof.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram for explaining a wireless communication system using an RS-CC code and decoding according to an embodiment of the present invention; FIG.

2 is a view for explaining an error correction apparatus according to an embodiment of the present invention.

3 and 4 are views for explaining a Viterbi decoding unit according to an embodiment of the present invention.

5 is a diagram for explaining a Reed Solomon decoding unit according to an embodiment of the present invention.

6 is a diagram for explaining an error correction method according to an embodiment of the present invention.

Claims (8)

A method for error correction of a Reed Solomon convolutional joint code scheme, Calculating a frame reliability for each frame upon Viterbi decoding; Detecting at least one frame in which mismatching between the start and end states occurs in the Viterbi decoding, Outputting an erasure position of a symbol length of 2t in descending order of the frame reliability among the detected at least one frame as a result of the Viterbi decoding; Generating an erasure locator polynomial having positional information to be corrected according to the erasure position upon Reed-Solomon decoding; And performing error correction using the erasure locator polynomial in the Reed-Solomon decoding of the Reed-Solomon convolutional code. The method according to claim 1, The step of performing the error correction includes the steps of calculating an error size and an error position using a value obtained by multiplying the error locator polynomial by the erasure locator polynomial and an error magnitude polynomial, And correcting the error of the Reed-Solomon convolutional code. The method according to claim 1, Wherein the frame reliability is calculated using at least one of reliability of the last state of the frame in one frame, summation of all state reliability of the frame, and summation of some state reliability among all states of the frame A method for error correction of a Reed Solomon convolutional joint code scheme. A Reed Solomon convolutional code code error correction apparatus, A frame reliability calculating unit for calculating a frame reliability for each frame and detecting at least one frame in which a mismatch between the start and end states occurs and for outputting an erasure position of a 2t symbol length in the order of decreasing the frame reliability among the detected at least one frame, Non-decoding unit; And a Reed Solomon decoding unit for generating an erasure locator polynomial having positional information to be corrected according to the erasure position and performing error correction using the erasure locator polynomial. Correction device. 5. The method of claim 4, The Reed-Solomon decoding unit, An erasure locator polynomial generator for generating an erasure locator polynomial using the erasure locator; A parity operation unit for calculating an error size and an error position using a value obtained by multiplying the error locator polynomial by the erasure locator polynomial and an error magnitude polynomial; And And an error correcting unit correcting the data using the error size and the error position. 5. The method of claim 4, Wherein the Viterbi decoder comprises: In one frame, a frame reliability calculation section that calculates the frame reliability using at least one of a reliability of a last state of a frame, a sum of all state reliability of a frame, and a sum of some state reliability among all states of a frame And an error correcting unit of the Reed-Solomon convolutional code system. delete delete

Images