KR101617965B1 - Encoder of systematic polar codes - Google Patents

Abstract

An embodiment of the present invention suggests an encoder of systematic polar codes by repeat processes. A method for performing the encoder of systematic polar codes to generate coded bits from message bits, may include a step of allocating a plurality of original message bits to some of the coded bits to perform systematic coding; and a step of obtaining some of the remaining coded bits, by repeatedly applying at least one basic calculation unit. So, systematic polar coding can be efficiently carried out.

Description

{ENCODER OF SYSTEMATIC POLAR CODES}

The following description relates to a coding technique and relates to a pole-coded encoder capable of achieving a channel capacity.

Polar codes, which can achieve the channel capacity, are emerging as interest of academia and industry. Most of these studies are concentrated on efficient or high-performance decoders, and relatively few studies on encoders are available.

It is known that the performance of Systematic poles is superior to that of Non-Systematic Poles, and has better BER performance. We propose an efficient encoder that performs systematic polar coding.

Embodiments of the present invention can provide an encoder that performs systematic polar coding.

A method for performing systematic coding to generate a plurality of coded bits from a plurality of message bits according to an embodiment includes allocating original message bits to a portion of a plurality of coded bits to perform systematic coding And obtaining the remaining part of the plurality of coded bits by repeatedly applying at least one predetermined basic arithmetic unit.

According to one aspect, at least some of the plurality of message bits may comprise predefined parity bits.

According to another aspect, each of said at least one basic arithmetic unit may comprise at least one adder for adding said plurality of coded bits to each other.

According to another aspect, each of the at least one basic arithmetic unit is configured to add each of N (N is a natural number) coded bits and N + 1 (N is a natural number) coded bits of the plurality of coded bits, And at least one adder for adding the adder.

According to another aspect, the at least one basic operation unit includes a basic operation unit composed of a plurality of basic operation units, and the order of each of the at least one basic operation units may be changeable.

According to another aspect, a method for performing systematic polar coding includes transmitting original message bits allocated to a portion of the plurality of coded bits and the obtained remaining portion to the receiver as the plurality of coded bits Or may be stored in a storage medium.

According to another aspect, obtaining the remaining portion of the plurality of coded bits may comprise restoring information about the plurality of message bits from the plurality of coded bits using a basic operation unit, And restoring the plurality of coded bits from information on the plurality of message bits using an operation unit, and repeatedly performing the restoration process.

According to another aspect, a generator matrix representing a relationship between the plurality of coded bits and the plurality of message bits comprises a plurality of columns, each of the at least one basic operation units comprises a plurality of consecutive bit nodes May correspond to an operation between columns.

An encoder that performs systematic polar coding to generate a plurality of coded bits from a plurality of message bits according to an embodiment may allocate original message bits to a part of a plurality of coded bits to perform systematic coding ; And an obtaining unit that obtains the remaining part of the plurality of coded bits by repeatedly applying at least one basic arithmetic unit preset.

According to one aspect, at least some of the plurality of message bits may comprise predefined parity bits.

According to another aspect, each of said at least one basic arithmetic unit may comprise at least one adder for adding said plurality of coded bits to each other.

According to another aspect, each of the at least one basic arithmetic unit is configured to add each of N (N is a natural number) coded bits and N + 1 (N is a natural number) coded bits of the plurality of coded bits, And at least one adder for adding the adder.

According to another aspect, the at least one basic operation unit includes a basic operation unit composed of a plurality of basic operation units, and the order of each of the at least one basic operation units may be changeable.

According to another aspect of the present invention, an encoder for performing the systematic policing may transmit original message bits allocated to a part of the plurality of coded bits and the obtained remaining part to the receiver as the plurality of coded bits Or may be stored in a storage medium.

According to another aspect, the obtaining unit is configured to recover information on the plurality of message bits from the plurality of coded bits using a basic calculation unit, and to use the basic calculation unit to calculate And reconstructs the plurality of coded bits from the information on the information about the coded bits.

According to another aspect, a generator matrix representing a relationship between the plurality of coded bits and the plurality of message bits comprises a plurality of columns, each of the at least one basic operation units comprises a plurality of consecutive bit nodes May correspond to an operation between columns.

Embodiments of the present invention can provide an efficient encoder that performs systematic polar coding in the same manner regardless of a coding rate and a channel. Also, the encoder that performs systematic polar sign can maximize the efficiency by reducing the number of operations through interleaving of the basic operation unit.

In addition, the present invention can be applied to a field in which error correction codes are used through an encoder that performs systematic polar coding, an error correction field for wired / wireless communication, an error correction field for NAND flash memory, And it is possible to reduce the delay caused by the coding, and to improve the size of the circuit required for coding and the power consumption efficiency.

1 is a diagram showing a conventional polar code encoding method.
FIG. 2 is a diagram illustrating a systematic method of encoding a polar sign.
3 is a view for explaining a basic operation unit according to an embodiment.
FIG. 4 is a diagram illustrating a method of performing systematic polar sign coding according to an exemplary embodiment. Referring to FIG.
FIG. 5 is a flowchart illustrating a method of performing systematic polar coding of an encoder performing systematic polar coding according to an exemplary embodiment. Referring to FIG.

Hereinafter, embodiments will be described in detail with reference to the accompanying drawings.

1 is a diagram showing a conventional polar code encoding method.

라고 하고, 코드 비트를

라고 할 때,

라고 표현할 수 있다. 메시지부(110)는 메시지 비트들(

,

,

,

)을 포함할 수 있고, 코딩 비트부(120)는 코딩된 비트들(

,

,

,

)을 포함할 수 있다. The poles encoding method uses the message bits

And the code bit

When you say,

. The message part 110 includes message bits (

,

,

,

), And the coding bit portion 120 may include coded bits (

,

,

,

).

으로 표현가능하며, 여기서

이고,

는 Kronecker Product를 자신에게 수행함을 표현하며,

으로, N은 부호의 길이를 나타낸다. 일반적으로 N은 2의 거듭제곱 형태를 갖는다. At this time,

Can be expressed as

ego,

Express Kronecker Product to himself,

, And N represents the length of the code. In general, N has a power of 2 form.

Referring to FIG. 1, the polarity sign coding method in the case of general N = 4 is shown. The message part of the polar sign is composed of information bits (information bits) to be actually transmitted and frozen bits Bit). In other words, the message bits of the message unit 110 may include information bits including message information and frozen bits corresponding to a parity.

FIG. 2 is a diagram illustrating a systematic method of encoding a polar sign.

,

이고, 프로즌 비트들을

,

라고 가정하자. 또한, 인포메이션 비트들의 인덱스 세트 A(Index Set A)와 체계적인 비트들, 즉, 코딩된 비트들(220) 중 인포메이션 비트들의 인덱스 세트 B (Index Set B)가 동일하다고 가정하자. 도 2에서는 A=B={3,4}이다.For example, the information bits

,

And the frozen bits

,

. It is also assumed that the index set A of the information bits and the index set B of the information bits of the coded bits 220 are the same. In Fig. 2, A = B = {3, 4}.

,

와 코딩된 비트 중 일부인 원래의 메시지 비트인

,

가 알려진 상황에서 메시지 비트들 중 인포메이션 비트들(

,

)과 코딩된 비트들 중 패리티 비트에 해당하는 비트인

,

을 구해내야 한다.The systematic polynomial encoder must find some of the message bits 210 and some bits of the coded bits in the known contexts, such as information bits and parity bits, among the coded bits. In other words, among the message bits 210,

,

And the original message bit, which is part of the coded bits

,

Lt; RTI ID = 0.0 > (b) < / RTI > of the message bits

,

) And a bit corresponding to the parity bit among the coded bits

,

.

To solve this problem, the following method is used. First, we can split the encoding problem into two small problems.

Each problem can be solved in the following order.

을 비롯한

들은 모두 자기 자신이 inverse가 된다는 사실이다. 이러한 방식은 결국 F에 대응하는 기초 연산 유닛 하나를 이용하여 그래프 전체의 노드 값을 순서대로 계산해나가는 방식을 의미한다.If there is a problem that can not be resolved, you can perform the task of breaking the problem down into two smaller problems. At this point,

Including

Are all inverse to themselves. This method means a method of computing the node values of the entire graph in order using one basic operation unit corresponding to F in the end.

3 is a view for explaining a basic operation unit according to an embodiment.

The basic operation unit 310 may be composed of a plurality of basic operation units, and may be configured by combining and multiplying between basic operation units. At this time, the basic operation unit 310 can change the order of each of the plurality of basic operations.

Each of the at least one basic arithmetic unit may include at least one adder for adding the plurality of coded bits to each other. Wherein each of the at least one basic arithmetic unit includes at least one adder for adding each of N (N is a natural number) coded bits and N + 1 (N is a natural number) coded bits of the plurality of coded bits can do. For example, the basic operation unit 310 may include at least two adders for adding together a plurality of coded bits. The basic operation unit 310 may include at least two adders for adding each of the first coded bit and the second coded bit and the third coded bit and the fourth coded bit of the plurality of coded bits have. The basic operation unit 310 may correspond to an operation between a plurality of consecutive bit node columns. In other words, the basic operation unit 310 may correspond to an operation of a matrix in which a generator matrix is decomposed.

FIG. 4 is a diagram illustrating a method of performing systematic polar sign coding according to an exemplary embodiment. Referring to FIG.

When encoding is performed through the proposed method of the present invention, it can be expressed as shown in FIG. 4, and an unknown value among the intermediate variables may be denoted by e and a known value may be denoted by c.

A method for performing systematic policing coding to generate a plurality of coded bits from a plurality of message bits includes assigning original message bits to a portion of a plurality of bits to perform systematic coding, Lt; RTI ID = 0.0 > of the plurality of coded bits. ≪ / RTI > At this time, the original message bits allocated to some of the plurality of coded bits and the remaining part obtained may be transmitted to the receiver as a plurality of coded bits or may be stored in a storage medium.

(420) from a plurality of coded bits (410) using a basic operation unit and a plurality of message bits (420) from information about a plurality of message bits (420) Lt; RTI ID = 0.0 > 430, < / RTI > At least some of the plurality of message bits may comprise predefined parity bits. At this time, a generator matrix representing a relationship between a plurality of coded bits and a plurality of message bits includes a plurality of columns, and each of at least one basic operation unit includes a plurality of consecutive bit node columns As shown in FIG.

Referring to FIG. 3, each of the at least one basic arithmetic unit may include at least one adder for adding the plurality of coded bits to each other. Wherein each of the at least one basic arithmetic unit includes at least one adder for adding each of N (N is a natural number) coded bits and N + 1 (N is a natural number) coded bits of the plurality of coded bits can do. For example, each of the at least one basic arithmetic unit may comprise at least two adders for adding together a plurality of coded bits. Each of the at least one basic arithmetic unit includes at least two adders for adding each of a first coded bit and a second coded bit and a third coded bit and a fourth coded bit of the plurality of coded bits . At this time, each of the basic arithmetic units includes a plurality of basic arithmetic units, and the order of each of the plurality of basic arithmetic units is changeable.

Each column can be computed by interleaving the basic operation, and the inverse operation of each column is itself. As described above, if the index set A of the information bits is the same as the index set B of the information bits of the systematic bits, i.e., the coded bits, systematic polar coding is performed irrespective of the coding rate and the channel .

로 표현할 수 있으며,

이고

는 Kronecker Product를 의미할 수 있다. 제너레이터 매트릭스 및

라는Kronecker Product 의 특성 및

의 표현이 가능함을 활용하여 다음과 같은 수식으로 해석할 수 있다.Generator Matrix G

As shown in FIG.

ego

Can mean Kronecker Product. Generator matrix and

The nature of the Kronecker Product and

, The following expression can be used.

와 같이 나타낼 수 있다.For example, the first term can be interpreted as an operation performed between the first bit node column and the second bit node column,

As shown in Fig.

와 같은 수식 내의 텀들간에 교환법칙이 성립한다. 즉, 그래프 표현에서의 컬럼들간의 순서를 마음대로 변경해도 연산 결과가 동일하다. 이에 따라 부호율 및 채널에 따라 제너레이터 매트릭스를 표현하는 기본 연산 유닛의 인터리빙 순서를 변경함으로써 연산 횟수를 줄일 수 있다. An encoder that performs systematic polar coding according to an exemplary embodiment includes:

The exchange rule is established between the terms in the equation. That is, even if the order of the columns in the graph representation is arbitrarily changed, the operation result is the same. Accordingly, the number of operations can be reduced by changing the interleaving sequence of the basic arithmetic unit expressing the generator matrix according to the code rate and the channel.

FIG. 5 is a flowchart illustrating a method of performing systematic polar coding of an encoder performing systematic polar coding according to an exemplary embodiment. Referring to FIG.

A method of performing systematic polar encoding may be performed by an encoder that performs systematic polar encoding, and an encoder that performs systematic polar encoding will be described with reference to FIG. 1 to FIG.

An encoder performing systematic polar coding in step 510 may allocate original message bits to some of the plurality of coded bits to perform systematic coding. At this time, at least some of the plurality of coded bits may include a predefined parity bit. A generator matrix representing a relationship between a plurality of coded bits and a plurality of message bits may comprise a plurality of columns.

The encoder performing systematic polar coding in step 520 may obtain the remaining part of the plurality of coded bits by repeatedly applying the predetermined at least one basic operation unit. At this time, the original message bits allocated to some of the plurality of coded bits and the remaining part obtained may be transmitted to the receiver as a plurality of coded bits or may be stored in a storage medium.

An encoder performing systematic polar coding restores information on a plurality of message bits from a plurality of coded bits using a basic operation unit, and generates a plurality of message bits from information on a plurality of message bits using a basic operation unit. The coded bits are restored, and the restoration process can be repeatedly performed.

Each of the at least one basic arithmetic unit may include at least one adder for adding the plurality of coded bits to each other. Wherein each of the at least one basic arithmetic unit includes at least one adder for adding each of N (N is a natural number) coded bits and N + 1 (N is a natural number) coded bits of the plurality of coded bits . The at least one basic calculation unit includes a plurality of basic calculation units, and the order of each of the plurality of basic calculation units is changeable.

An encoder that performs systematic polar coding according to an exemplary embodiment repeatedly uses a basic operation unit to recover information on a plurality of message bits from a plurality of coded bits, and uses a basic operation unit to generate a plurality of message bits Lt; / RTI > can be performed in the same manner regardless of the coding rate and the channel by restoring a plurality of coded bits from the information about the channel. In addition, the present invention can be applied to fields in which error correction codes are used through a coder performing a systematic polarity code, fields in which polar codes can be used, for example, error correction fields for wired / wireless communication, and error correction fields for NAND flash memories And it is possible to reduce the delay caused by the coding, and to improve the size of the circuit required for coding and the power consumption efficiency.

The apparatus described above may be implemented as a hardware component, a software component, and / or a combination of hardware components and software components. For example, the apparatus and components described in the embodiments may be implemented within a computer system, such as, for example, a processor, a controller, an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable array (FPA) A programmable logic unit (PLU), a microprocessor, or any other device capable of executing and responding to instructions. The processing device may execute an operating system (OS) and one or more software applications running on the operating system. The processing device may also access, store, manipulate, process, and generate data in response to execution of the software. For ease of understanding, the processing apparatus may be described as being used singly, but those skilled in the art will recognize that the processing apparatus may have a plurality of processing elements and / As shown in FIG. For example, the processing unit may comprise a plurality of processors or one processor and one controller. Other processing configurations are also possible, such as a parallel processor.

The software may include a computer program, code, instructions, or a combination of one or more of the foregoing, and may be configured to configure the processing device to operate as desired or to process it collectively or collectively Device can be commanded. The software and / or data may be in the form of any type of machine, component, physical device, virtual equipment, computer storage media, or device , Or may be permanently or temporarily embodied in a transmitted signal wave. The software may be distributed over a networked computer system and stored or executed in a distributed manner. The software and data may be stored on one or more computer readable recording media.

The method according to an embodiment may be implemented in the form of a program command that can be executed through various computer means and recorded in a computer-readable medium. The computer-readable medium may include program instructions, data files, data structures, and the like, alone or in combination. The program instructions to be recorded on the medium may be those specially designed and configured for the embodiments or may be available to those skilled in the art of computer software. Examples of computer-readable media include magnetic media such as hard disks, floppy disks and magnetic tape; optical media such as CD-ROMs and DVDs; magnetic media such as floppy disks; Magneto-optical media, and hardware devices specifically configured to store and execute program instructions such as ROM, RAM, flash memory, and the like. Examples of program instructions include machine language code such as those produced by a compiler, as well as high-level language code that can be executed by a computer using an interpreter or the like. The hardware devices described above may be configured to operate as one or more software modules to perform the operations of the embodiments, and vice versa.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. For example, it is to be understood that the techniques described may be performed in a different order than the described methods, and / or that components of the described systems, structures, devices, circuits, Lt; / RTI > or equivalents, even if it is replaced or replaced.

Therefore, other implementations, other embodiments, and equivalents to the claims are also within the scope of the following claims.

Claims (16)

A method for performing systematic polar coding to generate a plurality of coded bits from a plurality of message bits,
Assigning original message bits to the portion of the plurality of coded bits to perform systematic coding in a known state of some of the plurality of coded bits;
By repeatedly applying at least one pre-set basic arithmetic unit, the basic arithmetic unit comprising at least one adder for adding two of the input bits, the remaining part of the plurality of coded bits, ≪ / RTI >
Lt; / RTI >
Wherein the step of obtaining the remainder excluding the portion of the plurality of coded bits comprises:
Recovering information on the plurality of message bits from the plurality of coded bits using the basic operation unit and extracting the plurality of coded bits from information on the plurality of message bits using the basic operation unit, And restoring the bits, and performing the restoration process repeatedly. The method according to claim 1,
Wherein at least some of the plurality of message bits comprise predefined parity bits. delete The method according to claim 1,
Each of the at least one basic arithmetic unit
And at least one adder for adding each of N (N is a natural number) coded bits and N + 1 (N is a natural number) coded bits of the plurality of coded bits. The method according to claim 1,
The at least one basic arithmetic unit

A plurality of basic arithmetic units corresponding to the plurality of basic arithmetic units,
Wherein the order of each of the at least one basic arithmetic units performs a variable systematic polar coding. The method according to claim 1,
Transmitting the original message bits allocated to some of the plurality of coded bits and the obtained remaining part to the receiver as the plurality of coded bits or storing the same in a storage medium
The method comprising the steps of: delete The method according to claim 1,
A generator matrix representing a relationship between the plurality of coded bits and the plurality of message bits comprises a plurality of columns,
Wherein each of the at least one basic arithmetic unit is disposed between the plurality of columns to perform an arithmetic operation between the plurality of columns
A method for performing systematic polar coding. 1. An encoder performing systematic polar coding to generate a plurality of coded bits from a plurality of message bits,
An allocator for allocating original message bits to the portion of the plurality of coded bits to perform systematic coding in a known state of some of the plurality of coded bits; And
By repeatedly applying at least one pre-set basic arithmetic unit, the basic arithmetic unit comprising at least one adder for adding two of the input bits, the remaining part of the plurality of coded bits, ≪ / RTI >
Lt; / RTI >
The obtaining unit
Recovering information on the plurality of message bits from the plurality of coded bits using the basic operation unit and extracting the plurality of coded bits from information on the plurality of message bits using the basic operation unit, And performing systematic polar coding to repeatedly perform the restoration process. 10. The method of claim 9,
Wherein at least some of the plurality of message bits include predefined parity bits. delete 10. The method of claim 9,
Each of the at least one basic arithmetic unit
And at least one adder for adding Nth (N is a natural number) coded bit and N + 1 (N is a natural number) coded bits of the plurality of coded bits. 10. The method of claim 9,
The at least one basic arithmetic unit

A plurality of basic arithmetic units corresponding to the plurality of basic arithmetic units,
Wherein the order of each of the at least one basic arithmetic units performs variable systematic polar coding. 10. The method of claim 9,
Transmitting the original message bits allocated to a portion of the plurality of coded bits and the remaining portion obtained as the plurality of coded bits to a receiver or storing the same in a storage medium
And an encoder for performing a systematic polar encoding. delete 10. The method of claim 9,
A generator matrix representing a relationship between the plurality of coded bits and the plurality of message bits comprises a plurality of columns,
Wherein each of the at least one basic arithmetic unit is disposed between the plurality of columns to perform an arithmetic operation between the plurality of columns
An encoder that performs systematic polar coding.

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