KR101613510B1 - Multi-Mode Low-Noise Pipeline ADC - Google Patents

Abstract

The present invention relates to an ADC having an N-stage pipeline structure including a plurality of MDACs and a plurality of flash ADCs, wherein one or more stages including the MDAC and the flash ADC are sequentially blocked from the last stage, The number of bits to be controlled is controlled so that it is possible to drive in a multi-mode.

Description

Multi-mode Low-Noise Pipeline ADC < RTI ID = 0.0 >

The present invention relates to a CMOS pipelined ADC, and more particularly, to a CMOS pipelined ADC that can be driven in multiple modes by sequentially blocking one or more stages including MDAC and flash ADC from the last stage.

Unlike charge-coupled devices (CCDs), CMOS image sensors (CISs) are characterized by small area, low power, low cost, and high operating speed, and are integrated on-chip with other circuits using CMOS processes It is being used in a wide range of fields, from mobile devices, medical imaging equipment, automotive systems and high-resolution digital cameras. In particular, the demand for low power analog-to-digital converters (ADC) for high performance CIS applications in high resolution digital cameras such as digital single-lens reflex (DSLR) cameras is rapidly increasing. FIG. 1 shows a high-performance CIS block diagram of a cluster-parallel ADC structure in which a plurality of columns are divided into groups in order to optimize area and power consumption. A pixel array, a row / column scanner, a correlated double sampling (CDS) MUX, variable gain amplifier (VGA) and ADC. In this case, ADC for high resolution digital camera application requires 14-bit 50 MS / s high-resolution ADC to provide high-quality clear image in still image mode. In video image mode, 10-bit An ADC of 70MS / s is required. In recent commercial CIS market, single-slope ADC (SS-ADC), successive approximation register-based ADC (SAR-ADC) and cyclic ADC are mainly used. The SS-ADC has a simple structure, it has a small area, consumes less power, and has an excellent conversion performance. However, since more than 2 ^N clock cycles are required for N-bit conversion of one sampled input, there is a problem that the operation speed is limited when a high resolution is implemented. In the case of the SAR-ADC and the cyclic ADC, A / D conversion can be performed only with N clocks to realize N-bit resolution, which is advantageous in that the operation speed is comparatively faster than that of the SS-ADC. However, There is a speed limit. In addition, the SAR-ADC has a problem in that the number of capacitors used in a digital-to-analog converter (DAC) increases exponentially in proportion to the resolution, resulting in a drastic increase in area and power consumption, and a significant increase in capacitance due to parasitic capacitance and capacitor mismatch. Bit resolution or more.

As a result, a pipeline structure is mainly used for minimizing power consumption and area while simultaneously satisfying a high resolution of 14 bits or more and an operation speed of several tens MS / s or more among various ADC structures. In recent years, various correction techniques have been used to realize a high resolution of 14 bits or more. However, due to additional required circuits, the complexity of the system has increased, resulting in intellectual property (IP) for system-on-a-chip It is difficult to use.

Korean Patent "Pipeline Analog-to-Digital Converter (10-2011-0049522)"

SUMMARY OF THE INVENTION It is an object of the present invention to provide a CMOS pipeline ADC that can be driven in multiple modes by sequentially blocking one or more stages including MDAC and flash ADC from the last stage.

In order to solve the above-described problems, the present invention provides an ADC having a pipeline structure including N stages and including a plurality of MDACs and a plurality of flash ADCs, wherein one or more stages including an MDAC and a flash ADC And adjusts the number of bits determined by the ADC.

According to another embodiment of the present invention, the MDAC and the flash ADC of the last stage each include a cutoff switch in the bias circuit, and the MDAC and the flash ADC of the last stage are cut off by the respective cutoff switches ADC.

According to another embodiment of the present invention, the amplifier used for the input stage SHA may include an input stage SHA using an amplifier to which a gain boosting technique is applied, the NMOS stage gain boosting amplifier having a PMOS input, The amplifier may be a folded-cascade amplifier having an NMOS input, and the amplifier used in the input stage SHA may maximize the transconductance of the current source transistor within the saturation region to minimize amplifier noise, To maximize the transconductance of the transistor within the saturation region.

According to another embodiment of the present invention, the MDAC of the first stage and the MDAC of the second stage may share one amplifier, and the amplifier shared by the MDAC of the first stage and the MDAC of the second stage may share two pairs And an NMOS input terminal of the first stage and an unused input terminal of the two NMOS input stages may be alternately initialized to a predetermined bias voltage. An amplifier shared by the first stage MDAC and the second stage MDAC may include two When the NMOS input stage is selected, a phase-overlapping clock can be used. In order to minimize amplifier noise, the transconductance of the current source transistor is maximized within the saturation region and the transconductance of the input stage transistor is maximized within the saturation region. Can be an ADC that is characterized.

According to another embodiment of the present invention, a reference current and a reference voltage generator in which a driving circuit of a reference voltage used for amplifying the plurality of MDACs and a driving circuit of a reference voltage used for operation of the plurality of flash ADCs are separated, The reference current and the reference voltage generator may be integrated on-chip, and may be an ADC that selectively uses an integrated reference voltage or an externally applied reference voltage.

The present invention can provide a CMOS image sensor including the ADC.

In accordance with the present invention, multiple ADCs can be implemented with one ADC. That is, 14 bit 50MS / s for still image mode and 10 bit 70MS / s performance for video image mode can be implemented simultaneously without additional correction technique. In addition, 10-bit 70 MS / s mode can achieve the same input-referred noise as in 14-bit 50 MS / s mode and minimize power consumption, area and noise.

Figure 1 is a high performance CIS block diagram for high resolution digital camera applications.
2 is a multi-mode pipelined ADC according to an embodiment of the present invention.
FIG. 3 illustrates a low noise input stage SHA amplifier to which a gain-boosting circuit according to an embodiment of the present invention is applied.
4 illustrates a high gain low noise two stage amplifier based on an amplifier sharing technique according to an embodiment of the present invention.
FIG. 5 illustrates an MDAC using a switch-based bias circuit according to an embodiment of the present invention.
FIG. 6 illustrates a reference current and voltage generator that minimizes power consumption and switching noise according to an embodiment of the present invention. Referring to FIG.
7 is a chip and layout photograph of a multimode pipelined ADC according to an embodiment of the present invention.
8 to 11 are experimental results of a multimode pipelined ADC according to an embodiment of the present invention.

Prior to the description of the concrete contents of the present invention, for the sake of understanding, the outline of the solution of the problem to be solved by the present invention or the core of the technical idea is first given.

An ADC having a pipeline structure including N stages and including a plurality of MDACs and a plurality of flash ADCs according to an exemplary embodiment of the present invention sequentially blocks MDACs and flash ADCs from the last stage, And the number of bits determined by the ADC is adjusted.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. It will be apparent to those skilled in the art, however, that these examples are provided to further illustrate the present invention, and the scope of the present invention is not limited thereto.

BRIEF DESCRIPTION OF THE DRAWINGS The above and other features and advantages of the present invention will become more apparent by describing in detail preferred embodiments thereof with reference to the attached drawings in which: It is possible to quote the above. In the following detailed description of the principles of operation of the preferred embodiments of the present invention, it is to be understood that the present invention is not limited to the details of the known functions and configurations, and other matters may be unnecessarily obscured, A detailed description thereof will be omitted.

2 is a multi-mode pipelined ADC according to an embodiment of the present invention.

A multi-mode pipelined ADC according to an exemplary embodiment of the present invention includes N MDACs including a plurality of MDACs and a plurality of flash ADCs, and sequentially blocks MDACs and flash ADCs from the last stage. Thereby adjusting the number of bits determined by the ADC.

More specifically, the number of stages of the pipeline may vary according to the desired specifications, and thus the number of MDACs and flash ADCs involved may vary. It can also be used in dual mode or multi-mode by blocking the last stage MDAC and flash ADC, or by blocking two or more MDAC and flash ADCs. The number of stages of the pipeline or whether the pipeline is multi-mode may vary depending on the specifications of the ADC to be implemented.

In order to implement the multi-mode, the MDAC and flash ADC of the last stage each include a blocking switch in the bias circuit, and the MDAC and flash ADC of the last stage can be blocked by each blocking switch. The shutoff switch can be turned on and off according to a control signal. The control signal may vary according to a user's input or a predetermined order. The amplifier used for the input stage SHA, which constitutes the input stage, can be implemented by a gain boosting technique. The NMOS-only gain boosting amplifier of the amplifier used for the input stage SHA may have a PMOS input and the PMOS-only gain boosting amplifier may use a folded-cascode amplifier having an NMOS input. The amplifier used in the input stage SHA can maximize the transconductance of the current source transistor within the saturation region and maximize the transconductance of the input stage transistor within the saturation region in order to minimize the amplifier noise. The transconductance of the current source transistor may be determined according to the specification of the current source transistor, and the transconductance of the input terminal transistor may also be determined according to the specification of the input terminal transistor. Or by calculating the transconductance of the current source and the input terminal transistor that minimizes the thermal noise through the experiment.

The MDAC in the first stage and the MDAC in the second stage share one amplifier to minimize area and power consumption at the same time. The amplifiers shared by the MDAC of the first stage and the MDAC of the second stage may alternately initialize the unused input terminals of the two NMOS input stages to a predetermined bias voltage in order to reduce the memory effect generated when the amplifiers are shared, To reduce glitch energy, when two NMOS inputs are selected, a clock with overlapping phases can be used. Like the input stage SHA, the amplifier shared by the MDAC of the first stage and the MDAC of the second stage maximizes the transconductance of the current source transistor in the saturation region to minimize the noise of the amplifier and maximizes the transconductance of the input stage transistor It can be increased to the maximum within the saturation region.

In order to solve the instability of the reference voltage, a reference current and a reference voltage generator in which a driving circuit of a reference voltage used for the amplifying operation of the plurality of MDACs and a driving circuit of a reference voltage used for the operation of the plurality of flash ADCs are separated . The reference current and the reference voltage generator are integrated on-chip.

Hereinafter, an ADC according to an embodiment of the present invention will be described in detail using a pipelined ADC of FIG. 2, which implements multi-mode of 14 bits and 10 bits.

The ADC according to the embodiment of the present invention is implemented in a low noise dual mode 4-stage pipeline structure for implementing 14 bit 50MS / s in still image mode and 70MS / s in 10 bit in video image mode for high performance CIS application. It has the same input reference noise in 14 bit 50 MS / s mode and 10 bit 70 MS / s mode by interrupting the last stage MDAC3 and flash ADC4 when operating in 10 bit 70 MS / s mode. The input stage SHA can minimize power consumption, area and noise by using the conventional flip-around architecture. To overcome the limitations of the flip-around architecture, a single stage folded-cascode amplifier based on gain- Voltage gain and bandwidth. In addition, the necessary output swing margin of the amplifier is sufficiently taken into consideration, but the transconductance of the current source transistor is reduced and the input stage transconductance is increased, thereby minimizing the thermal noise generated in the amplifier itself. In order to minimize power consumption and area, the first and second MDACs, MDAC1 and MDAC2, share the same amplifier and use two separate pairs of inputs to effectively reduce the memory effect of sharing the amplifier. At this time, the amplifier can obtain the required voltage gain and secure stable signal fixing performance by using the two-stage amplifier using the cascode frequency compensation technique. In addition, as with SHA, the thermal noise of the amplifier can be minimized by optimizing the current source transistor and input stage transconductance design. Finally, the MDAC amplification operation and the reference voltage driver circuit used in flash ADC operation can be separated to reduce the problem of reference voltage instability according to different load conditions and requirements. In particular, sufficient power can be secured with only a small reference voltage connected to the MDAC which requires high resolution, so that the power consumed in the reference voltage driving circuit can be minimized.

A dual-mode ADC that simultaneously implements 14-bit and 10-bit modes is shown in FIG. Stage pipeline structure that determines 4 bits each in the first, second and third stages and determines 5 bits in the last stage. In the upper range of the _{P -P} 2.2V is applied from the outside to properly process the input signal input stage sample-and-hold amplifier (SHA ), MDAC, flash ADC, on-chip reference current and a voltage generator, the clock generator is at least It is implemented as a thick-gate-oxide transistor with a gate length of 0.35um and can operate at a high 3.3V supply voltage. On the other hand, a digital calibration circuit using a low 1.2V supply voltage and a divider can be implemented with a thin-gate-oxide transistor with a minimum gate length of 0.13um to output low-voltage digital data to the ISP. In the 14-bit 50MS / s mode, it operates in a 4-stage pipeline structure. However, in 10-bit 70MS / s mode, the operation of MDAC3 and flash ADC4 in the last stage is blocked, Has a reference noise. On the other hand, the input stage SHA based on the flip-around structure using two capacitors uses a gate-bootstrapping circuit to maintain high linearity in the Nyquist frequency input to the sampling switch, and a gain- With a single amplifier, sufficient phase margin can be obtained for a wide operating frequency range and stable signal setting while reducing power consumption. In MDAC, a stable signal can be obtained by securing a sufficient phase margin by using a two-stage amplifier using a low-impedance-based cascode frequency compensation technique. In the first and second stages, an amplifier is shared Area and power consumption are reduced. In addition, the reference current and the reference voltage generator are integrated on-chip for high resolution and high operation speed to stably supply the reference current and reference voltage to the core analog block, and the amplification operation of MDAC, By separately separating the reference voltage drive circuit in consideration of different load conditions, the problem of instability such as signal interference due to the switch operation is solved and power consumption is minimized. A digital calibration circuit including a divider can be used immediately in a variety of CIS systems using a high voltage clock signal and a level-shift circuit that converts digital data to a low voltage basis.

The ADC according to the embodiment of the present invention includes an input stage SHA to which a gain boosting technique is applied.

More specifically, the input stage SHA is the block with the greatest constraint on the pipelined ADC performance. It has a high voltage gain and at the same time a fast operation speed to minimize the SHA signaling error, non-linearity and noise components at the 14- Is required. If a two-stage amplifier is used in a SHA, high voltage gain and sufficient output swing margin can be achieved, but to obtain sufficient phase margin to enable stable operation, the input stage transconductance of the second stage amplifier must be increased , The power consumption is increased because of the use of the frequency compensation technique, and the dynamic performance degradation due to the thermal noise of the amplifier is larger than that of the first stage amplifier. Usually, a flip-around structure and a charge redistribution structure are commonly used in the input stage SHA structure. When the flip-around structure using two capacitors is compared with the charge redistribution structure, since the feedback factor (β) is ideally twice as large, the bandwidth required to obtain the same closed loop bandwidth is reduced by half, minimizing power consumption In addition, there is an advantage that the input reference noise generated in the SHA can be reduced by half. However, in the case of flip-around structure, the input common-mode voltage, which has a decisive influence on the amplifier performance, varies depending on the input condition.

Therefore, the input stage SHA according to the embodiment of the present invention reduces the influence on the input common mode voltage change during the holding operation in the flip-around structure, obtains sufficient voltage gain and phase margin, and minimizes the performance degradation due to the thermal noise of the amplifier As shown in FIG. 3, a single stage folded-cascode amplifier using a gain-boosting technique can be used. In this case, the gain-boosting amplifier is less susceptible to the input common-mode range and uses a folded-cascode amplifier with a PMOS input for the NMOS single gain-boosting amplifier and a NMOS input for the PMOS single- . Gain - The use of the boosting mechanism pole-zero pair (doublet) affecting the fixing performance benefit - is formed near the unity gain bandwidth of the boosting amplifier (f _{u, ba).} To optimize the fixing performance of the overall amplifier f _{u, ba} should be formed between the whole amplifier f _{-3 dB} and the second pole and, f _u, more _ba is close to the second pole, the less the effect of the doublet. As a result of this optimization, the overall amplifier achieves a high voltage gain of 100dB, and is designed to meet a 86 ° stable phase margin to achieve optimized fusing performance.

On the other hand, the kT / C noise generated from the SHA sampling switch and the thermal noise of the amplifier are also factors that limit the dynamic performance of the entire ADC. The kT / C noise of the SHA is determined by the sampling capacitor size, and the thermal noise generated by the folded-cascode amplifier itself can be expressed by Equation (1).

The input stage transistors M1 and M2 and the current source transistors M4 and M5 and M10 and M11 in FIG. 3 have a great influence on the thermal noise of the folded-cascode amplifier. Consider the output swing margin required in the amplifier, by maximizing the transient drive voltage (V _OV ) of (M4, M5), (M10, M11) to reduce transconductance and increasing the transconductance of The thermal noise generated by the amplifier itself can be minimized. SHA's sampling capacitor can be used to mitigate dynamic performance degradation due to kT / C noise by using 6pF considering 14-bit resolution and 2.2V _PP input signal range. have. In addition, to sample without distortion at a resolution of 14 bits or more, an input sampling switch can be provided with an on-resistance that is independent of the magnitude of the input signal using a gate-bootstrap circuit.

In the ADC according to the embodiment of the present invention, the first stage MDAC and the second stage MDAC share one amplifier.

More specifically, in order to implement a high-speed, high-resolution pipelined ADC, the output signal of the MDAC must be set within a certain level of error within a half period of the clock corresponding to the amplification mode according to the resolution processed at each stage. The first and second MDACs, MDAC1 and MDAC2, utilize the fact that the nature of the pipelined architecture based on switched-capacitor circuitry performs amplification operations only during the half-clock period of the clock and not during the remaining half- In order to minimize power consumption at the same time, one amplifier is implemented as two input stages as shown in FIG. 4 so that amplification operation is always performed in all clock phases. Also, in order to satisfy the required high voltage gain and operation speed, a telescopic amplifier can be configured in two stages to obtain a high voltage gain of 102dB level.

4, the memory effect of sharing the amplifier can be minimized by initializing the unused input terminals of the two NMOS input stages of the first stage amplifier to a constant bias voltage alternately. Also, as shown in the right side of FIG. 4, when the two input stages are selected, the amplifiers can operate stably by minimizing the glitch energy generated by alternately selecting the amplifiers by using a clock in which a part of the phases are overlapped. On the other hand, in a two-stage amplifier structure, a cascode frequency compensation scheme having a higher phase margin than the Miller frequency compensation scheme is used when the same current is used by connecting one end of the frequency compensation capacitor to a cascode node having a low impedance. The power consumption can be minimized while obtaining the phase margin. Like the input stage SHA, MDAC1 is a block that has a large impact on the dynamic performance of the entire ADC, and can use a 6pF sampling capacitor to account for kT / C noise. In the case of a two-stage amplifier architecture, the amplifier noise in the second stage is divided by the high voltage gain in the first stage, so that the overall amplifier noise is not affected. Thus, except for the amplifier noise in the second stage, the thermal noise generated in the first stage telescopic amplifier itself is expressed by Equation (2).

In the case of the telescopic amplifier shown in FIG. 4, the input stage transistors M1 and M2 and the current source transistors M6 and M7 have a large influence on the noise. Since the number of elements affecting the noise is smaller than that of the folded- Is possible. At this time, as in the input stage SHA, the V _OV voltage of (M6, M7) is maximally increased within the required output swing margin of the amplifier to reduce the transconductance and increase the transconductance of (M1, M2) The thermal noise component can be minimized.

To implement the dual mode, the ADC of the last stage of the ADC according to the embodiment of the present invention includes a blocking switch in the bias circuit, respectively, and the MDAC and flash ADC of the last stage are connected Can be blocked.

More specifically, 10-bit mode operation does not use the entire 14-bit output to simultaneously implement 14-bit 50 MS / s mode and 10-bit 70 MS / s mode operation. To do this, you can block the operation of the first stage MDAC and flash ADC, or block the MDAC and flash ADC operation of the last stage. The ADC according to the embodiment of the present invention blocks the operation of the last stage MDAC3 as shown in FIG. 5 in order to implement the dual mode. In the case of blocking the first stage MDAC and flash ADC, it is advantageous to minimize the power consumption by blocking the first stage MDAC with high power consumption in 10-bit 70 MS / s mode. However, It is not suitable for CIS applications requiring noise. On the other hand, since the noise component of the last stage MDAC3 is divided by the closed loop gain of MDAC1 and MDAC2 when viewed from the input of the ADC, the influence on the input reference noise of the entire ADC is insignificant. Thus, as shown in FIG. 5, the bias circuit of MDAC3 includes a switch controlled by the SHDNB signal for switching from the 14 bit 50 MS / s mode to the 10 bit 70 MS / s mode, and the ADC operates in 10 bit 70 MS / s mode By turning off the switch by the SHDNB signal, the power consumed by MDAC3 can be reduced to achieve the same input-referred noise as the 14-bit 50 MS / s mode while optimizing power consumption at each resolution. At the same time when MDAC3 does not operate, the bias circuit of the flash ADC4 at the last stage can also minimize the power consumed in the 10-bit 70 MS / s mode, including the switch controlled by the SHDNB signal.

The ADC according to the embodiment of the present invention includes a reference current and a reference voltage generator in which a driving circuit of a reference voltage used for amplifying operations of a plurality of MDACs and a driving circuit of a reference voltage used for operation of a plurality of flash ADCs are separated .

More specifically, a reference current and voltage generator, which is less sensitive to temperature and supply voltage variations, is essential for the proposed ADC to reliably achieve the required level of accuracy in the 14-bit 50 MS / s mode and the 10-bit 70 MS / s mode, respectively do. FIG. 6 shows reference currents and reference voltage generators used in SHA, MDAC, and flash ADCs, and can be integrated on-chip to enable various SoC applications. If a single reference voltage driving circuit is applied to MDAC and flash ADC, there is a problem of reference voltage instability due to mixed noise of switch noise due to different accuracy specifications and load conditions, so that the corresponding 2.2V _{P -P} input signal It is difficult to secure a signal fixing performance satisfying a high resolution of 14 bits. To solve this problem, high bandwidth and power consumption of the reference voltage driving circuit are required. The ADC according to the embodiment of the present invention has two reference voltage driving circuits implemented with a single reference voltage by separating only the reference voltage driving circuit used in the amplification operation of the MDAC and the flash ADC operation.

As shown in FIG. 6, since the problem of instability due to signal interference is solved through the separated reference voltage driving circuit, sufficient fixing performance can be ensured by only consuming less power of the reference voltage connected to the high resolution MDAC. In addition, on-chip RC filters of 20Ω and 200pF inside the chip and an additional bypass capacitor of 0.1uF outside the chip are simultaneously connected to solve noise and glitch problems caused by charge and discharge of the switch, It can be supplied to the entire ADC. On the other hand, in consideration of the diversity of the user environment, it is possible to correct the reference current and voltage value by combining 3-bit digital codes. In addition, the reference voltage applied from the outside, rather than the reference voltage integrated in the system, .

7 is a chip and layout photograph of a multimode pipelined ADC according to an embodiment of the present invention.

For high performance CIS applications, an ADC that implements both 14-bit 50 MS / s and 10-bit 70 MS / s mode operation can be fabricated using a 0.13-μm CMOS process. The overall chip and layout photograph of the ADC according to the embodiment of the present invention is as shown in FIG. 7, and the chip area excluding the input / output pads is 1.17 mm ² . The 370pF MOS decoupling capacitors are integrated on-chip in the idle space except for each circuit block space which constitutes the entire ADC, minimizing interference between each circuit block, EMI problem, power supply voltage and noise in high-speed operation. The prototype ADC consumes 192.9 mW in 14-bit 50 MS / s mode and 184.9 mW in 10-bit 70 MS / s mode.

As shown in FIG. 8A, differential non-linearity (DNL) and integral non-linearity (INL) are 0.79 LSB and 2.54 LSB maximum in the 14-bit mode, respectively. Respectively, at the maximum of 0.53LSB and 0.44LSB. 9A and 9B show signal spectra measured by applying differential input signals of 4 MHz in the 14-bit 50 MS / s mode and the 10-bit 70 MS / s mode, which are two modes of the prototype ADC, respectively. Figures 10 (a) and (b) show the measured dynamic performance of the proposed prototype ADC. 10 (a) shows the case where the operation speed of the ADC is increased from 10MS / s to 50MS / s in 14-bit mode and when it is increased from 10MS / s to 70MS / s in 10-bit mode, To-noise-and-distortion ratio (SNDR) and spurious-free dynamic range (SFDR). SNDR and SFDR for the differential inputs of the prototyped ADCs measured during the increase of the operating speed to 50 MS / s and 70 MS / s respectively in the two modes are maintained at 68.5 dB and 86.7 dB respectively in 14 bit mode, Respectively, at 60.9 dB and 78.2 dB, respectively. 10 (b) shows the SNDR and SFDR when increasing the input frequency at an operating speed of 50MS / s in 14-bit mode and an operating speed of 70MS / s in 10-bit mode, respectively. When increasing the input signal to the Nyquist frequency, the SNDR and SFDR measured in the 14-bit mode are maintained at more than 64.4 dB and 82.3 dB, respectively, and remain at 58.8 dB and 71.1 dB or more in 10-bit mode.

On the other hand, the theoretical maximum SNR _thermal can be expressed by Equation (3). Equation 3 represents the magnitude (V _rms ) of the sinusoidal input signal having the peak-to-peak value of V _{P -P} in Equation 4, the magnitude (N _Q ) of the quantization noise at 14 bits in Equation 5, 6, and the magnitude (N _T ) of noise introduced into the ADC input due to the thermal noise of the sampling switch and amplifier of SHA and MDAC1.

In the above equation, C _S represents the sampling capacitance used in SHA and MDAC1, C _CS represents the load capacitance of SHA, C _CM1 represents the frequency compensation capacitance used for MDAC1, and its values are 6 pF, 6.5 pF and 1 pF, respectively, The theoretical SNR _thermal calculated by substitution is 75.5dB.

11 shows the noise observed from the input obtained by analyzing the histogram of the output digital code after connecting the differential input of the prototype ADC. That is, the noise is measured based on 16,384 output codes in the 14-bit 50 MS / s mode, and the measured noise reference (N _I ) is 1.20 LSB _rms . At this time, the SNR _measurements obtained by substituting the equations (4) and (5) and the measured input reference noise into Equation (7) is 73.6 dB.

This value is about 2dB difference from the theoretically obtainable SNR _thermal , so it can be confirmed that the theoretical calculation value is similar to the measured value. On the other hand, in the case of 10-bit 70 MS / s mode, the input reference noise was measured to be sufficiently smaller than the 1 LSB level of 10 bits because it cut off the last stage with little effect on noise.

Table 1 summarizes the major performance measurement results of the ADC according to the embodiment of the present invention. Table 2 compares the performance of the 14-bit ADC with the previously disclosed ADC. It exhibits a high SNDR of 60.9dB in 10bit mode, a relatively low power consumption of 192.9mW and a high SNDR of 68.5dB, with a high resolution of 14 bits and an operating speed of 50MS / s. It achieves relatively high dynamic performance while simultaneously realizing 14 bit 50MS / s in still image mode and 10 bit 70MS / s in video image mode. At the same time, it can instantly apply to high performance CIS by minimizing area, power consumption and noise components .

A CMOS image sensor according to an embodiment of the present invention may include the ADC. By using a low noise, dual-mode, four-stage pipelined ADC that simultaneously implements 14-bit 50MS / s in still image mode and 10-bit 70MS / s in video image mode, one ADC can implement two image modes.

Claims (13)

In an ADC having a pipeline structure composed of N stages including a plurality of MDACs and a plurality of flash ADCs,
The number of bits determined by the ADC is controlled by sequentially interrupting one or more stages including the MDAC and the flash ADC from the last stage,
The MDAC in the first stage and the MDAC in the second stage share one amplifier,
The amplifier shared by the MDAC of the first stage and the MDAC of the second stage,
It consists of two pairs of NMOS inputs,
Wherein the second NMOS input stage of the first stage of the amplifier is alternately initialized to a predetermined bias voltage. The method according to claim 1,
The MDAC and flash ADC of the last stage each include a cutoff switch in the bias circuit,
Wherein the last stage MDAC and flash ADC are interrupted by the respective blocking switch. The method according to claim 1,
And an input stage SHA using an amplifier to which a gain boosting technique is applied. The method of claim 3,
The amplifier used for the input stage SHA includes:
Wherein the NMOS single gain boosting amplifier has a PMOS input and the PMOS single gain boosting amplifier is a folded-cascode amplifier having an NMOS input. The method of claim 3,
The amplifier used for the input stage SHA includes:
The ADC reduces the transconductance of the current source transistor to the maximum within the saturation region and maximizes the transconductance of the input transistor within the saturation region to minimize amplifier noise. delete delete The method according to claim 1,
The amplifier shared by the MDAC of the first stage and the MDAC of the second stage,
It consists of two pairs of NMOS inputs,
Wherein when the two NMOS input stages are selected, a clock whose phases overlap is used. The method according to claim 1,
The amplifier shared by the MDAC of the first stage and the MDAC of the second stage,
The ADC reduces the transconductance of the current source transistor to the maximum within the saturation region and maximizes the transconductance of the input transistor within the saturation region to minimize amplifier noise. The method according to claim 1,
And a reference current generator and a reference voltage generator in which a driving circuit of a reference voltage used for amplifying the plurality of MDACs and a driving circuit of a reference voltage used for operation of the plurality of flash ADCs are separated. 11. The method of claim 10,
Wherein the reference current and the reference voltage generator are integrated on-chip. The method according to claim 1,
Wherein the ADC selectively uses an internally integrated reference voltage or an externally applied reference voltage. 12. A CMOS image sensor comprising the ADC of any one of claims 1 to 5 and 8 to 12.

Images