KR101594672B1 - Display device - Google Patents

Abstract

A display device and a method for manufacturing and testing the display device according to an embodiment of the present invention include a display panel including a non-display area and a display area; An odd data shorting bar and odd data link interconnection formed in the non-display area and connected to each other, an odd gate shorting bar and an odd gate interconnection interconnection connected to each other, an even data shortening bar connected via a first interconnection electrode, An even gate shorting bar and even gate link wiring connected through; A data line formed in the display area and connected to the odd and even data link wiring through a gate line connected to the odd and even gate link wiring and a third connecting electrode; And a protective electrode formed on the odd-even data link wiring and the odd-even gate link wiring.

Description

Display device {DISPLAY DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device and a manufacturing method and a testing method of the display device.

The display device manufacturing process includes a process of manufacturing a TFT-formed substrate and a module process of assembling a circuit PCB or the like for driving the substrate. Then, the defect inspection process is performed for each process.

First, when the substrate on which the TFT is formed is completed, an inspection process called an array test process is performed to inspect TFT defects, pixel pattern defects, line disconnection, and the like. The panel inspection process is performed to check whether the panel is abnormal before assembling the circuit PCB. This is called panel inspection process.

In the panel inspecting process, defects due to foreign objects that may appear in the active region of the panel and defects of optical characteristics due to the partial variation of the thickness of the active region, point defects due to TFT defects, A line defect due to disconnection of the data line, and the like, to determine whether the panel is good or defective.

Panel inspection methods include A / P (Auto Probe) inspection method, vision inspection method and Shoting bar inspection method.

The shorting bar inspection method is a method of inspecting a panel by bundling a gate pad and a data pad of a panel with a shorting bar and then applying an inspection signal to each line.

The shorting bar inspection method solves the drawbacks of the A / P (Auto Probe) inspection method and the vision inspection method. However, after the inspection of the panel, the shorting bars are electrically connected to trimming lines trimming lines or cutting lines), the odd electrodes and neighboring even electrodes are melted and short-circuited to each other. Particularly, as the size of the panel is miniaturized, the gap between the pads becomes narrower, and the electrodes are more easily short-circuited when the cutting line is cut.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a display device for preventing a short circuit between pads in a process of cutting pads, a method of manufacturing the display device, and an inspection method.

It is another object of the present invention to provide a display device for protecting the electrodes of the pad portion, a manufacturing method and an inspection method of the display device in the step of cutting the pad portion.

An embodiment of the present invention is a display device including: a gate line and a data line which are formed in a display region and intersect each other and define a unit pixel region; A pixel electrode and a common electrode which form a transverse electric field between each other in the unit pixel region; A data shorting bar formed in a non-display area in parallel with the gate line, and a gate shorting bar formed in a non-display area parallel to the data line; A gate shorting bar for connecting the gate shorting bar and the gate line to each other, a data link wiring for connecting the data shorting bar and the data line to each other, A gate pad and a data pad formed on the gate link wiring and the data link wiring; And a protective electrode covering the upper gate link wiring and the data link wiring on the gate link wiring and the data link wiring.

In an embodiment of the present invention, the protective electrode overlaps with a cutting line for cutting the shorting bar from the display area.

An embodiment of the present invention further comprises a gate pad and a data pad each connected to the gate link wiring and the data link wiring.

An embodiment of the present invention is characterized in that the protective electrode is formed between the gate shorting bar and the gate pad and is formed between the data shorting bar and the data pad. And the electrode is composed of the pixel electrode or the transparent electrode constituting the common electrode.

The display device according to the embodiment of the present invention is characterized in that the protective electrode is formed on every gate link wiring and data link wiring.

The embodiment of the present invention is characterized in that the gate link wiring is composed of an odd gate link wiring and an even gate link wiring, the data link wiring is composed of an odd data link wiring and an even data link wiring, And the data link wiring is constituted by a protective electrode.

According to the embodiment of the present invention, the odd pads and the even pads are distinguished from each other among the pads, and the arrangement structure between them is changed to increase the interval between the pads. In addition, in the cutting line cutting step, the interval between the electrodes of the pad is designed to increase, thereby preventing a short circuit between the electrodes. Further, it is possible to prevent the electrodes of the pad portion from being short-circuited by melting in the cutting line cutting step. In addition, the embodiment can protect the electrode of the pad portion in the cutting line cutting process.

1 to 4 are views for explaining an arrangement structure of electrodes of a display panel according to a first embodiment of the present invention.
Fig. 5 is a cross-sectional view taken along a dotted line AB in Fig.
Fig. 6 is a cross-sectional view taken along the dotted line AB in Fig.
7 is a cross-sectional view of a pixel region cut out from a non-display region and a display region.
8 to 11 are views for explaining the arrangement structure of the electrodes of the display panel according to the second embodiment of the present invention.
12 is a sectional view taken along a dotted line AB of FIG. 11. FIG. 13 is a view for explaining an arrangement structure of electrodes of a display panel according to a third embodiment of the present invention.
14 to 17 are views for explaining an arrangement structure of electrodes of a display panel according to a fourth embodiment of the present invention.
18 is a cross-sectional view taken along a dotted line in Fig.
19 is a view for explaining a process of inspecting a display panel according to an embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a display device, a method of manufacturing a display device, and an inspection method according to embodiments of the present invention will be described in detail with reference to the drawings. The following embodiments are provided by way of example so that those skilled in the art can fully understand the spirit of the present invention. Therefore, the present invention is not limited to the embodiments described below, but may be embodied in other forms. In the drawings, the size and thickness of an apparatus may be exaggerated for convenience. Like reference numerals designate like elements throughout the specification.

≪ Electrode Forming Method of Display Panel According to First Embodiment of Present Invention >

The arrangement structure of the electrodes of the display panel 100 according to the first embodiment of the present invention will be described with reference to FIGS. 1 to 4. FIG.

The display panel 100 can be a transparent insulating substrate and is divided into a non-display area 100a and a display area 100b.

Referring to FIG. 1, the non-display area 100a includes an odd data slotting (ODS), an odd gate shorting bar (OGS), an odd and even data link wiring (ODL, EDL) , EGL) may be disposed.

Each of the odd and even data link lines (ODL, EDL) may be formed of a plurality of each other and arranged alternately with each other. Further, each of the odd-numbered and even-numbered gate wiring lines OGL and EGL may be formed of a plurality of each other and arranged alternately with each other.

The gate link lines OGL and EGL connect the gate shorting bars OGS and EGS and the gate line GL to each other and the data link lines ODL and EDL connect the data shorting bars ODS and EDS, The lines DL can be connected to each other.

Specifically, the odd data link line (ODL) may be formed directly connected to the odd data shorting bar (ODS), and they may be arranged in directions perpendicular to each other. Also, the odd gate link line OGL may be formed directly connected to the odd gate shorting bar OGS, and they may be arranged in directions perpendicular to each other.

Each of the odd and even gate wiring lines OGL and EGL may be connected to each other in a one-to-one correspondence with each of the gate lines GL.

The even data link line EDL and the even gate line EGL may be formed in a region corresponding to the trimming line TL in another term of a cutting line among the non-display region 100a.

The display region 100b may be provided with a gate line GL formed directly connected to the odd and even gate link lines OGL and EGL. The gate line GL may be perpendicular to the odd gate shorting bar OGS and may be parallel to the odd and even gate link lines OGL and EGL.

(ODL), odd and even gate link lines (OGL, EGL), and display area (ODS) on the non-display area 100a, the odd data shorting bar ODS, the odd gate shorting bar OGS, the odd and even data link wirings ODL and EDL, 100b may be formed of a gate electrode material that is the same material, and all the electrodes may be formed in a single process. Specifically, a metal material including chromium, molybdenum, tantalum, or antimony may be deposited on the entire surface of the substrate, and the electrodes may be patterned by a mask process.

Referring to FIG. 2, an even data display slot (EDS) and an even gate shorting bar (EGS) may be formed in the non-display area 100a.

The even data shining bar (EDS) may be formed parallel to the odd data shorting bar (ODS). The even gate shorting bar (EGS) may be spaced apart from and parallel to the odd gate shorting bar (OGS).

A plurality of data lines DL may be formed on the display region 100b, and they may be formed so as to intersect with the lines GL. In addition, the data lines DL may be formed in the same line as the odd and even data link lines ODL and EDL. The data lines DL may be spaced apart from the odd and even data link lines ODL and EDL.

The even data gate electrode (EDS), the even gate shorting bar (EGS), and the data line (DL) may be formed as source or drain electrodes, and all the electrodes may be formed in a single process.

On the other hand, the insulating material is first deposited on the display panel 100 before forming the even data shouting bar (EDS), the even gate shorting bar (EGS), and the data line (DL). Specifically, after forming a gate insulator, which is an inorganic insulating material such as silicon nitride or silicon oxide, a metal containing chromium or the like is deposited on the gate insulating film, patterned by a mask process, ), An even gate shorting bar (EGS), and a data line (DL).

(ODS), odd and even data link wiring (ODL, EDL), odd gate shorting bar (OGS), odd and even gate link wiring (OGL, EGL), and odd data sharing wiring A second step of forming a gate insulating film after the first step, and a second step of forming an even data gate (EDS), an odd and even gate An electrode may be formed on the substrate 100 through a third process of forming a data line DL and an even gate shorting bar (EGS). Accordingly, the electrode formed in the first process and the electrode formed in the third process can be formed in different layers.

Referring to FIG. 3, a data pad DP, a gate pad GP, and a contact electrode CE may be formed on the non-display region 100a.

The data pad DP may be formed on the gate link lines OGL and EGL and the gate pad GP may be formed on the data link lines ODL and EDL.

The gate pad GP may be connected to the gate link lines OGL and EGL and the data pad DP may be connected to the data link lines ODL and EDL.

After the display panel 100 is inspected, data and gate signals may be applied to the data pad and the gate pads (DP, GP) to drive corresponding pixels. The connection electrodes CE may include first to third connection electrodes CE1, CE2, and CE3. The first connection electrode CE electrically connects the even data bus (EDS) and the even data link wiring (EDL). The second connection electrode CE2 electrically connects the odd and even data link lines ODL and EDL to the data line DL. Also, the third connection electrode CE3 electrically connects the even gate shorting bar EGL and the even gate link EGL.

After forming the even data gate electrode (EDS), the even gate shorting bar (EGS) and the data line (DL) described in FIG. 2, an insulating material is applied on the data lines DL to form a passivation layer A connection electrode CE, which is an ITO (Indium Tin Oxide) electrode material, can be formed as shown in FIG.

The connection electrodes CE electrically connect the electrodes formed on different layers through the contact holes. Specifically, the odd and even data link lines (ODL, EDL) and the data lines (DL) exposed to the outside through the contact holes formed by etching the passivation layer and a part of the gate insulating film are electrically connected to each other, Tinguba (EGS) and even gate link wiring (EGL) can be electrically connected to each other.

4, in the non-display area 100a, the gate link lines OGL and EGL and the data link lines ODL and EDL are formed on the gate link lines OGL and EGL and the data link lines ODL and EDL, A shield electrode (SE) may be formed. The protective electrode SE may be formed in a region overlapping the trimming line TL to cut off the gate and data shutting bars OGS, EGS, ODS, and EDS from the display area 100b. The protective electrode SE may be formed on all of the gate link lines OGL and EGL and the data link lines OGL and EGL and specifically includes the upper area of the odd and even data link lines ODL and EDL, And the even gate line (OGL, EGL). The protective electrode SE may be formed between the gate shorting bar OGS and the gate pad GP and may be formed between the data shorting bar ODS and the data pad DP.

The protective electrode SE may be formed of a transparent electrode constituting the pixel electrode Pix and the common electrode Com, and may specifically be an ITO electrode material.

5 is a cross-sectional view taken along line A-B in Fig.

The process of forming the electrode structure according to the first embodiment of the present invention will be described with reference to FIG.

The substrate 100 is divided into a non-display area 100a and a display area 100b and a trimming line TL area is indicated by a one-dot chain line in the non-display area 100a.

In the first step, an odd data shorting bar (ODS) and an even data link wiring (EDL) of the gate electrode material may be formed on the substrate 100.

In the second step, a gate insulating film (GI) which is an inorganic insulating material such as silicon nitride or silicon oxide can be formed.

In the third step, a metal containing chromium or the like is deposited on the gate insulating film GI, and patterned by a mask process to form an even data bus (EDS), which is a source or drain electrode material, and an even data line DL .

In the fourth step, a passivation layer (PA), which is a protective film, may be formed by applying an insulating material on the substrate 100.

In the fifth step, a contact hole is formed in the gate insulating film (GI) and the passivation layer (PA), and then a connecting electrode (CE), which is an ITO material, is formed to form an even data shunt bar (EDS) A data pad DP which is an ITO material may be formed to electrically connect the even data lines DL (even) to connect the ITO electrode material and the even data link lines EDL to each other.

6 is a cross-sectional view taken along line A-B of Fig.

Referring to FIG. 6, a process of forming the protective electrode according to the first embodiment of the present invention will be described.

In FIG. 6, a structure different from FIG. 5 is a protective electrode SE, and a protective electrode SE, which is an ITO electrode material, may be further formed in a region corresponding to the trimming line TL. Since the protective electrode SE is an ITO electrode material, it can be formed at the same time as the connection electrode CE and the data pad DP formed in the fifth step described above. FIG. 7 is a cross- And the electrode structure of the pixel region of the display region.

The display region 100b of the substrate 100 may be formed with a gate line GL and a data line DL which define a unit pixel region intersecting with each other. A pixel electrode Pix and a common electrode Com, which form a transverse electric field between each other, may be formed in the unit pixel region.

In the non-display area 100a, odd and even gate shorting bars (OGS, EGS) parallel to the data line DL may be formed, and odd and even data sharing bars ODS, EDS) may be formed.

7, the pixel region on the display region 100b includes a gate electrode G formed on the substrate 100, a gate insulating film GI formed on the gate electrode G, (PA) covering the thin film transistor region and the passivation layer (PA). The passivation layer (PA) is composed of the active electrode (Active) formed on the active layer (Active) and the source and drain electrodes And a common electrode Com formed on the passivation layer PA and a pixel electrode Pix which is in contact through a contact hole.

In the pixel region having such a common electrode (Com) top structure, the gate electrode G is connected to the odd data shorting bar (ODS) and odd data link wiring (EDL) formed in the first step in FIGS. As shown in FIG.

Further, the source and drain electrodes S and D may be formed simultaneously with the even data shortening bar EDS and the even data line DL formed in the third process in FIGS. 5 and 6.

The pixel electrode Pix and the common electrode Com may be formed at the same time when any one of the connection electrode CE, the data pad DP, and the protective electrode SE is formed.

According to the first embodiment of the present invention, when cutting the trimming line TL, the protective electrode SE is connected to the odd and even data link lines ODL and EDL and the odd and even gate link lines OGL, EGL) is melted and spreads to the peripheral region and is prevented from being short-circuited to the peripheral electrodes.

The reason for this is that the ITO electrode material is stronger than the gate electrode, and the degree of melting of the trimming line TL is less than that of the gate material. Therefore, by forming the protective electrode SE made of the ITO electrode material in the upper region of the odd and even data link wiring (ODL, EDL) and the upper portion of the odd and even gate wiring wiring (OGL, EGL) can do.

Also, when a signal is transmitted from the non-display area 100a to the display area 100b, the lines on the non-display area 100a are denser than the display area 100b, However, when the electrode is arranged according to the embodiment of the present invention, it is possible to prevent the problem.

≪ Method of Forming Electrode of Display Panel According to Second Embodiment of the Present Invention &

The arrangement structure of the electrodes of the display panel 100 according to the second embodiment of the present invention will be described with reference to FIGS. 8 to 12. FIG.

Hereinafter, the odd data line is a line connected to the odd data link wiring, the even data line is a line connected to the even data link wiring, the odd gate line is a line connected to the odd gate link wiring, It is a line connected with wiring.

In describing the second embodiment of the present invention, the same components as those of the first embodiment are denoted by the same names, and detailed explanations of the same effects are omitted.

The display panel 100 is divided into a non-display area 100a and a display area 100b.

8, an odd data shorting bar (ODS), an odd gate shorting bar (OGS), an odd data link wiring (ODL) and an odd gate link wiring (OGL) may be disposed in the non-display area 100a .

And may be spaced apart from each other by a suitable distance so that even data link wiring (not shown) may be disposed in a region between each of the plurality of odd data link wirings (ODL). And may be spaced apart from each other by an appropriate distance so that an even gate link wiring (not shown) may be disposed in an area between each of the odd gate link lines OGL.

The odd data link line (ODL) may be formed directly connected to the odd data shorting bar (ODS), and they may be arranged in directions perpendicular to each other. Also, the odd gate link line OGL may be formed directly connected to the odd gate shorting bar OGS, and they may be arranged in directions perpendicular to each other.

Each odd gate link line OGL may be connected to each of the gate lines GL.

An odd gate line GL (odd) formed directly connected to the odd gate link line OGL may be disposed in the display area 100b. The gate line GL may be perpendicular to the odd gate shorting bar OGS and may be parallel to the odd gate link line OGL.

An even gate line GL (even) to be connected to an even gate line wiring (not shown) to be formed later in the gate line GL can be extended not only on the display region 100b but also on the non-display region 100a have. That is, the area between the boundary line of the trimming line TL and the display area 100b in the non-display area 100a. However, the even gate lines GL (even) do not correspond to the trimming lines TL.

The odd data sharing line ODS, the odd gate shorting bar OGS, the odd data link line ODL, the odd gate link line OGL and the gate line GL on the display area 100b on the non- May all be formed of the same material as the gate electrode material, and all the electrodes may be formed in a single process.

Referring to FIG. 9, the non-display area 100a may include an even data shining bar (EDS) and an even gate shortening bar (EGS). The even data shining bar (EDS) may be formed parallel to the odd data shorting bar (ODS). The even gate shorting bar (EGS) may be formed parallel to and spaced apart from the odd gate shorting bar (OES).

A plurality of data lines DL may be formed on the display region 100b, and they may be formed to intersect with the gate lines GL. The data lines DL may be formed parallel to the odd data link lines ODL. The data lines DL may be spaced apart from the odd data link lines ODL.

The even data gate electrode (EDS), the even gate shorting bar (EGS), and the data line (DL) may be formed as source or drain electrodes, and all the electrodes may be formed in a single process.

On the other hand, the insulating material is first deposited on the display panel 100 before forming the even data shouting bar (EDS), the even gate shorting bar (EGS), and the data lines (DL).

Referring to FIG. 10, an even data link line (EDL) may be formed on the non-display area 100a to connect an even data bus (EDS) and even data lines (DL) to each other. The even data link line EDL may be formed in an area between the odd data link lines ODL. That is, the even data link lines (EDLs) may be alternately arranged with the odd data link lines (ODLs). An even gate line (EGL) may be formed to connect the even gate line (EGS) and even gate line (GL) to each other. The even gate link wiring EGL may be formed in an area between the odd gate wiring lines OGL. That is, the even gate line interconnects EGL may be arranged alternately with the odd gate interconnect lines OGL.

The even data link line (EDL) connects the even data shortening line (EDS) and the even data line (DL) through the link wiring contact hole. The even gate link line (EGL) (EGS) and even gate lines GL (even).

Meanwhile, the even data link wiring (EDL) and the even gate wiring wiring (EGL) may be connected to the electrodes formed on the lower layer through the contact hole.

The even data link wiring (EDL) and the even gate wiring wiring (EGL) may be formed by a single process using an ITO electrode material.

Referring to FIG. 11, a connecting electrode CE may be formed on the non-display region 100a. The connection electrode CE may electrically connect the odd data link line ODL and the odd data line DL (odd).

The connection electrodes CE electrically connect the electrodes formed on different layers through the contact holes.

The even data link wiring (EDL), the even gate wiring wiring (EGL), and the connecting electrode CE shown in FIGS. 10 and 11 may be formed at one time by the same process, which is made of a transparent electrode material, specifically ITO electrode material.

12 is a cross-sectional view taken along the line indicated by A-B in Fig.

12, the substrate 100 is divided into a non-display area 100a and a display area 100b, and a trimming line TL area is indicated by a one-dot chain line in the non-display area 100a.

In a first step, an odd data shorting bar (ODS) of the gate electrode material may be formed on the substrate 100.

In the second step, a gate insulating film (GI) which is an inorganic insulating material such as silicon nitride or silicon oxide can be formed.

In the third step, a metal containing chromium or the like is deposited on the gate insulating layer GI, and patterned by a mask process to form an even data bus (EDS) or a even data line (DL) .

In the fourth step, a passivation layer (PA), which is a protective film, may be formed by applying an insulating material on the substrate 100.

In the fifth step, a contact hole is formed in the passivation layer (PA), and an even data link line (EDL), which is an ITO material, is formed to electrically connect the even data bus (EDS) .

In the second embodiment according to the present invention, uneven data link wiring (EDL) made of an ITO electrode material rather than a gate electrode is disposed in an area between odd data link lines (ODL), unlike the first embodiment. That is, the even data link wiring EDL and the even gate wiring wiring EGL may be the protective electrode CE described in the first embodiment. Thus, even when the odd data link line ODL is melted and spread to the peripheral area at the time of cutting the trimming line TL due to a sufficient distance between the odd data link lines ODL made of the gate electrode material, . Likewise, even-numbered gate wiring lines EGL made of an ITO electrode material other than the gate electrodes are disposed in the area between the odd gate wiring lines OGL, so that the gap between the odd gate wiring lines OGL made of the gate electrode material is sufficient . Therefore, when the trimming line TL is cut, the odd gate wiring line ODL can be prevented from being melted and short-circuited while spreading to the peripheral region.

On the other hand, since the odd data link wiring (ODL) and the even data link wiring (EDL) are formed on different layers, it is possible to prevent the electrodes from being short-circuited even if they are melted. Therefore, the interval between the odd data link line ODL and the even data link line EDL can be narrowed, and the interval of the data lines DL can be narrowed accordingly. Further, the effects obtained by forming the odd gate link wiring (OGL) and the even gate link wiring (EGL) in different layers are the same as described above.

≪ Method of Forming Electrode of Display Panel According to Third Embodiment of the Present Invention &

The arrangement structure of the electrodes of the display panel 100 according to the third embodiment of the present invention will be described with reference to FIG.

In describing the third embodiment of the present invention, the same components as those of the first and second embodiments are denoted by the same names, and detailed description of the same effects will be omitted.

Referring to FIG. 13, a shield electrode (SE) may be formed in the non-display region 100a. The protective electrode SE may be formed in a region corresponding to the trimming line TL. Also, the protective electrode SE may be formed on the odd data link wiring (ODL) upper region and the odd gate link wiring (OGL) upper region.

The protective electrode SE may be an ITO electrode material having a relatively higher rigidity than the gate electrode material.

When the trimming line TL is cut, the protective electrode SE is formed such that the odd data link wiring ODL and the odd gate wiring OGL disposed at the lower portion thereof are melted and short-circuited to the peripheral electrodes while spreading to the peripheral region .

<Method of Forming Electrode of Display Panel According to Fourth Embodiment of Present Invention>

The arrangement structure of the electrodes of the display panel 100 according to the fourth embodiment of the present invention will be described with reference to FIGS. 14 to 18. FIG.

In describing the fourth embodiment of the present invention, the same components as those of the first to third embodiments are denoted by the same names, and a detailed description of the same effects will be omitted.

The display panel 100 is divided into a non-display area 100a and a display area 100b.

14, an odd data shorting bar (ODS), an odd gate shorting bar (OGS), an odd data link wiring (ODL), and an odd gate link wiring (OGL) may be disposed in the non-display area 100a .

And may be spaced apart from each other by a suitable distance so that even data link wiring (not shown) may be disposed in a region between each of the plurality of odd data link wirings (ODL). And may be spaced apart from each other by an appropriate distance so that an even gate link wiring (not shown) may be disposed in an area between each of the odd gate link lines OGL.

The odd data link line (ODL) may be formed directly connected to the odd data shorting bar (ODS), and they may be arranged in directions perpendicular to each other. Also, the odd gate link line OGL may be formed directly connected to the odd gate shorting bar OGS, and they may be arranged in directions perpendicular to each other.

Each odd gate link line OGL may be connected to each of the gate lines GL.

An odd gate line GL (odd) formed directly connected to the odd gate link line OGL may be disposed in the display area 100b. The odd gate line GL (odd) may be perpendicular to the odd gate shorting bar OGS and may be parallel to the odd gate link line OGL.

A gate line GL (even) to be connected to an even gate line wiring (not shown) to be formed later in the gate line GL extends not only on the display region 100b but also on the non-display region 100a . That is, the area between the boundary line of the trimming line TL and the display area 100b in the non-display area 100a. However, the even gate lines GL (even) do not correspond to the trimming lines TL.

The odd data sharing line ODS, the odd gate shorting bar OGS, the odd data link line ODL, the odd gate link line OGL and the gate line GL on the display area 100b on the non- May all be formed of the same material as the gate electrode material, and all the electrodes may be formed in a single process.

Referring to FIG. 15, the non-display area 100a may be formed with an even data sharing electrode (EDS), an even data link wiring (EDL), and an even gate shorting bar (EGS). The even data link line (EDL) may be extended from the even data shining bar (EDS) and formed at the same time in the same process. The even data shining bar (EDS) may be formed parallel to the odd data shorting bar (ODS). The even gate shorting bar (EGS) may be formed parallel to and spaced apart from the odd gate shorting bar (OES).

A plurality of data lines DL may be formed on the display region 100b, and they may be formed to intersect with the gate lines GL. The odd data lines DL (odd) may be formed parallel to the odd data link lines ODL in the data lines DL. The even data lines DL (even) can be directly connected to the even data link lines EDL, and can be formed at the same time and in the same material at the same time. The odd data lines DL (odd) may be formed apart from the odd data link lines ODL.

The even data gate electrode (EDS), the even gate shorting bar (EGS), and the data line (DL) may be formed as source or drain electrodes, and all the electrodes may be formed in a single process.

On the other hand, the insulating material is first deposited on the display panel 100 before forming the even data shouting bar (EDS), the even gate shorting bar (EGS), and the data lines (DL).

16, an even gate line EGL composed of an ITO electrode material is formed on a non-display region 100a, and an even gate shorting gate EGS and even gate lines GL (even) are formed through a contact hole. Can be electrically connected to each other. The connection electrode CE may electrically connect the odd data link line ODL and the odd data line DL d via a contact hole.

Referring to FIG. 17, a data pad DP and a gate pad GP composed of an ITO electrode material may be formed on the non-display area 100a, and a protective electrode SE may be formed.

18 is a sectional view taken along the line A-B in Fig.

18, the substrate 100 is divided into a non-display area 100a and a display area 100b. In the non-display area 100a, a trimming line TL area is indicated by a one-dot chain line.

In a first step, an odd data shorting bar (ODS) of the gate electrode material may be formed on the substrate 100.

In the second step, a gate insulating film (GI) which is an inorganic insulating material such as silicon nitride or silicon oxide can be formed.

In the third step, a metal containing chromium or the like is deposited on the gate insulating film GI and patterned by a mask process to form a soda or drain electrode material, such as an even data bus (EDS), an even data link wiring (EDL) The data line DL can be formed.

In the fourth step, a passivation layer (PA), which is a protective film, may be formed by applying an insulating material on the substrate 100.

In the fifth step, after a contact hole is formed in the passivation layer PA, a data pad DP, which is an ITO material, may be formed and electrically connected to the even data link line EDL.

Further, the protective electrode SE can be formed on the region corresponding to the trimming line TL. The protective electrode SE is an ITO electrode material. The protective electrode SE may be formed at one time in the same process as the data pad DP, or may be integrally formed.

The third embodiment according to the present invention is different from the first embodiment in that an even data link wiring (EDL) composed of a source drain electrode material rather than a gate electrode is disposed in an area between odd data link wiring lines (ODL). Since the even and odd data link lines EDL and ODL are formed on different layers and the source and drain electrode materials forming the even data link lines EDL are stronger than the gate electrode materials, It is possible to prevent a phenomenon that the adjacent gate electrodes are short-circuited due to the melting of the adjacent gate electrodes at the time of trimming line TL. Further, by forming the protective electrode SE of the ITO electrode material in the region corresponding to the trimming line TL, the protective electrode SE is cut off from the trimming line TL by the odd data link wiring ODL ) And the odd gate wiring line (OGL) are melted and spread to the peripheral region and are prevented from being short-circuited to the peripheral electrodes.

<Inspection Procedure of Display Panel According to First to Fourth Embodiments of the Present Invention>

19 is a view for explaining a process of inspecting a display panel according to an embodiment of the present invention.

A process of inspecting the display panel 100 having the same structure as the first to third embodiments of the present invention will be described with reference to FIG.

The display panel 100 to be inspected is moved to the inspection area where the inspection data driver 110 and the gate driver 120 are arranged by the moving device of the A / P (Auto Probe) pin system.

A plurality of data checking probes 140 are arranged in the data driver 110 and a plurality of gate checking probes 150 are disposed in the gate driver 120.

The data check probe 140 is configured with a plurality of needle pins capable of electrical contact with the data TCP in which the data drive IC is mounted and the shorting bar formed in the non-display area 100a of the display panel 100 have.

Similarly, the gate inspection probe 150 includes a gate TCP on which the gate drive IC is mounted, and a plurality of needle pins capable of electrical contact with the shorting bar formed in the non-display area 100a of the display panel 100 .

The A / P pins (needles) are connected to the odd and even data display bars (ODS, EDS) and the odd and even gate shorting bars (OGS, EGS) on the non-display area 100a. Then, an inspection signal is applied to the odd and even data showting bars (ODS, EDS) and the odd and even gate show bars (OGS, EGS) to check whether the panel is defective.

At this time, a drive signal and a data signal may be applied in units of a shot bar, and a defect inspection such as a line defect or a point defect can be performed. In addition, the shorting bars can be divided into Data Shotting Bars (ODS, EDS) and Gate Shotting Bars (OGS, EGS), so they can be checked by data line (DL) or gate line (GL) . In addition, it is an inspection by the Shoting bar method, but there is an advantage that inspection freedom close to the conventional A / P pin contact method can be secured. In addition, since an inspection signal is applied to each pad unit, it is possible to prevent a line defect caused by a signal delay occurring in the conventional shorting bar system.

After the inspection is finished, the trimming line TL is cut to remove the shorting bar from the display panel 100.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

100 display panel
100a non-display area
100b display area
110 data driver
120 gate driver
140 Data Check Probe
150 Gate Check Probe

Claims (10)

A gate line and a data line arranged in a display region on the substrate and intersecting each other to define a unit pixel region;
A pixel electrode and a common electrode arranged in the unit pixel region;
A data shorting bar parallel to the gate line and disposed in a non-display area on the substrate; a gate shorting bar disposed in a non-display area parallel to the data line;
A gate shorting bar for connecting the gate shorting bar and the gate line to each other, a data link wiring for connecting the data shorting bar and the data line to each other,
A gate pad and a data pad arranged on the gate link wiring and the data link wiring;
And a protective electrode covering the gate link wiring and the data link wiring on the gate link wiring and the data link wiring,
Wherein the overlapping region of the gate link wiring and the data link wiring and the protective electrode overlaps a cutting line for cutting the shorting bar from the display region,
The data shotting bar comprising a first data showing slot and a second data shorting bar adjacent the first data slot,
The data link wiring includes a first data link wiring connected to the first data shorting bar and a second data link wiring connected to the second data shorting bar and adjacent to the first data link wiring,
Wherein the first data sharing electrode and the first data link wiring are disposed on a layer different from the second data sharing electrode and the second data link wiring with a gate insulating film therebetween. delete The method according to claim 1,
And a gate pad and a data pad respectively connected to the gate link wiring and the data link wiring. The method according to claim 1,
Wherein the protective electrode is disposed between the gate shorting bar and the gate pad, and is disposed between the data shorting bar and the data pad. The method according to claim 1,
Wherein the protective electrode comprises a transparent electrode constituting the pixel electrode or the common electrode. The display device according to claim 5, wherein the protective electrode is disposed on all of the gate link wiring and the data link wiring. The method according to claim 6,
Wherein the gate link wiring is constituted by a first gate link wiring and a second gate link wiring, and the second gate link wiring is constituted by a protective electrode. The method according to claim 1,
And the data line is disposed in the same layer as the second data link wiring. The method according to claim 1,
Wherein the gate line is disposed in the same layer as the first data link wiring. 8. The method of claim 7,
And the first gate link wiring is disposed on the same layer as the first data link wiring.

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