KR101576648B1 - Through-silicon via structure and predicting method for thermo-mechanical stress of the same - Google Patents

Abstract

The present invention relates to a through silicon via (TSV) structure, and a method for estimating thermo-mechanical stress of the TSV. The TSV structure comprises: a via hole formed in a vertical direction inside a silicon wafer; a conductor, a diffusion barrier, and an insulating layer sequentially arranged inside the via hole; and a copper overburden arranged in an upper part of the via hole.

Description

TECHNICAL FIELD [0001] The present invention relates to a silicon penetration electrode structure and a method of predicting thermomechanical stress of the silicon penetration electrode structure,

The present invention relates to a silicon penetrating electrode structure and a method for predicting thermomechanical stresses of the silicon penetrating electrode.

A three-dimensional integrated circuit (3D IC) is a new technology that integrates several things vertically into a single chip. Advantages of 3D ICs on a silicon-through-via (TSV) include improved packing density, reduced power consumption, wider bandwidth, and faster delivery speed. Copper is most commonly used as an additive to TSV due to its low resistivity of copper and good compatibility with copper wiring, and much effort has been focused on the development of the manufacturing process.

However, copper TSV poses many problems associated with degradation of device characteristics, yield, and long-term reliability. Copper diffuses rapidly in both silicon and silicon oxide, contaminating silicon devices. Discrepancies in the coefficient of thermal expansion (CTE) between the silicon wafer and the copper TSV lead to thermomechanical stresses in the copper TSV structure. The minority carrier lifetime of the active region is reduced by copper contamination diffused from the copper TSV during annealing at 300 DEG C for 5 minutes. The thermo-mechanical stress causes hole and electron mobility changes in the device, which can cause performance degradation. The delamination of TSV caused by thermal stresses was studied using other materials and structural designs: TSV diameter, TSV filling materials, type of dielectric materials, type of TSV (penetration-electrode etc.). Blind-vias, cylindrical). A dielectric liner was also determined by the cracking of the silicon substrates or by the thermo-mechanical stress, but the effect of the design parameters on cracking failure was barely reported. The stress distribution of the TSV structure was mainly studied by finite element analysis, while micro-Raman spectroscopy was able to determine only the thermomechanical stresses of the silicon surface.

On the other hand, in Korean Patent Laid-Open No. 10-2012-0104638 (regeneration of available integrated circuit chip area near through silicon vias), a substrate including vias passing through the substrate and a material introducing stress The manufacture of integrated circuit devices utilizes the regeneration of the available integrated circuit chip area near the penetrating electrodes.

The present invention relates to a semiconductor device comprising: a via hole formed in a silicon wafer in a vertical direction; A conductive layer, a diffusion barrier layer, and an insulating layer sequentially disposed in the via hole; And a copper overburden disposed at an upper portion of the via hole, the parameter being selected from the group consisting of a diameter of the via hole, a thickness of the insulating film, a thickness of the copper overburden, and combinations thereof. And a method of predicting the thermo-mechanical stress of the silicon penetration electrode.

However, the problems to be solved by the present invention are not limited to the above-mentioned problems, and other problems not mentioned can be clearly understood by those skilled in the art from the following description.

According to a first aspect of the present invention, there is provided a semiconductor device comprising: a via hole formed in a silicon wafer in a vertical direction; A conductive layer, a diffusion barrier layer, and a dielectric liner sequentially disposed in the via hole; And a copper overburden disposed at an upper portion of the via hole, the parameter being selected from the group consisting of a diameter of the via hole, a thickness of the insulating film, a thickness of the copper overburden, and combinations thereof. Wherein the stress of the silicon penetrating electrode is controlled by the first electrode.

According to a second aspect of the present invention, there is provided a method for predicting thermomechanical stress of a penetrating electrode using a silicon penetrating electrode structure according to the first aspect of the present invention, wherein a via hole diameter of the penetrating electrode, a thickness of the insulating film, Thermo-mechanical stresses of the silicon penetrating electrode, including preventing cracking of the penetrating electrode by predicting the stress of the silicon penetrating electrode by using a parameter selected from the group consisting of combinations thereof, Provides a prediction method.

According to one embodiment of the present disclosure, the silicon through-hole electrode structure (TSV) can reduce the maximum stress of the TSV as the via-hole diameter of the silicon through electrode decreases, and the diameter of the via- It can be used as a parameter for predicting the stress.

According to one embodiment of the present invention, as the thickness of the insulating layer of the silicon through electrode is increased, the maximum stress of the TSV may be lowered, and the thickness of the insulating layer may be used as a parameter for predicting the thermo-mechanical stress of the silicon through electrode.

According to one embodiment of the present disclosure, as the thickness of the copper overburden of the silicon through electrode is reduced, the maximum stress of the TSV may also decrease, and the thickness of the copper overburden is a parameter that predicts the thermo-mechanical stress of the silicon through electrode Can be used.

According to one embodiment of the present invention, in the silicon penetrating electrode, the maximum stress is predicted by a design parameter selected from the group consisting of the diameter of the via hole, the thickness of the insulating film, the thickness of the copper overburden, Thereby preventing cracks in the silicon through-hole electrode according to the present invention.

1 is a schematic diagram of a design parameter of a TSV in one embodiment of the present invention.
2A and 2B illustrate FEM modeling of a through-silicon via (TSV) in one embodiment of the present invention, wherein (a) the meshes of the model and the mesh at the critical interface, and (b) An example of the stress distribution calculated by ANSYS.
Figures 3a-3d are contour plots of the bottom edge of a TSV using different diameters, in one embodiment of the present invention: (a) 2 占 퐉, (b) 5 占 퐉, (c) 10 占 퐉, and d) 20 μm, where each aspect ratio is fixed at 10.
Figure 4 is a graph showing the maximum pomfilless stress as a function of the diameter and aspect ratio of the TSV, in one embodiment of the invention.
Figures 5A-5C are contour plots of the bottom edge of the TSV using different side slopes, respectively, in one embodiment of the present invention: (a) 88 占 (b) 89 占 and (c) 90 占, Wherein the diameter of each via is 10 탆.
Figure 6 is a graph showing the maximum pomfilless stress as a function of wall slope, in one embodiment of the invention.
Figures 7a to 7d, in the one embodiment of the invention, different SiO are contour plots at the bottom of the TSV edges with _two thicknesses: each of (a) 50 nm, (b ) 100 nm, (c) 200 nm, And (d) 500 nm, where each via diameter is 10 占 퐉.
8 is a graph showing the maximum pomposite stress as a function of SiO ₂ thickness and via diameter in one embodiment of the present invention.
Figure 9a and 9b, are yungak plot in accordance with the exemplary embodiment of the invention, the bottom of the TSV with each other, the step coverage of the SiO ₂ film (liner) edges: each of (a) 50% and (b) 100% , Wherein the diameter of each via is 10 탆.
10a-10d are, in one embodiment of the present disclosure, the lines of the lower edges of TSVs using different copper overburden thicknesses: (a) 0 占 퐉, (b) 0.5 占 퐉, , And (d) 5 占 퐉, where each via diameter is 10 占 퐉.
11 is a graph showing the maximum pomposite stress as a function of copper overburden thickness and via diameter in one embodiment of the present invention.

Hereinafter, embodiments and examples of the present invention will be described in detail with reference to the accompanying drawings, which will be readily apparent to those skilled in the art to which the present invention pertains. It should be understood, however, that the present invention may be embodied in many different forms and is not limited to the embodiments and examples described herein. In order to clearly illustrate the present invention, parts not related to the description are omitted, and similar parts are denoted by like reference characters throughout the specification.

Throughout this specification, when a part is referred to as being "connected" to another part, it is not limited to a case where it is "directly connected" but also includes the case where it is "electrically connected" do.

Throughout this specification, when a member is "on " another member, it includes not only when the member is in contact with the other member, but also when there is another member between the two members.

Throughout this specification, when an element is referred to as "including " an element, it is understood that the element may include other elements as well, without departing from the other elements unless specifically stated otherwise.

As used herein, the terms "about," " substantially, "and the like are used herein to refer to or approximate the numerical value of manufacturing and material tolerances inherent in the stated sense, Accurate or absolute numbers are used to prevent unauthorized exploitation by unauthorized intruders of the mentioned disclosure.

The term " step " or " step of ~ " as used throughout the specification does not imply " step for.

Throughout this specification, the term "combination (s) thereof " included in the expression of the machine form means a mixture or combination of one or more elements selected from the group consisting of the constituents described in the expression of the form of a marker, Quot; means at least one selected from the group consisting of the above-mentioned elements.

Throughout this specification, the description of "A and / or B" means "A or B, or A and B".

Hereinafter, embodiments of the present invention are described in detail, but the present invention is not limited thereto.

According to a first aspect of the present invention, there is provided a semiconductor device comprising: a via hole formed in a silicon wafer in a vertical direction; A conductive layer, a diffusion barrier layer, and an insulating layer sequentially disposed in the via hole; And a copper overburden disposed on the top of the via hole, wherein a parameter selected from the group consisting of a diameter of the via hole, a thickness of the insulating film, a thickness of the copper overburden, Wherein the stress of the silicon penetrating electrode is controlled by the through silicon via (TSV) structure.

In one embodiment of the present invention, the silicon penetrating electrode structure may be such that the stress of the penetrating electrode is smaller than the yield stress of silicon. If the stress of the penetrating electrode is larger than the yield stress of silicon, a crack may be generated in the penetrating electrode. For example, the stress of the penetrating electrode may be von Mises stress, but is not limited thereto. The von Meister stress may be concentrated at the bottom edge of the penetrating electrode.

Throughout this specification, "cracking" or "cracking" of the penetrating electrode is interpreted to include not only cracks in the silicon penetrating electrode but also cracks under the silicon or cracks on the insulating film.

In one embodiment of the present invention, the penetrating electrode may have a T value of less than about 700, but is not limited thereto:

[Equation 1]

T = 678.57 + 34.01x - 1.25y - 0.60x ² + 0.001y ² - 0.007xy;

In the above formula,

T is the stress (MPa), x is the diameter of the via hole, and y is the thickness of the insulating film.

When the T value in Equation (1) is about 700 or more, a crack can be generated in the penetrating electrode.

In one embodiment of the present invention, the penetrating electrode may have a T value less than about 700 in the following equation (2), but is not limited thereto:

&Quot; (2) "

T = 531.53 + 21.09x + 99z - 0.11x ² - 16.05z ² 0.04xZ;

In the above formula,

T is the stress (MPa), x is the diameter of the via hole, and z is the thickness of the copper overburden.

When the T value in Equation (2) is about 700 or more, a crack can be generated in the penetrating electrode.

In one embodiment of the invention, the penetrating electrode may have a T value of less than about 147.04, but is not limited thereto:

&Quot; (3) "

T = 0.49x ² - 0.001y ² - 16.05z ² + 0.007xy - 0.04xz - 12.92x + 1.25y + 99z;

In the above formula,

T is the stress, x is the diameter of the via hole, y is the thickness of the insulating film, and z is the thickness of the copper overburden.

When the T value in Equation (3) is about 147.04 or more, a crack can be generated in the penetrating electrode.

In one embodiment of the present invention, the stress, which is the T value in the above Equations 1 to 3, may be a stress applied to the Si under the TSV, but is not limited thereto.

In one embodiment of the present invention, the conductor comprises Cu and the diffusion barrier comprises Ti, Ta, W, Ru, Pt, Co, or combinations thereof; Their nitride; Carbides thereof; Their phosphides; But are not limited to, those selected from the group consisting of, and combinations thereof. The above equations (1) to (3) can be changed depending on the type of the diffusion preventing film, because physical properties of the material such as Young's modulus, Poisson's ratio and CTE are different depending on the kind of material used as the diffusion preventing film to be.

In one embodiment of the present invention, the via hole may include, but is not limited to, penetrating or partially penetrating the silicon wafer.

In one embodiment of the present invention, the insulating film is selected from the group consisting of SiO ₂ , SiN, SiC, SiCN, Al ₂ O ₃ , a low-k insulating film, combinations thereof, But are not limited thereto. The above formulas (1) to (3) can be changed depending on the type of the insulating film, because physical properties of the material such as Young's modulus, Poisson's ratio and CTE are different depending on the type of the material used as the insulating film.

Hereinafter, the silicon penetrating electrode structure according to one embodiment of the present invention will be described with reference to FIG. 1, but the present invention is not limited thereto.

1 is a cross-sectional view of a silicon penetrating electrode structure 100 according to an embodiment of the present invention. 1, the silicon penetration electrode structure 100 includes a silicon wafer 110, a via hole 120, a conductor 130, a diffusion barrier film 140, an insulation film 150, and a copper overburden 160. [ .

The via hole 120 refers to a hole formed vertically on the silicon wafer 110.

In one embodiment of the present invention, the smaller the diameter of the via hole 120, the smaller the maximum stress of the silicon through electrode. For example, the diameter of the via hole 120 may be from about 2 microns to about 20 microns, from about 2 microns to about 10 microns, from about 2 microns to about 5 microns, from about 5 microns to about 20 microns, from about 5 microns to about 10 mu m, or from about 10 mu m to about 20 mu m, but is not limited thereto.

In one embodiment of the present invention, the silicon penetrating electrode structure 100 may include the via hole 120 penetrating the silicon wafer 110 or partially penetrating the silicon wafer 110, but the present invention is not limited thereto.

In one embodiment of the present invention, the silicon penetrating electrode structure 100 may include at least one via hole 120, but is not limited thereto.

In one embodiment of the present invention, the thinner the copper overburden 160, the lower the maximum stress of the silicon through electrode. For example, the thickness of the copper overburden 160 may range from about 0 탆 to about 5 탆, from about 0 탆 to about 4 탆, from about 0 탆 to about 3 탆, from about 0 탆 to about 2 탆, To about 1 < RTI ID = 0.0 > pm, < / RTI >

In one embodiment of the present invention, the silicon penetrating electrode structure 100 includes an insulating layer 150 and a conductive layer 150 formed on a wall surface 120A and a lower surface 120B of a via hole 120 formed in the silicon wafer 110, Diffusion barrier film 140 may be stacked and the conductor 130 may be filled.

In one embodiment of the invention, the conductor 130 may comprise Cu. In one embodiment of the invention, the conductor 130 may be filled by a method selected from the group consisting of physical vapor deposition (PVD), chemical vapor deposition (CVD), electroplating, electroless plating, But is not limited thereto. Also, the conductor 130 may include, but is not limited to, a seed layer filled by ionizing sputtering, electrolytic plating, or a combination thereof.

In one embodiment of the present invention, the diffusion barrier layer 140 may include, for example, Ti, Ta, W, Ru, Pt, Co, or combinations thereof; Their nitride; Carbides thereof; Their phosphides; But are not limited to, those selected from the group consisting of, and combinations thereof.

In one embodiment, the diffusion barrier layer 140 may be deposited by a method selected from the group consisting of physical vapor deposition (PVD), chemical vapor deposition (CVD), electroplating, electroless plating, But is not limited thereto.

In one embodiment of the present invention, the greater the thickness of the insulating layer 150, the smaller the maximum stress of the silicon through electrode. For example, the thickness of the insulating layer 150 may range from about 50 nm to about 500 nm, from about 50 nm to about 250 nm, from about 50 nm to about 230 nm, from about 50 nm to about 110 nm, from about 110 nm to about 500 nm, about 110 nm to about 250 nm, about 110 nm to about 230 nm, about 230 nm to about 500 nm, about 230 nm to about 250 nm, or about 250 nm to about 500 nm, no.

In one embodiment of the present invention, the insulating layer 150 may be formed of, for example, SiO ₂ , SiN, SiC, SiCN, Al ₂ O ₃ , a low-k insulating film, And a laminated structure, but the present invention is not limited thereto.

In one embodiment, the insulating layer 150 may be deposited on the silicon wafer 110 by a process selected from the group consisting of thermal oxidation, wet process, chemical vapor deposition (CVD), and combinations thereof. But is not limited thereto. For example, the chemical vapor deposition process may be a sub-atmospheric chemical vapor deposition (SACVD) process or a plasma-enhanced chemical vapor deposition (PECVD) process.

According to a second aspect of the present invention, there is provided a method for predicting thermomechanical stress of a penetrating electrode using a silicon penetrating electrode structure according to the first aspect of the present invention, wherein a via hole diameter of the penetrating electrode, a thickness of the insulating film, Thermo-mechanical stresses of the silicon penetrating electrode, including preventing cracking of the penetrating electrode by predicting the stress of the silicon penetrating electrode by using a parameter selected from the group consisting of combinations thereof, Provides a prediction method.

In one embodiment of the present invention, when the stress of the penetrating electrode is greater than the yield stress of silicon, a crack may be generated in the penetrating electrode, but the present invention is not limited thereto. For example, the possibility of cracking of the penetrating electrode according to the variable may be predictable by using a thermo-mechanical stress prediction method of a silicon penetrating electrode according to an embodiment of the present invention. In addition, But it is not limited to this. In addition, the stress of the penetrating electrode may mean the von Mises stress, but is not limited thereto.

In one embodiment of the present invention, the stress of the penetrating electrode is predicted by the following equation (1), and cracking of the penetrating electrode may be prevented when the T value is less than about 700, It is not:

[Equation 1]

T = 678.57 + 34.01x - 1.25y - 0.60x ² + 0.001y ² - 0.007xy;

In the above formula,

T is the stress (MPa), x is the diameter of the via hole, and y is the thickness of the insulating film.

In one embodiment of the present invention, the stress of the penetrating electrode is predicted by the following equation (2), and cracking of the penetrating electrode may be prevented when the T value is less than about 700, It is not:

&Quot; (2) "

T = 531.53 + 21.09x + 99z - 0.11x ² - 16.05z ² - 0.04xz;

In the above formula,

T is the stress (MPa), x is the diameter of the via hole, and z is the thickness of the copper overburden.

In one embodiment of the present invention, the generation of cracks in the penetrating electrode may be prevented when the T value in Equation (3) is less than about 147.04, but is not limited thereto:

&Quot; (3) "

T = 0.49x ² - 0.001y ² - 16.05z ² + 0.007xy - 0.04xz - 12.92x + 1.25y + 99z;

In the above formula,

T is the stress, x is the diameter of the via hole, y is the thickness of the insulating film, and z is the thickness of the copper overburden.

The second aspect of the present application may be applied to all of the contents described in the first aspect of the present application.

Hereinafter, the present invention will be described in detail with reference to examples, but the present invention is not limited thereto.

[ Example ]

에 의해 분석하였다. 유력한 설계 파라미터가 도출되었고, 그것들 간의 상호작용을 검토하였다.In this embodiment, the influence of the design (design) parameters (variables) of the TSV on the thermo-mechanical stress distribution by the finite element method is calculated. Cu was used as the conductor, Ti was used as the diffusion preventing film, and SiO ₂ was used as the insulating film. The static analysis of the Ponmese stress was performed at 350 캜 and the selected parameters are as follows: diameter and aspect ratio of TSV, slope of TSV wall, thickness of insulating film and step coverage, and thickness of copper overburden. The two values of TSV were modeled assuming the symmetry of the cylindrical TSV, and the normal program, ANSYS

Lt; / RTI > Potential design parameters were derived, and the interactions between them were examined.

(ANSYS Inc., USA)을 사용하여 구성하였다. 본 실시예에서는 절연막(SiO₂)/배리어 금속(Ti)/구리 층으로 매립되고 구리 오버버든에 의해 덮인 블라인드 비아를 가정하였다. 화학-기계적 연마(chemical-mechanical polishing; CMP) 공정에 의해 디싱(dishing)이나 오목한 부분은 무시하였다. 상기 모델의 메쉬(mesh) 및 임계 계면에서의 메쉬는 도 2a에서 나타나며, 도 2b는 상기 모델링에 의해 계산된 응력 분포의 예를 나타낸다. 폰 미제스 응력은 하단 모서리에서 집중되어 있으며, 그래프는 설계 파라미터의 함수로서 최대 응력 값에 의해 플롯(plot)되었다.A two-dimensional finite element model using cylindrical coordinates is ANSYS

(ANSYS Inc., USA). In this embodiment, a blind via embedded with an insulating film (SiO ₂ ) / barrier metal (Ti) / copper layer and covered by a copper overburden is assumed. The dishing or concave portions were ignored by a chemical-mechanical polishing (CMP) process. The mesh at the model and the mesh at the critical interface are shown in FIG. 2A, and FIG. 2B shows an example of the stress distribution calculated by the modeling. The von Mises stress is concentrated at the lower edge, and the plot is plotted by the maximum stress value as a function of design parameters.

Static analysis was performed at 350 ° C and the maximum thermo-mechanical stress state during the process of manufacturing the TSV was assumed. The von Meisses stress was calculated to predict whether or not silicon cracking occurred. The peeling of the TSV / Si interface is not considered in this embodiment, but the compressive stress on the TSV / Si interface induced by heating does not affect the TSV peeling.

The properties of the materials used in this example are shown in Table 1 below.

[Table 1]

Since the copper has the largest thermal expansion coefficient in the TSV models in this embodiment, the thermo-mechanical stress is mainly caused by the behavior of the temperature-sensitive copper. Therefore, as shown in Table 2 below, the characteristics of non-linear materials of copper were considered.

[Table 2]

1 is a schematic cross-sectional view of a TSV structure tested in this embodiment. In this embodiment, for example, the diameter and the aspect ratio of the TSV, the slope of the TSV wall, the sidewall coverage and thickness of the insulating film, and the thickness of the copper overburden are considered as design parameters (variables). Since the diffusion barrier metal is thinner than the insulating film or copper vias, the effect of Ti thickness on the stress distribution can be neglected in this preliminary calculation. Therefore, the Ti thickness was fixed to 30 nm. We also did not consider the wave shape of the vias wall. The diameter of the copper overburden was fixed at 100 μm, while the thickness of the copper overburden was 5 μm except for FIGS. 10 and 11.

One. TSV of diameter  And Wall Tilt Effects

Since copper has the greatest thermal expansion coefficient than other materials, the amount of copper affects thermo-mechanical stresses on all systems. The von Mises stress was analyzed using various TSV diameters and aspect ratios. For these diameters of 2 탆, 5 탆, 10 탆, and 20 탆, the aspect ratio varied from 2 to 20. Figure 3 shows a contour plot of the bottom edge of the TSV when the vomitless stress is concentrated in the silicon. As the diameter of the vias increases, the maximum von Mises stress increases. When the aspect ratio was fixed at 10, the maximum stress increased from 584 MPa for 2 탆 diameter vias to 994 MPa for 2 탆 diameter vias. However, the effect of the aspect ratio was negligible with respect to the fixed diameter, as shown in Fig. In addition, it was shown that when the via diameter is greater than 5 占 퐉, the maximum stress in silicon is higher than the yield stress of silicon (700 MPa). Thus, the diameter of the TSV was an important design parameter for highly manufacturable processes.

Vertical via profiles are preferred for low-resistance TSVs, but adjustment of vertical profiles is difficult. We considered wall slopes of 88 °, 89 °, and 90 ° for bottom diameters of 3 μm, 6.5 μm, and 10 μm. Contour plot and maximum stress vs. Via slope plots are shown in Figures 5 and 6. The maximum stress was reduced to 634 MPa, which is lower than the yield stress of silicon at 838 MPa, by decreasing the slope angle from 90 ° to 88 °. The via slope was another design parameter of the TSV because there would be a trade-off between TSV resistance and maximum stress in silicon.

2. Influence of thickness of insulating film

The insulating film also plays an important role in determining the thermo-mechanical stress because the insulating film has the lowest CTE for the TSV models. Figure 7 shows that the maximum stress decreases from 919 MPa to 571 MPa as the thickness of the insulating film increases from 50 nm to 500 nm in 10 탆 diameter vias. The von Meisses stress was lower than the yield stress of silicon when the insulating film was thicker than 230 nm. Therefore, the thick insulating film is advantageous in lowering the maximum stress in the silicon, which is also an important design parameter with the via diameter. The minimum insulating film thickness for the maximum stress less than the silicon yield stress was 250 nm, 230 nm, and 110 nm, respectively, for the via diameters of 20 탆, 10 탆, and 5 탆, as shown in Fig.

The step coverage of the insulating film depends on the deposition method. Subatmospheric chemical vapor deposition (SACVD) and plasma-enhanced chemical vapor deposition (PECVD) are the most common methods for TSV processes. SACVD exhibits excellent step coverage and minimal wall roughness. PECVD exhibited a high deposition rate with poor wall coverage. Figure 9 compares the maximum stresses for different SiO ₂ step coverage of 50% and 100%, indicating that the lower step coverage of the SiO ₂ insulating film is higher. The maximum stress for 50% step coverage, 903 MPa, is similar to the maximum stress of 919 MPa in FIG. 7A because the lower step coverage means a thin SiO ₂ insulating film at the bottom of the TSV. Thus, PECVD induces higher stresses than SACVD on the thickness of the SiO ₂ insulating film in the same range.

3. Copper Overburden's  effect

The thickness of the copper overburden depends on, for example, the type of chemical additive in the electroplating bath, the duty ratio of the plating pulse, and the parameters of the electroplating process, such as total plating time It depends. Figure 10 shows that the maximum stress increases from 712 MPa to 838 MPa as the thickness of the copper overburden increases from 0 [mu] m to 5 [mu] m for 10 [mu] m diameter vias. Even though the thickness of the copper overburden was 0 탆, the pommex stress was higher than the yield stress of silicon.

Figure 11 shows the maximum pomposite stress as a function of copper overburden thickness and diameter. For 5 [micro] m diameter vias, the copper overburden would be thinner than 500 nm and had a lower p emitter stress than the silicon yield stress. Thus, the thickness of the copper overburden was another important design parameter and suppressed the stress developed in the silicon.

According to the present embodiment, the TSV diameter and the thickness of the insulating film were two important parameters for determining the maximum stress in silicon. While the maximum stress decreased as the TSV diameter decreased, the effect of the aspect ratio was negligible. The insulating film also played an important role in determining the thermo-mechanical stress, and the thick insulating film has an advantage of lowering the maximum stress in the silicon. The minimum insulating film thickness for this maximum stress, which is less than the yield stress of silicon, was 520 nm, 230 nm, and 110 nm for vias diameters of 20, 10, and 5 m. The maximum stress also decreased as the thickness of the copper overburden decreased. The effects of other parameters were also examined. The thermo-mechanical stresses in the TSV structure could be minimized by optimizing the design parameters and lowering the maximum process temperature.

It will be understood by those of ordinary skill in the art that the foregoing description of the embodiments is for illustrative purposes and that those skilled in the art can easily modify the invention without departing from the spirit or essential characteristics thereof. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive. For example, each component described as a single entity may be distributed and implemented, and components described as being distributed may also be implemented in a combined form.

The scope of the present invention is defined by the appended claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be interpreted as being included in the scope of the present invention .

100: Silicon penetrating electrode structure
110: Silicon wafer
120: via hole
120A: Via hole wall surface
120B: via hole bottom
130: conductor
140: diffusion barrier
150: insulating film
160: copper overburden

Claims (12)

A via hole formed in the silicon wafer in the vertical direction;
A conductor, a diffusion barrier, and a dielectric liner sequentially disposed in the via hole; And
And a copper overburden disposed on the top of the via hole,
The stress of the silicon penetrating electrode structure is controlled by a parameter selected from the group consisting of the diameter of the via hole, the thickness of the insulating film, the thickness of the copper overburden, and combinations thereof,
Wherein the silicon penetrating electrode structure has a through silicon via (TSV) structure wherein a T value of the following formula (1) or (2) is less than 700 or a T value of the formula (3) is less than 147.04:
[Equation 1]
T = 678.57 + 34.01x - 1.25y - 0.60x ² + 0.001y ² - 0.007xy;
&Quot; (2) "
T = 531.53 + 21.09x + 99z - 0.11x ² - 16.05z ² - 0.04xz;
&Quot; (3) "
T = 0.49x ² - 0.001y ² - 16.05z ² + 0.007xy - 0.04xz - 12.92x + 1.25y + 99z;
In the above equations,
T is the stress (MPa) of the silicon penetrating electrode,
x is the diameter of the via hole,
y is the thickness of the insulating film,
z is the thickness of the copper overburden.
The method according to claim 1,
Wherein a stress of the silicon penetrating electrode structure is smaller than a yield stress of silicon.
delete delete delete The method according to claim 1,
Wherein the conductor comprises Cu and the diffusion barrier comprises Ti, Ta, W, Ru, Pt, Co, or combinations thereof; Their nitride; Carbides thereof; Their phosphides; And combinations thereof. ≪ RTI ID = 0.0 > 11. < / RTI >
The method according to claim 1,
Wherein the via hole includes a through hole or a through hole of the silicon wafer.
The method according to claim 1,
The insulating film is a silicon penetrating electrode comprises one selected from the group consisting of SiO _2, SiN, SiC, SiCN, Al ₂ O _3, a low dielectric constant (low-k) insulating film, and a combination thereof in, and their laminate structure Structure.
A method for predicting thermo-mechanical stress of a silicon penetrating electrode using the silicon penetrating electrode structure according to any one of claims 1, 2, and 6 to 8,
The stress of the silicon penetration electrode is predicted by using a parameter selected from the group consisting of a via hole diameter of the penetrating electrode, a thickness of the insulating film, a thickness of the copper overburden, and combinations thereof, Preventing cracking of the silicon penetrating electrode,
The stress of the silicon through electrode is predicted by any one of the following equations (1) to (3)
Wherein the silicon penetration electrode prevents generation of a crack in the silicon penetration electrode when a T value of the following formula (1) or (2) is less than 700 or a T value of the following formula (3) is less than 147.04: Method of Predicting Thermo-mechanical Stresses:
[Equation 1]
T = 678.57 + 34.01x - 1.25y - 0.60x ² + 0.001y ² - 0.007xy;
&Quot; (2) "
T = 531.53 + 21.09x + 99z - 0.11x ² - 16.05z ² - 0.04xz;
&Quot; (3) "
T = 0.49x ² - 0.001y ² - 16.05z ² + 0.007xy - 0.04xz - 12.92x + 1.25y + 99z;
In the above equations,
T is the stress (MPa) of the silicon penetrating electrode,
x is the diameter of the via hole,
y is the thickness of the insulating film,
z is the thickness of the copper overburden. delete delete delete

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