KR101566487B1 - Apparatus for performing a power loss test for a non-volatile memory device and method of performing a power loss test for a non-volatile memory device - Google Patents

Abstract

The power loss test device of the nonvolatile memory device is inserted into the nonvolatile memory device to be tested in order to perform the power loss test on the nonvolatile memory device having at least one pin indicating the operation state of the internal NAND flash memories A test board unit having a socket, a test board unit for detecting an operation state of the internal NAND flash memories from the at least one pin, and supplying and stopping power supply necessary for the operation of the nonvolatile memory device, And a tester section for providing a predetermined write command to the non-volatile memory device and for performing a power loss test on the non-volatile memory device based on the supply and interruption of the power source.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a power loss test apparatus and method for a nonvolatile memory device. 2. Description of the Related Art [0002]

The present invention relates to non-volatile memory devices. More particularly, the present invention relates to a power loss test device and method of a non-volatile memory device (e.g., an embedded multimedia card, etc.) having at least one pin that indicates an internal operating state.

The semiconductor memory device can be divided into a volatile memory device and a nonvolatile memory device depending on whether data can be stored in a state in which power is not supplied. In recent years, NAND flash memory devices among NAND flash memory devices have been widely used because of miniaturization and large capacity of semiconductor memory devices, and these NAND flash memory devices are widely used, An embedded multi-media card (eMMC), etc.) is replacing a hard disk drive (HDD). Generally, a nonvolatile memory device includes at least one NAND flash memory therein and a memory controller for controlling the same. Specifically, the memory controller performs an address mapping operation using a flash translation layer to support a file system, and performs a read operation, a read operation, a write operation, an erase operation, a merge operation, a copyback operation, a compaction operation, a garbage collection operation, a wear leveling operation, .

As described above, in the nonvolatile memory device, a lot of operations are performed internally unlike the case of the host device. When the nonvolatile memory device performs the write operation or the garbage collection operation, the sudden power off occurs, the user data and / or the meta data associated therewith may be lost, resulting in an error. Therefore, the nonvolatile memory device should prevent the occurrence of an error through data recovery or the like, even if the power-off occurs, in order to provide usability stability to the user. In general, a usability test (hereinafter referred to as a power loss test) is performed on a non-volatile memory device according to a power-off before shipment of the product. For this purpose, in the related art, the nonvolatile memory device was randomly turned off during the writing operation, and then it was checked whether an error occurred due to the loss of the user data and / or the meta data. However, The internal operation state of the nonvolatile memory device is not taken into consideration at all, so that the power loss test is inefficiently performed.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a nonvolatile memory device which is capable of performing nonvolatile (nonvolatile) memory operations while performing a main operation (for example, a write operation of metadata, a garbage collection operation, And to provide a power loss test apparatus and method for a nonvolatile memory device that efficiently performs a power loss test by turning off the power supplied to the memory device. However, the object of the present invention is not limited to the above objects, but may be variously modified without departing from the spirit and scope of the present invention.

In order to accomplish one object of the present invention, a power loss test apparatus of a nonvolatile memory device according to embodiments of the present invention includes at least one pin indicating an operation state of internal NAND flash memories A test board unit having at least one socket into which the nonvolatile memory device to be tested is inserted to perform a power loss test on at least one nonvolatile memory device, A microcontroller unit for detecting an operation state and determining supply and interruption of a power supply necessary for operation of the nonvolatile memory device based on an operation state of the NAND flash memories; command, and at the same time, In response to the stage for the non-volatile memory device may include a tester performing the power loss test.

According to an embodiment, the operation state of the NAND flash memories includes a first voltage level of the pin indicating a busy state of the NAND flash memories, and a second voltage level indicating a ready state of the NAND flash memories. 2 < / RTI > voltage level.

According to one embodiment, the nonvolatile memory device may be an embedded MultiMediaCard (eMMC).

According to one embodiment, the microcontroller unit may be located inside the test board unit or inside the tester unit.

According to an embodiment, when the nonvolatile memory device performs a write operation of user data, the nonvolatile memory device may be supplied with the power, and the nonvolatile memory device stores meta data data from the non-volatile memory device when performing a write operation or a garbage collection operation of the non-volatile memory device.

According to an embodiment, the test board unit may perform supply and cut-off of the power supply to the nonvolatile memory device through the socket.

According to an embodiment, the microcontroller may determine the supply of the power when the operation state of the NAND flash memories indicates a normal operation pattern, and when the operation state of the NAND flash memories is the normal operation pattern , It is possible to determine the interruption of the power source.

In order to accomplish one object of the present invention, a method for testing a power loss of a non-volatile memory device according to embodiments of the present invention includes a step of testing a non- A power loss test can be performed on the volatile memory device. Specifically, the method includes providing predetermined write commands to the non-volatile memory device to perform the power loss test, determining whether the non-volatile memory device is in the non-volatile memory device based on the operating status of the NAND flash memories detected from the pin, Repeatedly performing supply and interruption of power required for operation of the volatile memory device and performing the power loss test on the non-volatile memory device in response to the supply and interruption of the power supply .

According to an embodiment, the operating state of the NAND flash memories may include a first voltage level of the pin indicating a ready state of the NAND flash memories, and a first voltage level of the NAND flash memories indicating a busy state of the NAND flash memories. 2 < / RTI > voltage level.

According to an embodiment, the step of repeatedly performing the supply and the interruption of the power supply includes supplying power to the nonvolatile memory device when the operation state of the NAND flash memories indicates a normal operation pattern, And disconnecting the power source from the non-volatile memory device if the operating state of the flash memories does not indicate the normal operation pattern.

The apparatus and method for testing a power loss of a nonvolatile memory device according to embodiments of the present invention include a nonvolatile memory device having at least one pin for indicating an operating state (i.e., ready state or busy state) of internal NAND flash memories (I.e., the operating state of the internal NAND flash memories) from the pin to detect a power supplied to the nonvolatile memory device during the critical operation of the nonvolatile memory device The power loss test can be efficiently performed. However, the effects of the present invention are not limited to the above effects, and may be variously expanded without departing from the spirit and scope of the present invention.

1 is a block diagram illustrating a power loss test device of a nonvolatile memory device according to embodiments of the present invention.
2 is a diagram showing an example in which a test board unit, a microcontroller unit, and a tester unit operate in the power loss test apparatus of FIG.
FIG. 3 is a flowchart showing an operation of the microprocessor-added nonvolatile memory device in the power loss test device of FIG. 1 to determine supply and interruption of power to the nonvolatile memory device.
FIG. 4 is a diagram illustrating an example in which an operation state of NAND flash memories provided in a nonvolatile memory device is detected in the power loss test apparatus of FIG. 1; FIG.
5 is a flowchart showing a power loss test method of a nonvolatile memory device according to embodiments of the present invention.
FIG. 6 is a diagram showing an example in which supply and cutoff of power supply to the nonvolatile memory device are determined in the power loss test method of FIG. 5; FIG.

For the embodiments of the invention disclosed herein, specific structural and functional descriptions are set forth for the purpose of describing an embodiment of the invention only, and it is to be understood that the embodiments of the invention may be practiced in various forms, The present invention should not be construed as limited to the embodiments described in Figs.

The present invention is capable of various modifications and various forms, and specific embodiments are illustrated in the drawings and described in detail in the text. It is to be understood, however, that the invention is not intended to be limited to the particular forms disclosed, but on the contrary, is intended to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention.

The terms first, second, etc. may be used to describe various components, but the components should not be limited by the terms. The terms may be used for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as a second component, and similarly, the second component may also be referred to as a first component.

It is to be understood that when an element is referred to as being "connected" or "connected" to another element, it may be directly connected or connected to the other element, . On the other hand, when an element is referred to as being "directly connected" or "directly connected" to another element, it should be understood that there are no other elements in between. Other expressions that describe the relationship between components, such as "between" and "between" or "neighboring to" and "directly adjacent to" should be interpreted as well.

The terminology used in this application is used only to describe a specific embodiment and is not intended to limit the invention. The singular expressions include plural expressions unless the context clearly dictates otherwise. In the present application, the terms "comprise", "having", and the like are intended to specify the presence of stated features, integers, steps, operations, elements, components, or combinations thereof, , Steps, operations, components, parts, or combinations thereof, as a matter of principle.

Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in commonly used dictionaries should be construed as meaning consistent with meaning in the context of the relevant art and are not to be construed as ideal or overly formal in meaning unless expressly defined in the present application .

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. The same reference numerals are used for the same constituent elements in the drawings and redundant explanations for the same constituent elements are omitted.

FIG. 1 is a block diagram showing a power loss test apparatus of a nonvolatile memory device according to an embodiment of the present invention. FIG. 2 is a block diagram of a power loss test apparatus of FIG. 1, in which a test board section, Fig.

Referring to FIGS. 1 and 2, the power loss test apparatus 100 of FIG. 1 can perform a power loss test on at least one nonvolatile memory device having a plurality of NAND flash memories have. At this time, the nonvolatile memory device may have at least one pin indicating the operating state (OSI) of the internal NAND flash memories. Specifically, the power loss test apparatus 100 of FIG. 1 may include a test board unit 120, a microcontroller unit 140, and a tester unit 160. 1, the microcontroller unit 140 is located outside the test board unit 120 and the tester unit 160. However, the microcontroller unit 140 is located inside the test board unit 120 Or may be located within the tester unit 160. [

The test board unit 120 may have a plurality of sockets 122-1, ..., 122-n into which the nonvolatile memory device to be tested for the power loss test is inserted. Generally, data (i.e., user data and / or metadata associated therewith) occurs when a non-volatile memory device experiences a sudden power-off that suddenly powers down during a write operation or a garbage collection operation. The error may occur. Therefore, the power loss test apparatus 100 of FIG. 1 performs a power loss test to confirm whether or not an error can be prevented through data recovery or the like even if power off occurs in the nonvolatile memory device . Since the test board unit 120 includes the sockets 122-1, ..., and 122-n into which the nonvolatile memory devices to be tested are subjected to the power loss test, The device 100 can simultaneously perform a power loss test on the nonvolatile memory devices to be tested in the power loss test. As a result, a power loss test for non-volatile memory devices can be performed quickly and efficiently. For example, as shown in FIG. 2, the power loss test for the non-volatile memory devices inserted in the sockets 122-1, ..., 122-n of the test board portion 120, respectively, When the control unit 160 receives the second control signal CTL2 (OFF) for instructing the end of the test from the time when the second control signal CTL2 (ON) indicating the start of the test is inputted from the microcontroller unit 140 Up to a point in time.

In one embodiment, the non-volatile memory device may be an embedded multimedia card. Usually, the standard of the embedded multimedia card defines more than 160 pins. Among these pins are pins (i.e., monitoring pins) capable of monitoring internal information (i.e., internal operating state) of the nonvolatile memory device as well as pins (i.e., input / output pins) for external input / output. In particular, such monitoring pins include at least one pin that indicates the operating state (OSI) (e.g., ready state or busy state) of the NAND flash memories provided in the non-volatile memory device. Therefore, the power loss test apparatus 100 of FIG. 1 detects the internal operating state of the nonvolatile memory device from at least one pin indicating the operating state (OSI) of the NAND flash memories provided in the nonvolatile memory device, The power loss test can be efficiently performed (for example, test time reduction, test strength improvement, etc.) by cutting off the power supplied to the nonvolatile memory device while the nonvolatile memory device is performing important operations. In the above description, the nonvolatile memory device is an embedded multimedia card, but the type of the nonvolatile memory device is not limited thereto. For example, a non-volatile memory device may include a secure digital card (SD) card, a compact flash card (CF) card, a memory stick (memory card), or the like, having at least one pin for indicating the operating state stick, an XD picture card, or the like.

The microcontroller unit 140 detects the operating state (OSI) of the NAND flash memories provided in the nonvolatile memory device from at least one or more pins of the nonvolatile memory device, and detects the operating state of the NAND flash memories (OSI), it is possible to determine the supply and interruption of the power supply necessary for the operation of the nonvolatile memory device. That is, in the related art, after the nonvolatile memory device is randomly turned off during the write operation, it is checked whether an error occurs due to loss of user data and / or metadata. However, the power loss test device 100 considers the internal operating state of the non-volatile memory device (i.e., the operating state (OSI) of the NAND flash memories provided in the non-volatile memory device) in performing the power loss test. Therefore, the power loss test apparatus 100 of FIG. 1 interrupts the power supplied to the nonvolatile memory device while the nonvolatile memory device is performing a critical operation (for example, a write operation of metadata, a garbage collection operation, etc.) The power loss test can be efficiently performed. Generally, in performing the power loss test on the embedded multimedia card, the test time is shortened when the power is turned off at the time when the metadata (i.e., FTL meta information) is programmed in the nonvolatile memory device, Can be improved. In other words, the metadata (i.e., the FTL meta information) is stored in the non-volatile memory device at the time when the user data is programmed into the nonvolatile memory device, when the central processing unit (CPU) The power loss test can be performed efficiently when the power is turned off at the time of being programmed in the memory device or at the time when the garbage collection operation is performed in the nonvolatile memory device.

Therefore, when the nonvolatile memory device performs the write operation of the user data, the microcontroller unit 140 determines to supply power to the nonvolatile memory device, and the nonvolatile memory device performs the writing operation of the metadata or the garbage When performing the collection operation, it can be determined that the power is turned off from the nonvolatile memory device. To this end, the microcontroller unit 140 detects the operating state (OSI) of the NAND flash memories provided in the nonvolatile memory device from at least one or more pins of the nonvolatile memory device, and based thereon, You can decide to supply and cut off the required power. Specifically, the microcontroller unit 140 determines to supply power to the nonvolatile memory device when the operating state (OSI) of the NAND flash memories provided in the nonvolatile memory device indicates the normal operation pattern, If the operating state (OSI) of the NAND flash memories provided in the memory device does not indicate the normal operation pattern, it can be determined that the power is turned off from the nonvolatile memory device. In general, when the user data is programmed into the nonvolatile memory device, the operating state (OSI) of the NAND flash memories provided in the nonvolatile memory device is set to a normal operation pattern (for example, Volatile memory device, and at the time when the metadata is programmed into the nonvolatile memory device or when the garbage collection operation is performed in the nonvolatile memory device, the operating state of the NAND flash memories included in the nonvolatile memory device OSI) does not represent the normal operation pattern. Therefore, the microcontroller unit 140 determines whether or not the power supply (not shown) required for operation of the nonvolatile memory device, depending on whether the operating state (OSI) of the NAND flash memories detected from the at least one pin of the nonvolatile memory device indicates the normal operation pattern Can be determined.

On the other hand, the internal operating state of the non-volatile memory device (i.e., the operating state (OSI) of the NAND flash memories provided in the non-volatile memory device) 1 voltage level and the second voltage level of the at least one pin of the non-volatile memory device indicating the ready state of the NAND flash memories. For example, during a write operation to one NAND flash memory provided in a nonvolatile memory device, a predetermined pin associated with the operating state (OSI) of the NAND flash memory reaches a first voltage level (for example, (OSI) of the NAND flash memory is at a second voltage level (e.g., a low voltage level) during a write operation to the NAND flash memory, (low) voltage level). Accordingly, the operating state (OSI) of the NAND flash memories provided in the nonvolatile memory device may correspond to a voltage level pattern indicated by at least one pin of the nonvolatile memory device. However, this is merely an example, and the present invention is not limited thereto. For example, the first voltage level may be a low voltage level, and the second voltage level may be a high voltage level. On the other hand, if the microcontroller unit 140 determines to supply and cut off the power required for operation of the nonvolatile memory device based on the internal operating state of the nonvolatile memory device, Volatile memory device through the sockets 122-1, ..., 122-n.

The tester unit 160 may provide a predetermined write command to the non-volatile memory device and at the same time perform a power loss test on the non-volatile memory device in response to the supply and interruption of power required for operation of the non-volatile memory device . The tester unit 160 may provide predetermined writing commands to the non-volatile memory device to allow the non-volatile memory device to continuously perform a writing operation by a test algorithm. For example, as shown in FIG. 2, the tester unit 160 instructs the end of the test from the time when the second control signal CTL2 (ON) indicating the start of the test is input from the microcontroller unit 140 The write operation by the test algorithm can be continuously performed until the second control signal CTL2 (OFF) is received. On the other hand, while the microcontroller unit 140 provides the first control signal CTL1 (ON) for instructing the supply of the power to the test board unit 120, the microcontroller unit 140 controls at least the non- (I.e., indicated by DECISION) from the nonvolatile memory device based on the operating state (OSI) of the NAND flash memories detected from the one or more pins, the microcontroller unit 140 controls the test board unit 120 The first control signal CTL1 (OFF) indicating the interruption of the power supply. Accordingly, the test board unit 120 can cut off power from the non-volatile memory device through the sockets 122-1, ..., 122-n in which the non-volatile memory device is inserted. In this way, the power loss test for the nonvolatile memory device in the test period TEST can be repeatedly performed.

As described above, the power loss test apparatus 100 of FIG. 1 has a configuration in which, from the pin to the non-volatile memory device having at least one or more pins for indicating the operation states of internal NAND flash memories, (I.e., the operating state (OSI) of the NAND flash memories included in the nonvolatile memory device) is detected and the nonvolatile memory device performs a critical operation (for example, a write operation of the metadata, a garbage collection operation, The power supplied to the nonvolatile memory device can be cut off. As a result, the power loss test for the nonvolatile memory device can be efficiently performed. That is, the tester unit 160 provides predetermined write commands to the non-volatile memory device inserted in the sockets 122-1, ..., 122-n of the test board unit 120, The power loss test for the nonvolatile memory device can be performed in response to the supply and cutoff of the power required for operation of the apparatus. At this time, if the microcontroller unit 140 detects the movement of the pin that is out of the normal movement of the pin as shown in the normal operation of the nonvolatile memory device (for example, when the user data is programmed into the nonvolatile memory device) By judging that the important operation of the nonvolatile memory device (for example, when the metadata is programmed into the nonvolatile memory device, when the garbage collection operation is performed in the nonvolatile memory device, etc.) is performed at the detection time, It is possible to cut off the power supplied to the nonvolatile memory device through the sockets 122-1, ..., and 122-n of the unit 120. [ On the other hand, the power loss test is performed simultaneously for each of the nonvolatile memory devices inserted in the sockets 122-1, ..., 122-n of the test board unit 120 at the same time. As a result, the time required for the power loss test and the test coverage are widened as compared with the prior art, so that the productivity of the manufacturer can be improved and the stability of the final product can be improved.

FIG. 3 is a flowchart showing an operation of the microcomputer-added nonvolatile memory device in the power loss test apparatus of FIG. 1 to determine supply and interruption of power supply, and FIG. 4 is a flow chart of the power loss test apparatus of FIG. FIG. 5 is a diagram showing an example in which an operation state of NAND flash memories is detected. FIG.

Referring to FIGS. 3 and 4, the microcontroller unit 140 controls the supply of power to the nonvolatile memory device based on the operating state (OSI) of the NAND flash memories detected from the at least one pin of the nonvolatile memory device It is shown to determine blocking. Specifically, the microcontroller unit 140 detects the operating state (OSI) of the NAND flash memories from at least one or more pins of the nonvolatile memory device (S120), and then detects the operating state of the NAND flash memories (S140) whether or not the OSI indicates the normal operation pattern. At this time, if the operating state (OSI) of the NAND flash memories provided in the nonvolatile memory device does not indicate the normal operation pattern, the microcontroller unit 140 determines to cut off the power required for the operation of the nonvolatile memory device )can do. In this case, the microcontroller unit 140 may provide a first control signal CTL1 (OFF) for instructing the test board unit 120 to cut off the power supply. On the other hand, if the operating state (OSI) of the NAND flash memories included in the nonvolatile memory device indicates the normal operation pattern, the microcontroller unit 140 can determine to continuously supply power necessary for operation of the nonvolatile memory device have. In this case, the microcontroller unit 140 may provide a first control signal CTL1 (ON) for instructing the test board unit 120 to supply power. Accordingly, the microcontroller unit 140 may repeat the steps S120 and S140. Thereafter, the test board unit 120 supplies power from the non-volatile memory device through the sockets 122-1, ..., 122-n according to the determination regarding the cutoff and supply of power to the microcontroller unit 140 Or supply power to the non-volatile memory device continuously.

As described above, the operating state (OSI) of the NAND flash memories provided in the nonvolatile memory device is determined by the first voltage level of at least one pin of the nonvolatile memory device representing the busy state of the NAND flash memories, May be detected based on the second voltage level of at least one or more of the pins of the non-volatile memory device representing the state. 4, when a write operation is performed on one NAND flash memory included in the nonvolatile memory device, a predetermined pin associated with the operating state (OSI) of the NAND flash memory is set to a first voltage level A predetermined pin associated with the operating state (OSI) of the NAND flash memory may be coupled to a second voltage level (e.g., a high voltage level) during a write operation to the NAND flash memory, Low voltage level). Meanwhile, FIG. 4 exemplarily shows a nonvolatile memory device (for example, an embedded multimedia card or the like) incorporating NAND flash memories using 8 KB pages. However, for convenience of explanation, it is assumed that the monitoring pins (DIE_0 READY / BUSY PIN, DIE_1 READY / BUSY PIN) allocated to two dies having one plane structure per die do. In this case, when the tester unit 160 provides the write command (8K WRITE) corresponding to the 8KB page data to the nonvolatile memory device via the test board unit 120, one NAND flash The memory can be operated. In Fig. 4, a write command (8K WRITE) corresponding to 8KB page data is sequentially provided to the nonvolatile memory device, and two NAND flash memories are alternately operated to program the 8K page data.

For example, a write command (8K WRITE) corresponding to 8KB page data is sequentially provided to the nonvolatile memory device, and two NAND flash memories The 8 KB page data is alternately programmed in the two NAND flash memories provided in the nonvolatile memory device when monitoring at least one pin of the nonvolatile memory device from the outside It can be seen that a given pin associated with each of these operating states OSI rises from a second voltage level (e.g., a low voltage level) to a first voltage level (e.g., a high voltage level). That is, when the write command (8K WRITE) corresponding to the 8KB page data is sequentially provided to the nonvolatile memory device, the operating state (OSI) of the NAND flash memories provided in the nonvolatile memory device is set to be regular And an operating state (OSI) of the NAND flash memories provided in the nonvolatile memory device may exhibit an irregular pattern due to the intermittent program of the meta data according to the FTL algorithm. For example, as shown in FIG. 4, when a seventh write command (8K WRITE) corresponding to 8KB page data is generated, the first monitoring pin (DIE_0 READY / BUSY PIN) (E.g., a low voltage level) to a first voltage level (e.g., a high voltage level), then a second monitoring pin (DIE_1 READY / BUSY PIN) For example, a low voltage level) to a first voltage level (e.g., a high voltage level). Since the voltage level change of the second monitoring pin (DIE_1 READY / BUSY PIN) is not a regular behavior pattern that the host device can predict to some extent (i. E. ASD in Fig. 4) Or it may be assumed that a garbage collection operation is performed in a non-volatile memory device.

In this way, the microcontroller unit 140 can monitor at least one or more pins of the nonvolatile memory device to determine whether the operating state (OSI) of the NAND flash memories provided in the nonvolatile memory device indicates the normal operation pattern have. Specifically, in the normal operation of the nonvolatile memory device (for example, when the user data is programmed into the nonvolatile memory device), the operating state (OSI) of the NAND flash memories provided in the nonvolatile memory device is set to the normal operation pattern (For example, when the metadata is programmed into the nonvolatile memory device, when the garbage collection operation is performed in the nonvolatile memory device, and the like) in the nonvolatile memory device, The operation state (OSI) of the NAND flash memories provided in the NAND flash memory does not indicate the normal operation pattern. [0064] As shown in FIG. 4, when one NAND flash memory operates to program 8K page data, RTI ID = 0.0 > (OSI) < / RTI > (I.e., ASD in FIG. 4) when the metadata is programmed into the non-volatile memory device, or when the garbage collection operation is performed in the non-volatile memory device, the operation state of the NAND flash memories The microcontroller unit 140 can detect the movement of the pin from the at least one pin of the non-volatile memory device, According to whether or not the operating state (OSI) of the NAND flash memories indicates the normal operation pattern, it is possible to determine supply and interruption of the power supply necessary for operation of the nonvolatile memory device.

As described above, the microcontroller unit 140 monitors at least one or more pins of the non-volatile memory device so that when the metadata is programmed into the non-volatile memory device, or when the garbage collection operation is performed in the non-volatile memory device ( That is, ASD in Fig. 4), the power supplied to the nonvolatile memory device can be cut off. On the other hand, various methods can be used as to which power supply to the nonvolatile memory device is to be precisely cut off at the power-off target period (that is, indicated by ASD in Fig. 4). For example, in FIG. 4, a second monitoring pin (DIE_1 READY / BUSY PIN) is activated at a second voltage level (e. G., Low voltage level) Level), the microcontroller unit 140 determines that the second monitoring pin DIE_1 READY / BUSY PIN is at the second voltage level (for example, the low voltage level) to the first voltage level (for example, The power supplied to the nonvolatile memory device can be cut off when a predetermined time (for example, in units of microseconds) elapses after the power supply voltage is raised to the predetermined voltage level. At this time, the preset time may be randomly determined between 0 and the average time in which one page data is programmed. However, this is merely an example, and it can be variously changed whether the microcontroller unit 140 cuts off the power supplied to the nonvolatile memory device at a certain point in the power-off target period (that is, indicated by ASD in FIG. 4) .

FIG. 5 is a flowchart showing a power loss test method of a nonvolatile memory device according to embodiments of the present invention, FIG. 6 is a flowchart illustrating a power loss test method of FIG. Fig.

Referring to FIGS. 5 and 6, the power loss test method of FIG. 5 may perform a power loss test on a nonvolatile memory device having at least one pin that indicates the operation state of internal NAND flash memories. Specifically, the power loss test method of FIG. 5 includes a step S220 of providing predetermined write commands to perform a power loss test on a nonvolatile memory device to be tested, (S240) repeatedly performing supply and interruption of the power supply necessary for the operation of the non-volatile memory device based on the operation state of the flash memories; and, in response to supply and interruption of the power required for the operation of the non- And performing a power loss test on the apparatus (S260). For example, a power loss test for a non-volatile memory device includes a plurality of test cycles, and one test cycle may be performed in three stages as follows. In a first step, the data in the non-volatile memory device is examined when power is applied to the non-volatile memory device. At this time, if the data check result is pass, the test is proceeded. If the data check result is fail, the test is ended. In a second step, it sends predetermined write commands to the non-volatile memory device. In a third step, at least one pin of the non-volatile memory device is monitored. At this time, if the operation state of the NAND flash memories indicates the normal operation pattern, the second and third steps are performed again. If the operation state of the NAND flash memories does not indicate the normal operation pattern, the power supplied to the non- The data of the nonvolatile memory device is inspected. If the data test result is not a failure even after such a test cycle is performed a plurality of times (for example, about 100K), it is determined that the nonvolatile memory device has passed the test. However, this is merely an example, and the power loss test and its test cycle are not limited thereto.

Specifically, the power loss test method of FIG. 5 may provide predetermined write commands to perform a power loss test on a nonvolatile memory device to be tested (S220). That is, the power loss test method of FIG. 5 may provide the non-volatile memory device with write operations predetermined by the test algorithm by continuously providing the write commands predetermined to the non-volatile memory device. In addition, the power loss test method of FIG. 5 repeatedly performs supply and interruption of power supply necessary for operation of the nonvolatile memory device based on the operation state of the NAND flash memories detected from at least one pin of the nonvolatile memory device (S240 )can do. At this time, the operating state of the NAND flash memories provided in the nonvolatile memory device is determined by the first voltage level of the at least one pin of the nonvolatile memory device indicating the busy state of the NAND flash memories and the ready state of the NAND flash memories And may be detected based on the second voltage level of at least one or more pins of the non-volatile memory device. In one embodiment, the power loss test method of FIG. 5 repeatedly performs supply and interruption of power supply necessary for operation of the nonvolatile memory device. In this case, when the operation state of the NAND flash memories included in the non- Volatile memory device and can turn off power from the non-volatile memory device if the operating state of the NAND flash memories included in the non-volatile memory device does not indicate the normal operation pattern. Further, the power loss test method of FIG. 5 may perform a power loss test (S260) on the nonvolatile memory device in response to the supply and cutoff of the power required for operation of the nonvolatile memory device.

Thus, the power loss test method of FIG. 5 can be applied to a nonvolatile memory device when power is supplied to the nonvolatile memory device when performing a general operation (for example, when user data is programmed into the nonvolatile memory device) When the nonvolatile memory device performs an IMPORTANT OPERATION (for example, a write operation of metadata, a garbage collection operation, and the like), the power supplied to the nonvolatile memory device is shut off, The power loss test for the volatile memory device can be performed efficiently (for example, shortening the test time, improving the test strength, etc.). Thus, as shown in FIG. 6, the power loss test method of FIG. 5 may be used to determine whether the non-volatile memory device is in a powered state 220 and in a non- (240). ≪ / RTI > However, since this has been described above, a duplicate description thereof will be omitted. Meanwhile, the non-volatile memory device may be an embedded multimedia card, but the type of the non-volatile memory device is not limited thereto. For example, the non-volatile memory device may be an SD card, a CF card, a memory stick, an XD picture card, or the like, which has at least one pin for indicating the operation state of internal NAND flash memories. Although the apparatus and method for testing a power loss of a nonvolatile memory device according to embodiments of the present invention have been described with reference to the drawings, the above description is illustrative and not restrictive within the scope of the present invention. Modifications and alterations may occur to those skilled in the art. For example, while the important operation of the nonvolatile memory device is described as the write operation of the metadata, the garbage collection operation, etc., the important operation of the nonvolatile memory device can be variously determined according to the required conditions.

The present invention can be applied to a power loss test of a nonvolatile memory device having at least one pin for indicating the operating state of internal NAND flash memories. Accordingly, the present invention may be applied to an embedded multimedia card, an SD card, a CF card, a memory stick, and the like having at least one pin for indicating the operation state of internal NAND flash memories.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention as defined in the following claims. It can be understood that it is possible.

100: Power loss test device 120: Test board part
122-1, 122-2, ..., 122-n: first to nth sockets
140: Micro controller unit 160: Tester unit

Claims (10)

Volatile memory device to be tested in order to perform a power loss test on at least one or more non-volatile memory devices having at least one pin indicating the operating state of internal NAND flash memories, A test board portion having at least one socket to be inserted;
A microcontroller for detecting an operation state of the NAND flash memories from the pins, and determining a supply and an interruption of a power supply necessary for operation of the nonvolatile memory device based on an operation state of the NAND flash memories; And
And a tester section for providing the predetermined write commands to the nonvolatile memory device and performing the power loss test on the nonvolatile memory device in response to the supply and cutoff of the power supply,
Wherein the operating state of the NAND flash memories is based on a first voltage level of the pin indicating a busy state of the NAND flash memories and a second voltage level of the pin indicating a ready state of the NAND flash memories Respectively,
Wherein when the nonvolatile memory device performs a write operation of user data, the nonvolatile memory device is supplied with power, and the nonvolatile memory device performs a writing operation of meta data or a garbage collection volatile memory device, the power source is disconnected from the nonvolatile memory device when performing a garbage collection operation. delete The apparatus of claim 1, wherein the nonvolatile memory device is an embedded MultiMediaCard (eMMC). The apparatus of claim 1, wherein the microcontroller unit is located inside the test board unit or inside the tester unit. delete The apparatus of claim 1, wherein the test board unit performs supply and interruption of the power supply to the nonvolatile memory device through the socket. The microcontroller according to claim 1, wherein the microcontroller unit determines supply of the power when the operation state of the NAND flash memories indicates a normal operation pattern, and determines whether the operation state of the NAND flash memories is the normal operation pattern The power loss test apparatus of the nonvolatile memory device determines that the power supply is interrupted. 1. A power loss test method for a nonvolatile memory device that performs a power loss test on a nonvolatile memory device having at least one or more pins for indicating an operating state of internal NAND flash memories,
Providing predetermined write commands to the non-volatile memory device to perform the power loss test;
Repeatedly performing supply and interruption of power required for operation of the nonvolatile memory device based on an operation state of the NAND flash memories detected from the pin; And
Performing the power loss test on the non-volatile memory device in response to the supply and shutdown of the power supply,
Wherein the operating state of the NAND flash memories is based on a first voltage level of the pin indicating a ready state of the NAND flash memories and a second voltage level of the pin indicating a busy state of the NAND flash memories Respectively,
The step of repeatedly performing supply and interruption of the power source
Supplying power to the nonvolatile memory device when the operation state of the NAND flash memories indicates a normal operation pattern; And
And disconnecting the power source from the non-volatile memory device when the operation state of the NAND flash memories does not indicate the normal operation pattern. delete delete

Images