KR101565255B1 - Method of fabricating layer comprising metal and chalcogen, and transistor comprising the same - Google Patents

Method of fabricating layer comprising metal and chalcogen, and transistor comprising the same Download PDF

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KR101565255B1
KR101565255B1 KR1020140102524A KR20140102524A KR101565255B1 KR 101565255 B1 KR101565255 B1 KR 101565255B1 KR 1020140102524 A KR1020140102524 A KR 1020140102524A KR 20140102524 A KR20140102524 A KR 20140102524A KR 101565255 B1 KR101565255 B1 KR 101565255B1
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South Korea
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substrate
compound layer
dimensional compound
source
metal
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KR1020140102524A
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Korean (ko)
Inventor
함기열
전형탁
신석윤
박주현
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한양대학교 산학협력단
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/40—Alloying of impurity materials, e.g. doping materials, electrode materials, with a semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film

Abstract

Provided is a method for manufacturing a thin film. The method for manufacturing a thin film comprises the following steps of: preparing a substrate; providing a first source having chalcogen onto the substrate; and forming a 2-dimensional compound layer of the chalcogen and metal on the substrate by providing a second source having the metal onto the substrate.

Description

METHOD FOR MANUFACTURING THIN FILM CONTAINING METAL AND CHALKOGEN, AND TRANSISTOR CONTAINING THE SAME,

The present invention relates to a method of manufacturing a thin film including a metal and a chalcogen, and a transistor including the same, and more particularly, to a method of manufacturing a thin film including a two-dimensional compound layer of metal and chalcogen, .

With the tendency to favor designs and human-friendly products, interest in flexible and transparent next-generation electronics products is increasing. As such, flexible electronic devices can be applied in a wide range of fields ranging from flexible displays, wearable computers, healthcare, robots, and energy.

However, conventional bulk and thin film based materials have problems of life due to compression and tensile, and there are problems such as low charge mobility, unstable interfacial state and low reliability, so that they are applied to next generation electronic products There is a difficulty. Therefore, it is required to develop new electronic materials capable of achieving not only ultra light weight, ultra thin film, high integration but also transparency and flexibility. As part of efforts to find such electronic materials, materials of two-dimensional structure have been actively researched and studied in recent years.

Two-dimensional molecular layer materials are attracting attention as next-generation electronic materials due to their specific properties such as physical, chemical, electrical, and optical properties that were not found in bulk. For example, in Korean Patent Laid-Open Publication No. 10-2009-0106948 (Application No. 10-2008-0032369), a two-dimensional photonic crystal structure is formed by combining a nano-spiral lithography process and an atomic layer deposition technique, , A method of improving the luminous efficiency is disclosed.

In addition, graphene is a two-dimensional material that has undergone much research to solve the problems of the conventional electronic materials described above. Due to the inherent band structure of graphene, there is no band gap. Due to this, due to the high off current characteristic, there is a problem in that it is not suitable as a material of the switching element because of its low on / off current ratio. In order to solve this problem, researches are being carried out to form a band gap by processing into a ribbon and a mesh so that the graphene has semiconductor characteristics. However, when graphene has a bandgap, the charge mobility is drastically lowered, and ribbon and mesh processes have a disadvantage of low reproducibility.

Accordingly, there is a demand for a two-dimensional electronic material which can be manufactured at a process temperature that does not affect a flexible substrate so as to be easily applied to a flexible device, has a high charge mobility and an on / off current ratio, Development is necessary.

Korean Patent Publication No. 10-2009-0106948

SUMMARY OF THE INVENTION The present invention provides a method of manufacturing a thin film including a two-dimensional compound layer of metal and a chalcogen, and a transistor including the thin film.

Another technical problem to be solved by the present invention is to provide a manufacturing method of a thin film which is flexible and easy to produce at a large area / low cost, and a transistor including the same.

It is another object of the present invention to provide a transistor of high mobility and high reliability.

In order to solve the above technical problems, the present invention provides a method for manufacturing a thin film.

According to one embodiment, the method of making the thin film comprises the steps of preparing a substrate, providing a first source comprising chalcogen on the substrate, and depositing a metal on the substrate To form a two-dimensional compound layer of the chalcogen and the metal on the substrate.

According to one embodiment, the two-dimensional compound layer may be formed at a process temperature of 140-150 ° C.

According to one embodiment, the method of manufacturing the thin film may further include pretreating the substrate before providing the first source on the substrate, and removing oxygen on the substrate surface.

According to one embodiment, pretreating the substrate may comprise providing a hydrogen plasma on the substrate.

According to one embodiment, the thin film manufacturing method may further include post-treating the two-dimensional compound layer to remove oxygen from the two-dimensional compound layer.

According to one embodiment, pretreatment of the substrate and post-treatment of the two-dimensional compound layer may involve being performed using the same kind of plasma.

According to one embodiment, the method of manufacturing the thin film includes repeating the step of providing the first source and the step of providing the second source to form a multilayer film in which the two-dimensional compound layer is stacked in plurality As shown in FIG.

According to one embodiment, the metal may include at least one of tin (Sn), molybdenum (Mo), and tungsten (W).

According to one embodiment, the chalcogen may comprise at least one of sulfur (S), selenium (Se), or tellurium (Te).

According to one embodiment, the substrate may comprise a flexible one.

According to an aspect of the present invention, there is provided a transistor.

According to one embodiment, the transistor comprises a two-dimensional compound layer made according to the method of manufacturing a thin film according to the embodiments described above, a gate electrode overlapping the two-dimensional compound layer, and a gate between the gate electrode and the two- And may include an insulating film.

According to an embodiment of the present invention, a two-dimensional compound layer of metal and chalcogen may be formed by providing a first source comprising a chalcogen and a second source comprising a metal. Thus, a method of manufacturing a two-dimensional compound layer that facilitates large-area and low-cost production can be provided.

Further, according to an embodiment of the present invention, there is provided a transistor including the two-dimensional compound layer of the metal and the chalcogen. Due to the high mobility of the two-dimensional compound layer and the high on / off current ratio characteristics, a highly reliable transistor can be provided.

1 is a flowchart illustrating a method of manufacturing a thin film according to an embodiment of the present invention.
2 to 4 are cross-sectional views illustrating a method of manufacturing a thin film according to an embodiment of the present invention.
5 is a diagram showing a molecular model of a two-dimensional compound layer including tin and chalcogen produced according to a method of manufacturing a thin film according to an embodiment of the present invention.
6 is a cross-sectional view illustrating a method of manufacturing a thin film according to another embodiment of the present invention.
FIG. 7 is a view for explaining an embodiment of a transistor including a two-dimensional compound layer of a metal and a chalcogen fabricated according to a method of manufacturing a thin film according to embodiments of the present invention.
FIG. 8 is a view for explaining another embodiment of a transistor including a two-dimensional compound layer of a metal and a chalcogen fabricated according to a method of manufacturing a thin film according to embodiments of the present invention.
9 is an XRD graph for explaining the characteristics of a two-dimensional compound layer of tin and sulfur produced according to the method of manufacturing a thin film according to an embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the technical spirit of the present invention is not limited to the embodiments described herein but may be embodied in other forms. Rather, the embodiments disclosed herein are provided so that the disclosure can be thorough and complete, and will fully convey the concept of the invention to those skilled in the art.

In this specification, when an element is referred to as being on another element, it may be directly formed on another element, or a third element may be interposed therebetween. Further, in the drawings, the thicknesses of the films and regions are exaggerated for an effective explanation of the technical content.

Also, while the terms first, second, third, etc. in the various embodiments of the present disclosure are used to describe various components, these components should not be limited by these terms. These terms have only been used to distinguish one component from another. Thus, what is referred to as a first component in any one embodiment may be referred to as a second component in another embodiment. Each embodiment described and exemplified herein also includes its complementary embodiment. Also, in this specification, 'and / or' are used to include at least one of the front and rear components.

The singular forms "a", "an", and "the" include plural referents unless the context clearly dictates otherwise. It is also to be understood that the terms such as " comprises "or" having "are intended to specify the presence of stated features, integers, Should not be understood to exclude the presence or addition of one or more other elements, elements, or combinations thereof. Also, in this specification, the term "connection " is used to include both indirectly connecting and directly connecting a plurality of components.

In the following description of the present invention, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

FIG. 1 is a flow chart for explaining a method of manufacturing a thin film according to an embodiment of the present invention, FIGS. 2 to 4 are sectional views for explaining a method of manufacturing a thin film according to an embodiment of the present invention, FIG. 2 is a diagram showing a molecular model of a two-dimensional compound layer including tin and chalcogen produced according to a method of manufacturing a thin film according to an embodiment of the present invention.

Referring to FIGS. 1 and 2, a substrate 100 is prepared (S110). The substrate 100 may be a flexible substrate. Alternatively, the substrate 100 may be a plastic substrate, a glass substrate, or a semiconductor substrate (for example, a silicon substrate, a compound semiconductor substrate, or the like). For example, the substrate 100 may include any one of polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polycarbonate (PC), polyether sulfone (PES), polyimide (PI) In the embodiment of the present invention, the type of the substrate 100 is not limited.

The substrate 100 may be pretreated (S120). The substrate 100 may be pretreated to remove oxygen O present on the surface of the substrate 100. For example, the pretreatment process of the substrate 100 may include providing a hydrogen plasma 110 on the surface of the substrate 100.

Referring to FIGS. 1 and 3, a first source including a chalcogen may be provided on the preprocessed substrate 100 (S130). The chalcogen may include at least one of sulfur (S), selenium (Se), or tellurium (Te), for example. For example, the first from the source, H 2 S, S 2, H 2 Se, H 2 Te, (Et 3 Si) 2 S, (Et 3 Si) 2 Se, or (Et 3 Si) 2 Te And may include at least any one of them.

A second source comprising a metal is provided on the substrate 100 so that the metal contained in the second source and the chalcogen contained in the first source react on the substrate 100, A two-dimensional compound layer of the metal and the chalcogen may be formed.

According to one embodiment, the metal contained in the second source may be tin (Sn). In this case, the two-dimensional compound layer 120 may be a compound of tin and chalcogen (for example, SnS 2 , SnSe 2 , or SnTe 2 ). 5 illustrates a molecular model of a two-dimensional compound (e.g., SnS 2 , SnSe 2 , or SnTe 2 ) of tin 120A and chalcogen 120B, according to one embodiment of the present invention, A two-dimensional compound layer having the molecular model shown in Fig. 5 can be produced on the substrate 100. [

According to another embodiment, the metal contained in the second source may be molybdenum (Mo). In this case, the two-dimensional compound layer 120 may be a compound of molybdenum and chalcogen (for example, MoS 2 ). According to another embodiment, the metal included in the second source may be tungsten (W). In this case, the scarifying two-dimensional compound layer 120 may be a compound of tungsten and chalcogen (for example, WS 2 ). According to yet another embodiment, the first source may comprise a plurality of types of chalcogen. In this case, the second-dimensional compound layer 120 may be formed by depositing a metal contained in the second source and a compound of the plurality of kinds of chalcogenes (for example, SnS x Se 1-x , SnS x , Te 1-x , SnSe x Te 1-x , or SnS x Se y Te z , x, y, z may be 0 or more and 1 or less).

According to one embodiment, the two-dimensional compound layer 120 of the metal and the chalcogen may be formed by atomic layer deposition (ALD). According to another embodiment, the two-dimensional compound layer 120 may be formed by a chemical vapor deposition (CVD) method, a low pressure CVD method, a metalorganic chemical vapor deposition (CVD) method, a plasma chemical vapor deposition CVD), metalorganic ALD, or plasma ALD (plasma ALD).

When the process temperature for producing the two-dimensional compound layer 120 exceeds 150 ° C, it is not easy to be formed into a two-dimensional structure. Further, when the process temperature for producing the two-dimensional compound layer 120 is less than 140 캜, it is not easy to form an amorphous state and form a two-dimensional structure. Thus, according to an embodiment of the present invention, the two-dimensional compound layer 120 can be formed at 140-150 ° C using the first source comprising the chalcogen and the second source comprising the metal have.

Referring to FIGS. 1 and 4, the two-dimensional compound layer 120 may be post-treated (S150). When the two-dimensional compound layer 120 is exposed to the atmosphere, oxygen present in the atmosphere may be located in the two-dimensional compound layer 120. By the post-treatment process of the two-dimensional compound layer 120, the oxygen located in the two-dimensional compound layer 120 can be removed. The post-treatment process of the two-dimensional compound layer 120 may be performed using a plasma (for example, hydrogen plasma) of the same kind as the pretreatment process of the substrate 100. As a result, the process source management can be facilitated and the production cost can be reduced.

According to an embodiment of the present invention, a first source comprising a chalcogen, and a second source comprising a metal are provided on a substrate such that, at a process temperature of 140-150 DEG C, a two-dimensional compound layer of metal and chalcogen . As a result, a method for manufacturing a two-dimensional compound layer of metal and chalcogen can be provided, in which damage to the substrate is minimized while facilitating large-area and low-cost production.

The method for producing a two-dimensional compound layer of metal and chalcogen using a peeling method has a low reproducibility and is difficult to apply to a large area. Furthermore, when a two-dimensional compound layer of metal and chalcogen is produced using a deposition method at high temperature, it is not easy to manufacture a two-dimensional compound layer of metal and chalcogen on a flexible substrate due to the problem of substrate damage.

However, as described above, according to the embodiment of the present invention, a two-dimensional compound layer of metal and chalcogen can be formed by a method such as atomic layer deposition at a processing temperature of 140 to 150 ° C, And a method of manufacturing a two-dimensional compound layer having high reproducibility, large area, and low cost can be provided.

According to another embodiment of the present invention, unlike the above-described embodiments, a multilayer film in which a plurality of the two-dimensional compound layers 120 of the metal and the chalcogen are stacked can be provided. This will be described with reference to FIG.

6 is a cross-sectional view illustrating a method of manufacturing a thin film according to another embodiment of the present invention.

Referring to FIG. 6, in the method described with reference to FIGS. 1 to 5, a substrate 100 is provided, and a pre-processing process of the substrate 100 is performed. According to the method described with reference to Figures 1 to 5 on the substrate 100, a first source comprising a chalcogen and a second source comprising a metal are provided, wherein the chalcogen and the metal 1 < / RTI > two-dimensional compound layer 121 may be formed.

Repeating the steps of providing the first source and the second source on the first two-dimensional compound layer (121) according to the method described with reference to Figures 1 to 5, so that the chalcogen and the metal A second two-dimensional compound layer 122 of the first two-dimensional compound layer 122 and a third two-dimensional compound layer 123 on the second two-dimensional compound layer 122 may be sequentially formed. Accordingly, the multi-layered film 120M in which the first to third two-dimensional compound layers 121 to 123 are stacked can be formed.

Although three layers of two-dimensional compound layers are shown as being laminated in Fig. 6, it is obvious that two or four or more two-dimensional compound layers can be laminated. In addition, a boundary line is shown between each two-dimensional compound layer, but the boundary line is omitted so that a plurality of stacked two-dimensional compound layers can form one body.

According to one embodiment, after the multilayer film 120M is formed, the multilayer film 120M may be post-processed by the method described with reference to FIGS. Alternatively, according to another embodiment, after each of the first to third two-dimensional compound layers 121 to 123 is formed, the post-treatment process of the two-dimensional compound layer described with reference to Figs. 1 and 4 may be performed have.

The two-dimensional compound layer or multilayer film described with reference to Figs. 1 to 6 can be used as an active layer of a transistor. This will be described with reference to FIGS. 7 and 8. FIG.

FIG. 7 is a view for explaining an embodiment of a transistor including a two-dimensional compound layer of a metal and a chalcogen fabricated according to a method of manufacturing a thin film according to embodiments of the present invention.

Referring to Fig. 7, a substrate 200 is provided. According to one embodiment, the substrate 200 may be a glass substrate or a plastic substrate. According to another embodiment, the substrate 200 may be a semiconductor substrate.

An active layer 210 is provided on the substrate 100. The active layer 210 may be a multilayer film in which a two-dimensional compound layer of chalcogen and metal or a two-dimensional compound layer of chalcogen and metal is stacked as described with reference to FIGS. 1 to 6.

A gate insulating layer 210 covering the active layer 210 is provided. For example, the gate insulating film 210 may be formed of a high dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, or metal oxide (e.g., aluminum oxide or hafnium oxide).

A gate electrode 230 is provided on the gate insulating layer 210. The gate electrode 230 may overlap the active layer 210 with the gate insulating layer 210 interposed therebetween. The gate electrode 230 may be formed of a metal. For example, the gate electrode 230 may be formed of nickel, chromium, molybdenum, aluminum, titanium, copper, tungsten, or an alloy thereof. The gate electrode 230 may be formed of a single layer or multiple layers using the metal. For example, the gate electrode 230 may be a triple layer in which molybdenum, aluminum, and molybdenum are sequentially stacked, or a double layer in which titanium and copper are sequentially stacked. Or a single film of an alloy of titanium and copper. Alternatively, the gate electrode 230 may be formed of a transparent conductive material.

An interlayer insulating film 250 covering the gate electrode 230 and the gate insulating film 220 is provided. The interlayer insulating layer 250 may be formed of a silicon oxide layer.

A drain electrode 240d which penetrates the interlayer insulating layer 250 and contacts a part of the active layer 210 on one side of the gate electrode 230 and a drain electrode 240d which penetrates the interlayer insulating layer 250, And a source electrode 240s that is in contact with a portion of the active layer 210 on the other side may be provided. The drain electrode 240d and the source electrode 240s

Nickel, chromium, molybdenum, aluminum, titanium, copper, tungsten, and alloys thereof. The source electrode 240s and the drain electrode 240d may be formed of a single layer or a multi-layer using the metal. For example, the source electrode 240s and the drain electrode 240d may be a double layer in which titanium and copper are sequentially stacked. Or a single film made of an alloy of titanium and copper. Alternatively, the source electrode 240s and the drain electrode 240d may be formed of a transparent conductive material.

FIG. 8 is a view for explaining another embodiment of a transistor including a two-dimensional compound layer of a metal and a chalcogen fabricated according to a method of manufacturing a thin film according to embodiments of the present invention.

Referring to Fig. 8, a substrate 300 is provided. The substrate 300 may be the same as the substrate 200 described with reference to FIG.

A gate electrode 330 is provided on the substrate 300. The gate electrode 330 may be formed of the same material as the gate electrode 230 described with reference to FIG.

A gate insulating layer 320 is provided on the gate electrode 330. The gate insulating layer 320 may be formed of the same material as the gate insulating layer 220 described with reference to FIG.

An active layer 310 overlapping the gate electrode 330 may be provided on the gate insulating layer 320. The active layer 310 may be a multilayer film in which a two-dimensional compound layer of chalcogen and metal or a two-dimensional compound layer of chalcogen and metal is stacked as described with reference to FIGS. 1 to 6.

A passivation film 350 is provided to cover the active layer 310. For example, the passivation film 350 may be formed of a silicon oxide film.

A drain electrode 340d and a source electrode 340s which are in contact with a part of the active layer 330 adjacent to one side and the other side of the passivation film 350 may be provided . The drain electrode 340d and the source electrode 340s may be formed of the same material as the drain electrode 240d and the source electrode 240s described with reference to FIG.

According to the embodiment of the present invention, a transistor using as a active layer a multilayer film in which a two-dimensional compound layer of chalcogen and metal or a two-dimensional compound layer of chalcogen and metal are stacked as described with reference to Figs. 1 to 6 Can be provided. Due to the high mobility characteristics of the two-dimensional compound layer and the high on / off current ratio, a highly reliable transistor can be provided.

In addition to the structure of the transistors shown in Figs. 7 and 8, the active layer of transistors having various structures may be formed by using the two-dimensional compound layer of chalcogen and metal described with reference to Figs. 1 to 6, May be used.

9 is an XRD graph for explaining the characteristics of a two-dimensional compound layer of tin and sulfur produced according to the method of manufacturing a thin film according to an embodiment of the present invention.

Referring to FIG. 9, a TDMASn precursor as a first source containing tin and a H 2 S gas as a second source containing chalcogenine sulfur are supplied into the chamber at a processing temperature of 60 ° C to 180 ° C, A 50 nm thick SnS x (where X is a positive integer) film was deposited.

As can be seen from FIG. 9, SnS 2 having a rhombohedral crystal structure was formed at a process temperature of 140 to 150 ° C having a peak in the (001) plane, and no peak was found at a temperature lower than 140 ° C, State SnS 2 is formed. Further, it can be confirmed that SnS having a crystal structure of orthorhombic crystal having peaks at (120) and (111) planes was formed at a temperature higher than 150 ° C.

It is thus understood that the preparation of a compound layer of tin and sulfur using sources containing tin and sulfur at a process temperature of 140-150 占 폚 is an effective method of forming a two-dimensional compound layer of metal and chalcogen having a layered structure have.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the scope of the present invention is not limited to the disclosed exemplary embodiments. It will also be appreciated that many modifications and variations will be apparent to those skilled in the art without departing from the scope of the present invention.

100, 200, 300: substrate
110, 130: hydrogen plasma
120, 121, 122, 123: Two-dimensional compound layer
120A: Annotation
120B: Calcogen
120M: multilayer film
210, and 310:
220, 320: gate insulating film
230, 330: gate electrode
240d, 340d: drain electrode
240s, 340s: source electrode
250: interlayer insulating film
350: passivation membrane

Claims (12)

Preparing a substrate;
Providing a first source comprising sulfur on the substrate; And
Providing a second source including tin on the substrate to form a two-dimensional compound layer containing the sulfur and the tin and having a rhombohedral crystal structure at a processing temperature of 140 to 150 ° C, And forming the thin film on the substrate.
delete The method according to claim 1,
Before providing the first source on the substrate,
Further comprising pretreating the substrate to remove oxygen on the surface of the substrate.
The method of claim 3,
Wherein pretreating the substrate comprises providing a hydrogen plasma on the substrate.
The method of claim 3,
Further comprising the step of post-treating the two-dimensional compound layer to remove oxygen in the two-dimensional compound layer.
6. The method of claim 5,
Wherein the pretreatment of the substrate and the post-treatment of the two-dimensional compound layer are performed using the same type of plasma.
The method according to claim 1,
Wherein the step of providing the first source and the step of providing the second source are repeated to form a multilayer film in which the two-dimensional compound layer is laminated in plural.
delete delete The method according to claim 1,
Wherein the substrate is flexible.
A method for producing a thin film according to claim 1, comprising the steps of: preparing the two-dimensional compound layer;
Forming a gate electrode overlying the two-dimensional compound layer; And
And forming a gate insulating film between the gate electrode and the two-dimensional compound layer.
Preparing a substrate;
Providing a first source comprising a chalcogen element on the substrate;
Providing a second source comprising a metal on the substrate to form a two-dimensional compound layer containing the chalcogen element and the metal and having a rhombohedral crystal structure by atomic layer deposition at a processing temperature of 140-150 ° C, To form a thin film on the substrate.
KR1020140102524A 2014-08-08 2014-08-08 Method of fabricating layer comprising metal and chalcogen, and transistor comprising the same KR101565255B1 (en)

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KR20210014353A (en) * 2019-07-30 2021-02-09 한양대학교 산학협력단 Method for controlling crystal growth behavior of thin-film

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KR101179010B1 (en) 2011-02-01 2012-08-31 연세대학교 산학협력단 Chalcogenide semiconductor thin film and fabrication method thereof

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KR20210014353A (en) * 2019-07-30 2021-02-09 한양대학교 산학협력단 Method for controlling crystal growth behavior of thin-film
KR102311396B1 (en) 2019-07-30 2021-10-12 한양대학교 산학협력단 Method for controlling crystal growth behavior of thin-film

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