KR101561344B1 - Hybrid pulse generator for automotive radar using ultra wide band - Google Patents

Abstract

The present invention relates to an apparatus for generating a hybrid UWB pulse.
A hybrid UWB pulse generation apparatus of the present invention includes: a clock generator receiving an external signal and outputting a low clock and a high clock having a signal width longer than that of the low clock; A counter for receiving a low clock from the clock generator and outputting a counter signal; A plurality of MUXs sequentially receiving signals output from the counter unit; A signal selector for controlling operation of at least one of the plurality of muxes based on a predetermined value; And a signal processor for receiving the high clock and outputting a pulse signal by aligning values output from the at least one mux.
According to the present invention, a digital pulse signal having various pulse widths can be generated by using an FPGA, unlike a pulse signal implemented using a conventional analog signal.

Description

HYBRID PULSE GENERATOR FOR AUTOMOTIVE RADAR USING ULTRA WIDE BAND BACKGROUND OF THE INVENTION [0001]

The present invention relates to a hybrid UWB pulse generation apparatus, and is intended to provide a hybrid UWB pulse generation apparatus for a vehicle radar capable of generating a digital pulse signal having various pulse widths in an automobile radar.

In general, automotive radar is a short-range vehicle detection system for ITS (Intelligent Transport System), and has received much attention in recent years. Typically, short range radars (SRRs) are widely used in automotive detection and surveillance systems.

Since the SRR has been applied to automobiles, the Federal Communications Commission (FCC) has established a spectrum from 22 to 29 GHz for UWB radar within a limited power of -41.3 dBM / MHz.

Here, according to the FCC, one frequency band of UWB (ULTRA WIDE BAND) is defined to occupy more than 500 MHz or more than 20% of the center frequency band.

Accordingly, a UWB radar has a pulse generator in the radar having a pulse width of 2 ns.

Conventional pulse generators use CMOS to implement a single chipset, but because flexibility is a characteristic that can be applied to various devices, a pulse generator using a Field Programmable Gate Array (FPGA) Many generators are being studied.

However, the pulse generator using the FPGA is considerably better than the conventional CMOS in terms of flexibility. However, in the case of generating a digital pulse signal, a pulse generator generating only a broadened pulse width having a narrow bandwidth There is a problem.

The background art of the present invention is disclosed in Korean Patent Laid-Open Publication No. 10-2013-0095742 (published on Mar. 28, 2018).

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a hybrid UWB pulse generator for an automotive radar capable of generating a digital pulse signal having various pulse widths in an automobile radar.

According to an aspect of the present invention, there is provided an apparatus for generating a hybrid UWB pulse, the apparatus including: a clock generator receiving an external signal and outputting a low clock and a high clock having a signal width that is longer than the low clock; A counter for receiving a low clock from the clock generator and outputting a counter signal; A plurality of MUXs sequentially receiving signals output from the counter unit; A signal selector for controlling operation of at least one of the plurality of muxes based on a predetermined value; And a signal processor for receiving the high clock and outputting a pulse signal by aligning values output from the at least one mux.

Here, the hybrid UWB pulse generator may further include a comparator for comparing the input signal input from the counter with a preset value input from the outside, and outputting the counter signal to the plurality of muxes when the compared values match .

Here, the plurality of muxes are connected to the comparator and the signal processor, respectively, and the counter signals inputted from the comparator are sequentially divided and input, and when selected by the signal selector, An output value corresponding to the counter signal can be generated and transmitted to the signal processing unit.

The signal selector may match the order of the muxes to have the predetermined value and control the at least one mux of the muxes to provide an output value to the signal processor according to the predetermined value.

Here, the hybrid UWB pulse generator may be implemented on a Field Programmable Gate Array (FPGA).

As described above, according to the present invention, a digital pulse signal having various pulse widths can be generated by using an FPGA, unlike a pulse signal implemented using a conventional analog signal.

FIG. 1 is a block diagram of a hybrid UWB pulse generator applied to an automotive radar according to an embodiment of the present invention. Referring to FIG.
2 is a detailed block diagram of a UWB digital pulse generation module of a hybrid UWB pulse generation apparatus according to an embodiment of the present invention.
3 is a diagram illustrating a signal flow between respective units in the UWB digital pulse generation module of the hybrid UWB pulse generation apparatus according to the embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings, which will be readily apparent to those skilled in the art. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. In order to clearly illustrate the present invention, parts not related to the description are omitted, and similar parts are denoted by like reference characters throughout the specification.

Throughout the specification, when an element is referred to as "comprising ", it means that it can include other elements as well, without excluding other elements unless specifically stated otherwise.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily carry out the present invention.

FIG. 1 is a block diagram of a hybrid UWB pulse generator applied to an automotive radar according to an embodiment of the present invention. FIG. 2 is a detailed block diagram of a UWB digital pulse generation module of a hybrid UWB pulse generator according to an embodiment of the present invention. FIG. 3 is a diagram illustrating a signal flow between respective devices in the UWB digital pulse generation module of the hybrid UWB pulse generation device according to the embodiment of the present invention.

1, a hybrid UWB (UWB) pulse generator applied to a vehicle radar according to an embodiment of the present invention includes a UWB digital pulse generation module 100 and a 24 GHz RF conversion Module 200 as shown in FIG.

The UWB digital pulse generation module 100 includes a Narrow Bandwidth (NW) pulse generator 110 and a Pulse Chopper 120. [ Here, the UWB digital pulse generation module 100 is implemented on a field programmable gate array (FPGA).

Referring to FIG. 2, the UWB digital pulse generation module 100 includes a narrowband pulse generator 110, a pulse chopper 120, and a clock generator 130.

The narrowband pulse generator 110 includes a comparator 111 and a counter 112. The narrowband pulse generator 110 generates a low clock (hereinafter referred to as "low clock ") from a phase locked loop (PLL) (Hereinafter also referred to as " LC "), generates a pulse signal, and transmits it to the pulse chopper 120.

The comparator 111 compares the counter signal input from the counter 112 with an externally input signal (set to 1). If the comparison result is the same, And outputs a signal.

The counter 112 receives a clock signal from the clock generator 130 and outputs a counter signal when the received clock signal is input a predetermined number of times. For example, when the counter unit 112 receives five clock signals from the clock generation unit 130, it outputs one counter signal.

The pulse chopper 120 includes a plurality of muxes 121, a multiplexer (MUX), a signal selector 122 and a serializer-deserializer 123, The pulse signal generated from the narrowband pulse generating unit 110 using the high clock (HC) (hereinafter also referred to as a "high clock") input from the generating unit 130 by the mux 121 And selectively receives and outputs a digital pulse signal DOHC.

The plurality of muxes 121 are connected to the comparing unit 111 and the signal processing unit 123 of the narrowband pulse generating unit 110 and respectively output the low signals DOLC input from the narrowband pulse generating unit 110 Only the muxes selected by the signal selection unit 122 are generated and transmitted to the signal processing unit 123. [

For example, if the signal output by the narrowband pulse generator 110 is a 10-ns pulse signal, the pulse signal input to the mux 121 is 2 ns in 10 ns / 5 (consisting of 5 muxes) .

3, when the signal selector 122 sets the code value to 10000, the output signals of the first and second multiplexers 121 and 121, -1) to generate an output value, and transmits the generated output value to the signal processing unit 123. At this time, the signal processing unit 123 outputs a pulse signal DOHC having a 2 ns signal input from the first mux 121-1.

If the signal selector 122 is set to 11000, only the first and second muxes 121-1 and 121-2 of the muxes 121 operate to transmit the output value to the signal processor 123. [ At this time, the signal processing unit 123 outputs a pulse signal DOHC of 4 ns, which is input from the first and second muxes 121-1 and 121-2, and aligns 2 ns signals.

If 11100 is set in the signal selection unit 122, only the first, second, and third muxes 121-1, 121-2, and 121-3 of the muxes 121 operate, (123). At this time, the signal processing unit 123 outputs a pulse signal DOHC of 6 ns, which is obtained by arranging signals of 2 ns inputted from the first, second and third muxes 121-1, 121-2 and 121-3 .

If 11111 is set in the signal selection unit 122, all of the muxes 121 are operated and all signals output from the muxes 121 are input to the signal processing unit 123. At this time, the signal processing unit 123 aligns all the signals of the input muxes 121 and outputs a signal of 10 ns as a pulse signal.

The signal selection unit 122 stores a predetermined value and selects a value output from each of the muxes 121 based on a predetermined value and outputs the selected value to the signal processing unit 123. [

The signal processing unit 123 receives the high clock from the clock generating unit 130 and generates signals as a single signal by aligning the signals inputted from the plurality of muxes 121 and outputs the generated pulse signal DOHC Output.

A phase locked loop (PLL) 130 generates a low clock and a high clock by receiving an external signal and supplies the generated low clock to the counter unit 112 and the pulse chopper 120, and transmits the generated high clock to the pulse chopper 120.

For example, when receiving an external signal of 50 MHz, the clock generating unit 130 generates a clock of 100 MHz as a low clock and a clock of 500 MHz as a high clock to output a clock signal to the counter unit 112 of the pulse generating unit 110 and the pulse chopper 120 and the pulse chopper 120, respectively.

The 24 GHz RF (Radio Frequency) conversion module 200 converts a signal input from the UWB digital pulse generation module 100 into a 24 GHz signal and outputs the signal.

Meanwhile, although the hybrid UWB pulse generation apparatus according to the embodiment of the present invention is implemented in an automobile radar, it can also be implemented in a radar, a communication device, an electronic device, etc. that require a digital pulse signal outside an automobile radar.

The hybrid UWB pulse generator according to the present invention can generate a digital pulse signal having various pulse widths using an FPGA, unlike a pulse signal using a conventional analog signal. .

While the present invention has been described with reference to exemplary embodiments, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims. Accordingly, the true scope of the present invention should be determined by the technical idea of the appended claims.

100: UWB digital pulse generation module 110: Narrowband pulse generation unit
111: comparator 112: counter
120: Pulse chopper 121: MUX
122: Signal selection unit 123: Signal processing unit
130: clock generating unit 200: 24 GHz RF converting module

Claims (5)

A clock generator receiving an external signal and outputting a low clock and a high clock having a signal width longer than that of the low clock;
A counter for receiving the low clock from the clock generator and generating a counter signal;
A comparator for comparing the counter signal input from the counter with an externally input set value and outputting the counter signal when the compared values match;
A plurality of MUXs dividing and inputting the counter signals sequentially input from the comparison unit and generating output values corresponding to the divided input signals;
A signal selector having a predetermined value matched to the order of the muxes and controlling operation of at least one of the muxes by the predetermined value; And
A signal processor for receiving the high clock and outputting a pulse signal by sorting the values output from the at least one mux,
And a second UWB pulse generator for generating a second UWB pulse. delete delete delete The method according to claim 1,
A hybrid UWB pulse generator implemented on an FPGA (Field Programmable Gate Array).

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