KR101525589B1 - Data storage device and data processing system having the same - Google Patents

Abstract

A data storage device according to the present invention is a data storage device for exchanging data with a plurality of memory devices and a plurality of memory devices via a plurality of channels and a channel for accessing the plurality of memory devices according to an external command (VS_CMD) (VS_CMD) is a vendor specific instruction provided from the outside by referring to a BIOS setting value. The memory controller controls the bandwidth of the memory device or the number of memory devices accessed by interleaving.

Description

DATA STORAGE DEVICE AND DATA PROCESSING SYSTEM HAVING THE SAME [0002]

The present invention relates to an electronic device, and more particularly to a data storage device and an information processing system including the same.

2. Description of the Related Art Generally, a flash memory is widely used for computers, memory cards and the like because it has a function of electrically erasing cell data collectively. 2. Description of the Related Art In recent years, portable information devices such as mobile phones, PDAs, and digital cameras have been rapidly used, and flash memories are widely used as storage devices in place of hard disk drives (HDDs).

In recent years, flash memory has been used as a storage medium for replacing a hard disk drive (HDD) according to technological progress and price reduction of a flash memory device. The above-described storage device is also referred to as a semiconductor disk device or a solid state drive or a solid state disk. Hereinafter, it will be simply referred to as an SSD. According to the access operation to the SSD, although the data can be input / output at high speed, the mechanical delay and the failure rate are remarkably small. In addition, the SSD is advantageous in that data is not easily damaged even in the event of an external impact, heat generation, noise and power consumption are reduced, and the SSD can be reduced in size and weight. Thus, the demand for SSDs that do not use mechanically rotating platters is increasing rapidly with low power, high capacity mobile trends.

One of the strengths of SSDs versus hard disk drives (HDDs) was low power consumption. However, with the recent demand for higher capacity and higher performance, there is a growing demand for SSDs with higher power efficiency.

An object of the present invention is to provide a solid state drive capable of adjusting the amount of power consumption and an information processing system including the solid state drive.

According to an aspect of the present invention, there is provided a storage device for exchanging data with a plurality of memory devices and a plurality of memory devices via a plurality of channels, (VS_CMD) is a vendor-specific instruction provided externally with reference to a BIOS (BIOS) setting value. The memory controller controls the channel bandwidth for accessing the BIOS or the number of memory devices accessed interleaved.

In an embodiment, the memory controller decodes the instruction (VS_CMD) to generate a driving power mode (P_mode), and activates some or all of the plurality of channels in accordance with the driving power mode (P_mode).

In an embodiment, the memory controller adjusts the number of memory devices accessed interleaved in the activated channel according to the driving power mode (P_mode).

In an embodiment, the memory controller adjusts the access start time of each of the activated channels differently according to the driving power mode (P_mode).

The memory controller may further include a buffer memory for buffering data under the control of the memory controller. The memory controller adjusts a clock frequency for driving the buffer memory according to the driving power mode (P_mode).

In an embodiment, the memory controller further comprises a central processing unit for decoding the instruction (VS_CMD), wherein the clock frequency of the central processing unit is adjusted according to the driving power mode (P_mode).

In an embodiment, the memory controller adjusts the frequency of the clock for exchanging data in the activated channel according to the driving power mode (P_mode).

In an embodiment, the plurality of memory devices is configured as a flash memory device, and the plurality of memory devices and the memory controller are provided as a solid state drive.

According to another aspect of the present invention, there is provided a storage device including a plurality of memory devices and a plurality of memory devices for exchanging data with the plurality of memory devices through a plurality of channels, And a memory controller that adjusts the channel bandwidth for accessing the plurality of memory devices with reference to the number of interleaved memory devices to be accessed.

According to still another aspect of the present invention, there is provided an information processing system including a host that issues a command (VS_CMD) with reference to BIOS (BIOS) setting information and a host that issues a command in response to the command (VS_CMD) And a solid state drive operating at a corresponding performance.

According to the present invention, the driving power mode of the solid state drive can be set by referring to the BIOS setting information. Therefore, it is possible to increase the stability of the information processing system by preventing the rapid decrease of the residual power due to the rapid increase of the instantaneous power consumption.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and should provide a further description of the claimed invention. Reference numerals are shown in detail in the preferred embodiments of the present invention, examples of which are shown in the drawings. Wherever possible, the same reference numbers are used in the description and drawings to refer to the same or like parts.

Hereinafter, a solid state drive (SSD) will be used as an example of a nonvolatile memory system for explaining the features and functions of the present invention. However, those skilled in the art will readily appreciate other advantages and capabilities of the present invention in accordance with the teachings herein. In addition, although a NAND flash memory is exemplified as a storage medium, it may be configured with other nonvolatile memory devices. For example, PRAM, MRAM, ReRAM, FRAM, NOR flash memory, or the like can be used as a storage medium, and the present invention can be applied to a memory system in which heterogeneous memory devices are mixed.

The present invention may be implemented or applied through other embodiments. In addition, the detailed description may be modified or modified in accordance with the aspects and applications without departing substantially from the scope, spirit and other objects of the invention. Hereinafter, embodiments according to the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram showing an information processing system 100 of the present invention. Referring to FIG. 1, an information processing system 100 of the present invention includes a host 110 and an SSD 120.

Host 110 controls SSD 120 to store data or to read stored data. The SSD 120 stores data in the memory devices 123, 124, and 125 in response to a read / write request from the host 110, or reads the stored data. In particular, the host 110 includes a basic input / output system (BIOS) 111, which is a basic input / output system of the information processing system 100.

The BIOS 111 contains the most basic setting information of the information processing system 100. For example, in the BIOS 111, code and setting information for controlling basic input / output devices are stored in the information processing system 100. In addition, the user can adjust the basic functions by changing the set values of the BIOS 111. [ The BIOS 111 is mounted on the main board of the information processing system 100 in the form of a ROM chip.

At the initial booting of the information processing system 100, the user can select, inspect, change and adjust various hardware devices installed in the information processing system 100 using the setting program of the BIOS 111. For example, the user can adjust the date and time of the built-in clock by using the setting program of the BIOS 111, or select the type and transmission mode of the solid state drive (SSD) or the optical disk drive (ODD). In addition, through the BIOS 111 setup program, the user can select whether or not to use the L1 and L2 cache of the CPU, adjust the memory test and operation speed, select the priority of the boot drive, adjust the keyboard speed, Settings, interrupt changes, serial and parallel port selection, and so on.

In addition, when power of the information processing system 100 by the user is provided, the BIOS 111 sequentially checks various hardware devices so that the information processing system 100 can operate normally. If there is no abnormality in the check result, the BIOS 111 transfers the boot authority to the OS boot loader. This process is called POSTing (Power On Self Testing).

The configuration information of the SSD 120 is further included in the BIOS 111 of the present invention. The BIOS 111 further includes a setting mode in which a user can select a driving power mode of the SSD 120. [ Therefore, the operation performance or the driving power mode of the SSD 120 can be selected through the setting of the BIOS 111 by the user.

When the setting of the BIOS 111 is completed, the host 110 provides a control command to the SSD 120 by referring to the SSD power configuration mode of the BIOS 111. [ For example, the host 110 instructs to change or adjust all the drive conditions of the SSD 120 through a vendor specific command (VS_CMD, Vender Spific command).

In response to the vendor specific instruction (VS_CMD), the SSD 120 sets up the drive mode. That is, in response to the vendor specific instruction (VS_CMD), the SSD 120 sets the operating condition in the drive power mode (P_mode) selected in the BIOS 111. For example, the SSD 120 may activate some or all of the channel bandwidths of the memory devices 123, 124, 125 connected to the multiple channels CH.1 to CH.n. Alternatively, the way interleaving scheme for the memory devices in the same channel may be changed to adjust the power consumption in accessing the memory devices 123, 124, 125. Alternatively, the frequency of the data transfer clock of the channel connected to the memory devices 123, 124, and 125 may be adjusted. In addition, the power consumption of the SSD 120 can be adjusted by adjusting the drive clock frequency of the buffer memory 122 and the clock frequency of the central processing unit (CPU, not shown) included in the SSD controller 121.

To this end, the SSD 120 includes an SSD controller 121, a buffer memory 122, and a plurality of memory devices 123, 124, and 125. The SSD 120 decodes the vendor specific instruction (VS_CMD) to control the memory devices 123, 124, 125 and the buffer memory 122 in a mode corresponding to the driving power mode (P_mode).

The SSD controller 121 provides a physical connection between the host 110 and the SSD 120. That is, the SSD controller 121 provides interfacing with the SSD 120 in response to the bus format of the host 110. In particular, the SSD controller 121 decodes the vendor specific instruction (VS_CMD) provided from the host 110. Depending on the decoded result, the SSD controller 121 sets channel bandwidth or way interleaving schemes for the memory devices 123, 124, Alternatively, the SSD controller 121 may also change the clock frequency of the channel. The SSD controller 121 can adjust the drive clock frequency of the buffer memory 122 and the clock frequency of the central processing unit (CPU) in the SSD controller 121 in accordance with the decoding result of the vendor specific instruction (VS_CMD).

In the buffer memory 122, write data provided from the host 110 or data read from the memory devices 123, 124, and 125 are temporarily stored. When data existing in the memory devices 123, 124, and 125 is cached at the time of a read request of the host 110, the buffer memory 230 stores a cache function for directly providing the cached data to the host 110 . At this time, no access to the memory devices 123, 124, 125 occurs. Generally, the data transfer rate by the bus format (for example, SATA or SAS) of the host 110 is much faster than the transfer rate of the channel of the SSD 120. That is, when the interface speed of the host 110 is much higher, performance degradation caused by the speed difference can be minimized by providing the buffer memory 122 with a large capacity.

The buffer memory 122 may be provided to a synchronous DRAM (DRAM) in order to provide sufficient buffering in the SSD 120 used as a large capacity auxiliary storage device. However, it will be apparent to those skilled in the art that the buffer memory 122 is not limited to the disclosure herein.

The memory devices 123, 124, 125 are provided as the storage medium of the SSD 120. For example, the memory devices 123, 124, and 125 may be provided in a NAND-type Flash memory having a large storage capacity. Of course, some or all of the memory devices 123, 124, and 125 may also be configured as volatile DRAMs or SRAMs.

Each of the memory devices 123, 124, and 125 is connected to the SSD controller 121 on a channel-by-channel basis. A plurality of memory devices are connected to one channel, and each of these memory devices is connected to the same data bus. Memory devices as storage media will be exemplified by flash memory devices. However, the memory devices may be configured with other non-volatile memory devices. For example, PRAM, MRAM, ReRAM, FRAM, NOR flash memory and the like can be used as the storage medium.

According to the features described above, the information processing system 100 of the present invention can select the driving power mode (P_mode) of the SSD 120 according to the setting information of the BIOS 111. [ Therefore, the size of the power consumed by the SSD 120 can be adjusted according to the setting of the BIOS 111. This means that the power consumption of the information processing system 100 can be easily changed through the setting of the BIOS 111 in a situation where the power management is preferred over the performance.

2 is a block diagram showing the configurations of the SSD controller 121 of FIG. Referring to FIG. 2, the SSD controller 121 of the present invention includes a central processing unit 210, a host interface 220, a buffer manager 230, and a flash interface 240.

The central processing unit 210 decodes the vendor specific instruction (VS_CMD) transmitted from the host 110 (see FIG. 1). The central processing unit 210 sets the environment to a drive condition corresponding to the vendor specific instruction (VS_CMD). The central processing unit 210 generates arbitrary commands using the values of the control registers (not shown) in the host interface 220 or the flash interface 240. Alternatively, the central processing unit 210 transfers various control information necessary for the read / write operation to the registers of the host 110 and the flash interface 240. [ For example, when a vendor specific instruction (VS_CMD) is inputted from the outside, it is stored in a register (not shown) of the host interface 220. The host interface 220 informs the central processing unit 210 that a read / write command has been input according to the stored command. This operation also occurs between the central processing unit 210 and the flash interface 240. The central processing unit 210 controls the respective components according to the firmware for driving the SSD 120.

The host interface 220 provides a physical connection between the host and the SSD 120. That is, the host interface 220 provides interfacing with the SSD 120 in correspondence with the host bus format. The bus format of the host is composed of USB (Universal Serial Bus), SCSI (Small Computer System Interface), PCI express, ATA, PATA (Parallel ATA), SATA (Serial ATA) .

The host interface 220 may support a disk emulation function that allows a host to recognize the SSD 120 as a hard disk drive (HDD). For example, it provides functions such as a Flash Translation Layer (FTL) to hide deletion operations.

The buffer manager 230 controls the read and write operations of the buffer memory 122 (see FIG. 1). For example, the buffer manager 230 temporarily stores write data and read data in the buffer memory 122. The buffer manager 230 may adjust the frequency of the driving clock of the buffer memory 122 under the control of the central processing unit 210. [ That is, the power consumption of volatile memory such as synchronous DRAM (SDRAM) mounted to provide a large amount of buffering depends largely on the clock frequency. Accordingly, the buffer manager 230 can control the buffer memory 122 to operate with a driving clock of a maximum frequency in a mode in which performance is prioritized and a driving clock in a frequency lower than that in a mode in which power saving is prioritized.

The flash interface 240 exchanges data with the memory devices 123, 124, and 125. The flash interface 240 scatters the data transferred from the buffer memory 120 to each of the channels CH.1, CH.2, ..., CHn. Data read from the non-volatile memories 123, 124, and 125 provided through the channel is collected by the flash interface 240. [ The collected data will then be stored in the buffer memory 122.

The flash interface 240 adjusts the channel bandwidth / interleaving scheme or the frequency of the channel for the memory devices 123, 124, 125 under the control of the central processing unit 210. [ The central processing unit 210 will set the flash interface 240 to operation parameters corresponding to the decoding result (drive power mode, P_mode) of the vendor specific instruction (VS_CMD). Then, the number of way interleaving of memory devices connected to each of the channels (CH.1, CH.2, ..., CHn) and channels is adjusted.

If the driving power mode (P_mode) is the maximum performance mode (or maximum power mode), all channels are active and the number of ways interleaving of each channel will be maximum. Alternatively, depending on the driving power mode (P_mode), only a part of the channels may be activated and the number of interleaving sizes of the activated channels may be limited. That is, the flash interface 240 accesses the memory devices with the operating parameters corresponding to the driving power mode (P_mode) set.

According to the characteristics of the SSD controller 121, the residual power amount of the power source (e.g., battery) of the information processing system 100 can be used most efficiently. Here, there is a difference in terms of the performance and the consumed power, but the power consumption increases as the performance increases. Therefore, these terms are used without discrimination.

FIG. 3 is a block diagram showing the memory devices and channel configuration controlled by the flash interface 240 of FIG. 1 described above. Referring to FIG. 3, the flash interface 240 is connected to memory devices through a plurality of channels (CH.1, CH.2, ..., CH.n).

An input / output port (for example, an 8-bit I / O port) of m memory devices 123 (MEM_11, MEM_12, MEM_1m) is connected to the first channel CH.1 (m is a natural number). The plurality of memory devices 124 and 125 share the input / output ports in the same manner in the second channel (CH.2) and the third channel (CH.3), respectively. When the vendor specific instruction (VS_CMD) is input from the host 110, the central processing unit 210 (see FIG. 2) decodes it and stores it in the register 241 of the flash interface 240. The number of channels to be simultaneously activated among a plurality of channels is determined according to the information stored in the register 241. [ And the number of memory devices (Way) that are simultaneously selected for the way interleaving in each of the channels is determined according to the information stored in the register 241. [

The information stored in the register 241 may further include clock frequency information for exchanging data with the memory devices. In addition, additional channel settings can be made to implement low power consumption. For example, even if a plurality of channels are activated at the same time, the time point at which data is exchanged through each channel may be configured to be different. That is, the operating condition of the flash interface 240 may be set to have a channel skew.

Figures 4A and 4B are tables that briefly illustrate examples of decoding results of a vendor specific instruction (VS_CMD). The operating modes of the SSD 120 varying according to the driving power mode (P_mode) derived by decoding the vendor specific command (VS_CMD) are shown. The SSD 120 will operate in various operation modes according to the drive power mode (P_mode) included in the vendor specific instruction (VS_CMD).

Hereinafter, to describe the technical features of the present invention, it is assumed that the flash interface 240 of the present invention comprises eight channels, and the input / output ports of eight memory devices are shared by the respective channels. That is, it is assumed that the flash interface 240 controls the memory devices in an 8-channel bandwidth / 8-way interleaving (8CH / 8Way) manner. Here, Way means the number of memory devices that are the units of interleaving access in one channel. That is, if it is an 8-way interleaving access, it means that eight memory devices sharing one channel can be programmed or read out in an interleaving manner.

Referring to FIG. 4A, it is assumed that the driving power mode (P_mode) has a 3-bit size. When the decoding result of the vendor specific instruction (VS_CMD) transmitted from the host 110, that is, the driving power mode (P_mode) is '000', the SSD 120 activates 8 channels and 8 ways. In this case, the memory devices will be accessed in a full power mode. Accordingly, the instantaneous power consumption of the SSD 120 can reach a maximum value.

If the drive power mode (P_mode) is '001', the SSD 120 activates four channels and four ways to manage memory devices in a half power mode. If the drive power mode (P_mode) is '010', the SSD 120 activates two channels and two ways to manage memory devices in a quarter power mode. If the drive power mode (P_mode) is '011', the SSD 120 activates one channel and one way to manage memory devices in a minimum power mode.

The driving power mode (P_mode) bits '100', '101', '110', and '111' may be used as reserved bits to provide additional features. However, it goes without saying that these bits may also be configured to indicate additional drive power modes. Here, although it has been described as having four driving power modes (P_mode), the driving power mode can be further subdivided into various stages or more simply set.

FIG. 4B is a table showing an embodiment of a drive power mode (P_mode) that is more subdivided than the drive power mode (P_mode) of FIG. 4A. 4B shows an embodiment further including selection information of the driving clock (CLK) frequency of the SSD 120 in the driving power mode (P_mode). Referring to FIG. 4B, the frequencies f _b , f _c , and f _i of the driving clock CLK provided in the SSD 120 may be varied according to the value of the driving power mode P_mode. Here, the driving clock CLK may be an operation clock signal of the buffer memory 122 included in the SSD 120. [ Alternatively, the drive clock (CLK) may be an operation clock of the central processing unit (210) inside the SSD controller (121). Or the operation clock CLK may be the operation clock of the flash interface 240. [ For example, the drive clock CLK may be provided to the flash interface 240 and provided as a write enable signal / WE or a read enable signal / OE provided to the memory device.

If, it is the case in the three-bit drive power mode (P_mode) the MSB value of "0" is provided with the driving clocks (CLK) corresponding to the default value of the frequency (f _b, f _c, f _i). A channel / way to be simultaneously activated is set according to the value of the remaining 2-bits excluding the MSB among the 3-bit driving power mode (P_mode). That is, when the value of the drive power mode (P_mode) is "000", the frequency terms (f _b, f _c, f _i) 8 channel / 8-way from: a (PM0 Full power mode) approach is to access the memory device. If the value of the drive power mode (P_mode) of '001' is that the memory device is accessed by four-channel / 4-way (PM1) manner in the frequency terms _{(f b, f c, f} i). If the value of the drive power mode (P_mode) is "010", the frequency is that the memory device access condition _{(f b, f c, f} i) 2 -channel / two-way (PM2) in the method. If the value of the drive power mode (P_mode) of '011' is that the memory device is accessed by one channel / one-way (PM2) manner in the frequency terms _{(f b, f c, f} i).

On the other hand, when the MSB value is '1' in the 3-bit driving power mode (P_mode), the driving clock CLK is provided in the frequency condition (f _b / 2, f _c / 2, f _i / 2). If the value of the drive power mode (P_mode) is "100", the frequency terms _{(f b / 2, f c} / 2, f i / 2) by 8 channel / 8-way (PM0 ') scheme in the memory device are accessed . If the value of the drive power mode (P_mode) is "101", the frequency terms _{(f b / 2, f c} / 2, f i / 2) with 4-channel / 4-way (PM1 ') scheme in the memory device are accessed . If the value of the drive power mode (P_mode) is "110", the frequency terms _{(f b / 2, f c} / 2, f i / 2) in a two-channel / two-way (PM2 ') scheme in the memory device are accessed . When the value of the driving power mode (P_mode) is '111', the SSD 120 is driven in the minimum power mode. That is, the terms frequency _{(f b / 2, f c} / 2, f i / 2) 1 channel / one-way (PM3 ': Minimum power mode) in such a way that the memory device is accessed.

In the above, the driving power mode (P_mode) is classified into a full power mode, a half power mode, a quarter power mode, and a minimum power mode. However, the present invention is not limited to these definitions or terms. Further, although the channel / way setting is exemplified as having 8 channels / 8 ways, 4 channels / 4 ways, 2 channels / 2 ways and 1 channel / 1 way, various changes of channels / ways will be possible.

Figures 5A, 5B, and 5C are timing diagrams illustrating interleaving access procedures of memory devices connected to one channel in accordance with the value of a driving power mode (P_mode) provided through a vendor specific instruction (VS_CMD). FIG. 5A shows 8-way interleaving, FIG. 5B shows 4-way interleaving, and FIG. 5C shows a 2-way interleaving access method.

Referring to FIG. 5A, eight memory devices MEM_11, MEM_12,..., MEM_18 are connected to one channel (for example, CH.1) to share an input / output port. Assume that the SSD 120 is provided with a driving power mode (P_mode) from the host 110 so as to perform a writing operation according to an 8-way interleaving scheme. Write data may be provided according to a direct memory access (DMA) operation from the buffer memory 122 to the memory device MEM_11 in order to write data to one memory device MEM_11.

It takes time (tDMA) to transfer the write data (for example, 4K bytes or 16K bytes) to one memory device MEM_11 according to the DMA operation. And it takes time (tPROG) to program the write data provided to the memory device MEM_11 into the cell array of the memory device MEM_11. During the time that the provided write data is all programmed into the cell array (tPROG), the level of the ready / busy pin RnB of the memory device MEM_11 remains at logic 'L'. After the provided write data is all programmed into the cell array, the ready / busy pin RnB is switched to logic 'H'.

Interleaving means initiating a DMA operation 362 on another memory device MEM_12 as soon as the DMA operation 361 on one memory device MEM_11 is completed. That is, the time tPROG for programming the data provided by one memory device into the memory cell means that it can be hidden through the access of the interleaving method. 8-way interleaving refers to applying interleaved access to eight memory devices sharing channel (CH.1). And is an operation mode of the SSD 120 that continuously performs the DMA operation for the other memory device as soon as the DMA operation for one memory device is completed. It is possible to provide maximum access to memory devices sharing channel CH.1 through sequential DMA operations (361? 362? 363? 364? 365? 366? 367? 368).

However, when providing the maximum access to the eight memory devices MEM_11 to MEM_18, the program times tPROG of the respective memory devices can be overlapped. A relatively high power is consumed in the program operation. Therefore, although the maximum performance can be shown at the time tPmax shown by the hatched portion, the instantaneous power consumption by the memory devices MEM_11 to MEM_18 is also the maximum. When all channels are activated and simultaneously the programming time tPROG of the memory devices included in each of the channels is overlapped, the instantaneous power consumption of the SSD 120 will exhibit the maximum value. Therefore, when the residual power amount of the power source is insufficient, it is possible to cause a power failure of the information processing system 100.

5B is a timing diagram showing an embodiment in which 4-way interleaving is applied in a write operation. Referring to FIG. 5B, four memory devices MEM_11 to MEM_14 sharing the channel CH.1 are divided into one interleaving unit. And the remaining four memory devices MEM_15 to MEM_18 are divided into another interleaving unit. Under the control of the flash interface 240, each of the four-way interleaving will start the next interleaving operation when either one ends. Therefore, in case of 4-way interleaving, instantaneous maximum power consumption is relatively reduced as compared with 8-way interleaving.

5C is a timing diagram showing an embodiment in which 2-way interleaving is applied in a write operation. Referring to FIG. 5C, two memory devices MEM_11 to MEM_12 sharing a channel CH.1 are divided into one interleaving unit. The two memory devices MEM_13 to MEM_14 are divided into another interleaving unit. The two memory devices MEM_15 to MEM_16 are separated into another interleaving unit. The two memory devices MEM_17 to MEM_18 are divided into the last one interleaving unit. Each of the interleaving units is controlled by the flash interface 240 so that the data transmission and the programming of any one interleaving unit are started.

Although not shown in the above, a vendor specific instruction (VS_CMD) may be provided to not use the interleaving scheme in the selected channel. That is, the DAM operation time (tDAM) and the program time (tPROG) of each of the memory devices sharing the selected channel can be set so as not to overlap each other. In this case, the instantaneous power consumption at the time of the write operation will be the minimum, but the time required for the write operation will be the maximum.

6A and 6B are timing diagrams illustrating other embodiments of the present invention. FIG. 6A shows an embodiment in which the clock frequency of a channel is variable according to a vendor specific instruction (VS_CMD). FIG. 6B shows an embodiment for providing skew to each of the channels in accordance with a vendor specific instruction (VS_CMD).

Referring to FIG. 6A, the data transfer clock of the channel is provided to the channel by the flash interface 240. That is, the write enable signal / WE or the output enable signal / OE of the memory devices connected to each channel is generated by the clock signal provided to the flash interface 240. Thus, the frequency of the clock provided to the flash interface 240 determines the access rate of the memory devices. In particular, the frequency of the clock provided to the flash interface 240 determines the input rate of write data loaded into each memory device during DMA operations.

In the case of the clock frequency f _i corresponding to the default value, the input time of the write data by the DMA operation corresponds to the time period (t0-t1) in the DMA 391. On the other hand, when the clock frequency (f _i / 2) is provided, the input time of the write data by the DMA operation increases by about two times from the DMA 394 to the time period (t0-t2). In general, the power dissipation is known to be proportional to the square of the frequency of the clock. Therefore, it is possible to reduce the power consumption by varying the frequency of the driving clock.

Only the frequency of the clock signal provided to the flash interface 240 in FIG. 6A has been described. However, the present invention is not limited to the clock signal provided to the flash interface 240. Although briefly described above, the frequency of the driving clock of the buffer memory 122 may be varied. Or the frequency of the driving clock of the SSD controller 121 (for example, the CPU clock) may be varied to achieve the object of the present invention.

6B is a timing diagram showing that each channel can be set to have a skew by a vendor specific instruction (VS_CMD). That is, the flash interface 240 may be set to change the timing at which the DMA operation is started for each of the activated channels. That is, there is a constant time interval (Channel skew) between the time t0 at which the DMA operation 397 starts on the channel CH.1 and the time t1 when the DMA operation 398 starts on the channel CH.2 exist. The channel skew between these activated channels is also present between the channel (CH.2) and the channel (CH.3). By providing such a channel skew, it is possible to reduce the overlap of the DMA operation time (tDAM) and the program time tPROG of the memory devices without reducing the channel bandwidth. Therefore, the case where the instantaneous power consumption is rapidly increased can be blocked.

FIG. 7 is a flowchart illustrating an operation procedure of the information processing system 100 according to the embodiment of the present invention. 7, the information processing system 100 of the present invention issues a vendor specific instruction (VS_CMD) for adjusting the power mode of the SSD 120 with reference to a setting value of the BIOS 111 (see FIG. 1) . In response to the vendor specific command (VS_CMD), the SSD 120 performs a setup operation to operate in the decoded drive power mode (P_mode). More detailed description is as follows.

In a situation such as booting or resetting, if the booting by the OS is performed at the booting step by the BIOS 111, the information processing system 100 is provided with the BIOS setting information. In particular, the host 110 receives the SSD power mode information of the BIOS 111 described in the embodiment of the present invention (S110).

The host 110 transmits a vendor specific command (VS_CMD) to the SSD 120 in order to change the selected power mode condition to the power mode information provided from the BIOS 111 (S120). The SSD 120 receiving the vendor specific instruction VS_CMD decodes the vendor specific instruction VS_CMD to generate a driving power mode P_mode S130.

Then, according to the driving power mode (P_mode), the SSD controller 121 (see FIG. 1) will adjust all the operating parameters in the SSD 120 (S140). If the driving power mode P_modes shown in FIG. 4A are applied, if the driving power mode P_mode '000' is provided, the SSD 120 must be set in the full power mode. The SSD controller 121 sets a channel bandwidth / interleaving mode so that the memory devices are accessed in an 8-channel / 8-way manner to provide a high performance without considering consumption power (S150).

If the driving power mode (P_mode) '001' is provided, the SSD 120 should be set in the half power mode. The SSD controller 121 sets the channel bandwidth / interleaving mode so that the memory devices are accessed by the 4-channel bandwidth / 4-way interleaving scheme corresponding to the half power mode (S160).

If the drive power mode (P_mode) '010' is provided, the SSD 120 should be set in a quarter power mode. The SSD controller 121 sets the channel bandwidth / interleaving mode so that the memory devices are accessed in a two-channel bandwidth / two-way interleaving mode corresponding to a quarter power mode (S170).

If the driving power mode (P_mode) '011' is provided, the SSD 120 should be set to the minimum power mode. The SSD controller 121 will set the channel bandwidth / interleaving mode so that the memory devices are accessed in a one-channel bandwidth / non-interleaving manner corresponding to a minimum power mode (S180).

Although herein not shown, the internal clock signal of the SSD (120) in accordance with the drive power mode (P_mode) (the central processing unit, a clock signal of the buffer memory, and a flash interface) of each of the frequency (f _b, f _c, f _i may be further included in the setting operation steps S150, S160, S170, and S180. In addition, the flash interface 240 may be configured to provide a channel skew for each of the channels activated for the low power mode.

FIG. 8 is a block diagram illustrating an information processing system 400 according to another embodiment of the present invention. Referring to FIG. 8, the information processing system 400 adjusts the driving power mode of the SSD 420 itself without intervention from the host 410. That is, an information processing system 400 is disclosed in which SSD 420 itself generates and sets a drive power mode without instructions from host 410, such as a vendor specific instruction (VS_CMD).

The host 410 periodically checks the residual power amount of the power source (e.g., battery) and updates it in the storage area of the SSD 420. [ The data indicating the residual power amount in this way will be referred to as power data. The power data 424 is stored by the host 410 in the memory device 423, which is the storage medium of the SSD 420, and is periodically updated.

The SSD controller 421 receives the positional information of the power data 424 described above from the host 410 or detects the power data 424 stored in the preset memory area. In accordance with the detected result, the SSD controller 421 generates a driving power mode (P_mode). The SSD controller 421 adjusts or resets the operating parameters of the SSD 420 according to the generated driving power mode (P_mode). That is, the SSD 120 is set to achieve performance corresponding to the drive power mode (P_mode) as shown in FIG. 4A or FIG. 4B described above. Through the generation of the active driving power mode of the SSD 420, it is possible to stably drive the SSD 420 against the residual power amount of the information processing system 400 without the intervention of the host 410.

FIG. 9 is a flowchart showing operational procedures of the information processing system 400 of FIG. 9, the SSD 120 generates a driving power mode (P_mode) without an instruction (e.g., VS_CMD) of the host 410 and outputs the driving power mode (P_mode) as operating parameters corresponding to the generated driving power mode The SSD 420 is set.

The SSD controller 421 periodically detects the power data 424 stored in a specific area of the memory. The SSD controller 424 analyzes the power data 424 to calculate the residual power amount of the power supply. The SSD controller 421 generates a driving power mode (P_mode) according to the value of the residual power amount (S210).

The SSD controller 421 will adjust all of the operating parameters in the SSD 120 to one of the corresponding modes according to the generated driving power mode (P_mode) (S220). Referring to the driving power mode (P_modes) shown in FIG. 4A, when the driving power mode (P_mode) '000' is provided, the SSD 120 should be set in a full power mode. The SSD controller 121 sets a channel bandwidth / interleaving mode so that the memory devices are accessed in an 8-channel / 8-way manner to provide a high performance without considering consumption power (S230).

If the driving power mode (P_mode) '001' is provided, the SSD 120 should be set in the half power mode. The SSD controller 121 sets the channel bandwidth / interleaving mode so that the memory devices are accessed by the 4-channel bandwidth / 4-way interleaving scheme corresponding to the half power mode (S240).

If the drive power mode (P_mode) '010' is provided, the SSD 120 should be set in a quarter power mode. The SSD controller 121 sets the channel bandwidth / interleaving mode so that the memory devices are accessed by the 2-channel bandwidth / 2-way interleaving scheme corresponding to the quarter power mode (S250).

If the driving power mode (P_mode) '011' is provided, the SSD 120 should be set to the minimum power mode. The SSD controller 121 will set the channel bandwidth / interleaving mode to access memory devices in a one-channel bandwidth / non-interleaving manner corresponding to a minimum power mode (S260).

Although herein not shown, the internal clock signal of the SSD (120) in accordance with the drive power mode (P_mode) (the central processing unit, buffer memory, and the clock signal of the Flash interface) of each of the frequency (f _b, f _c , f _i ) may be further included in the setting operation steps (S150, S160, S170, S180). In addition, the flash interface 240 may be configured to provide a channel skew for each of the channels activated for the low power mode.

According to the embodiment described with reference to FIGS. 8 and 9, the driving power mode P_mode can be generated by the self-determination of the SSD 420 without the intervention of the host 410. FIG. It is also possible to drive the SSD 120 considering the residual power amount of the power source. In the information processing system 400 such as a mobile device, it is possible to extend the operating time and provide stability of the system by driving the SSD 420 considering such power.

FIG. 10 is an exemplary illustration of a computing system 500 with a solid state drive (SSD) in accordance with the present invention. A computing system 500 according to the present invention includes a BIOS 520 electrically connected to a system bus 570, a microprocessor 530, a user interface 540, a battery 550, a RAM 560 and an SSD 510, . The SSD 510 includes an SSD controller 511, and a memory device 512. N-bit data to be processed / processed by the microprocessor 530 (where N is an integer greater than or equal to 1) will be stored in the memory device 412 via the SSD controller 511. [ Although it is not shown in the drawing, the application system of the present invention can be provided with an application chipset, a camera image processor (CIS), a modem, a mobile DRAM, To those who have learned.

The driving power mode of the SSD 510 may be selected according to the setting data of the BIOS 520 input through the user interface 540 of the computing system 500 of the present invention. That is, a vendor specific instruction (VS_CMD) corresponding to the configuration data of the BIOS 520 is issued by the microprocessor 530, and in response, the SSD 510 will set or adjust internal operating parameters.

According to another embodiment, the SSD 510 may itself sense power data and generate a drive power mode without external control, such as a vendor specific instruction (VS_CMD). And the internal operating parameters of the SSD 510 may be adjusted or set according to the generated drive power mode. In this case, the performance or the instantaneous power consumption of the SSD 510 can be controlled in consideration of the residual power amount of the battery 550.

The SSD 510 of the present invention can be used as a storage medium such as an MMC card, an SD card (Secure Digital Card), a micro SD card, a memory stick, an ID card, a PCMCIA card, a chip card, A smart card, a CF card (Compact Flash Card), and the like.

The memory device 512 may be configured as a flash memory device capable of retaining stored data even when power is interrupted. With the increasing use of mobile devices such as cellular phones, PDA digital cameras, portable game consoles, and MP3Ps, flash memory devices can be widely used as code storage as well as data storage. The SSD 510, including the memory device 512 and the SSD controller 511, may also be used in home applications such as HDTV, DVD, router, and GPS.

The SSD 510 of the present invention is applicable to an embedded system. An embedded system is a built-in computing system that is part of another device and performs only specific computing tasks that are imposed on the device that contains it, unlike a normal computer. To do this, an embedded system has a central processing unit, requires an operating system, and runs applications on the operating system to perform specific tasks. Generally, embedded systems are embedded to control military equipment, industrial equipment, communication equipment, set-top boxes, home appliances such as DTVs and digital cameras.

The memory device and / or SSD controller according to the present invention may be implemented using various types of packages. For example, the memory device and / or the SSD controller according to the present invention may be implemented as a package on package (PoP), ball grid arrays (BGAs), chip scale packages (CSPs), plastic leaded chip carriers Die in Wafer Form, Chip On Board (COB), Ceramic Dual In-Line Package (CERDIP), Plastic Metric Quad Flat Pack (MQFP), Thin Quad Flatpack (TQFP), Small Outline (SOIC), Shrink Small Outline Package (SSOP), Thin Small Outline (TSOP), Thin Quad Flatpack (TQFP), System In Package (SIP), Multi Chip Package (MCP), Wafer-level Fabricated Package -Level Processed Stack Package (WSP), and the like.

As described above, an optimal embodiment has been disclosed in the drawings and specification. Although specific terms have been employed herein, they are used for purposes of illustration only and are not intended to limit the scope of the invention as defined in the claims or the claims. Therefore, those skilled in the art will appreciate that various modifications and equivalent embodiments are possible without departing from the scope of the present invention. Accordingly, the true scope of the present invention should be determined by the technical idea of the appended claims.

1 is a block diagram showing an information processing system according to an embodiment of the present invention;

FIG. 2 is a block diagram illustrating the SSD controller of FIG. 1;

3 is a block diagram briefly showing the connection relationship of the flash interface and the memory devices;

Figures 4A and 4B are tables showing various embodiments of the driving power mode (P_mode);

Figures 5A, 5B and 5C are timing diagrams showing different interleaving access modes, respectively;

6A is a timing diagram showing an embodiment for varying the driving clock frequency of the flash interface;

FIG. 6B is a timing chart illustrating a channel skew; FIG.

7 is a flowchart showing the control operation of the information processing system of the present invention;

8 is a block diagram illustrating an information processing system according to another embodiment of the present invention;

FIG. 9 is a flowchart showing the operation of the SSD of FIG. 8; FIG. And

10 is a block diagram illustrating a computing system in accordance with the present invention.

Description of the Related Art [0002]

110, 410: Host 111: BIOS

120, 420: SSD 121, 421: SSD controller

122, 422: buffer memory

123, 124, 125, 423: memory devices

210: central processing unit 220: host interface

230: Buffer manager 240: Flash interface

424: Power data 510: SSD

511: SSD controller 512: memory device

520: BIOS 530: CPU

540: User interface 550: Battery

560: RAM 570: System bus

Claims (10)

A plurality of memory devices; And (P_mode) by decoding an external command (VS_CMD), exchanging data with the plurality of memory devices through a plurality of channels, and controlling a bandwidth of the plurality of channels according to the driving power mode Or a memory controller that adjusts the number of interleaved accessed memory devices, The external command (VS_CMD) is a vendor specific command provided from the outside by referring to a BIOS setting value, Wherein the access start time of each of the activated channels is adjusted differently according to the driving power mode (P_mode). The method according to claim 1, Wherein the memory controller activates some or all of the plurality of channels in accordance with the driving power mode (P_mode). The method according to claim 1, Wherein the memory controller adjusts the number of memory devices accessed interleaved in the activated channel according to the driving power mode (P_mode). delete The method according to claim 1, Further comprising a buffer memory for buffering data under the control of the memory controller, wherein the memory controller adjusts a frequency of a clock for driving the buffer memory according to the driving power mode (P_mode). The method according to claim 1, Wherein the memory controller further comprises a central processing unit for decoding the external command (VS_CMD), and the clock frequency of the central processing unit is adjusted according to the driving power mode (P_mode). The method according to claim 1, Wherein the memory controller adjusts the frequency of a clock for exchanging data in the activated channel according to the driving power mode (P_mode). The method according to claim 1, Wherein the plurality of memory devices are configured as a flash memory device, and the plurality of memory devices and the memory controller are provided as a solid state drive. A plurality of memory devices; And Exchanging data with the plurality of memory devices via a plurality of channels, the channel bandwidth for accessing the plurality of memory devices with reference to power supply data stored in the plurality of memory devices, or the number of interleaved memory devices And a memory controller for controlling the memory controller, Wherein the access start time of each of the plurality of channels is adjusted differently according to the power supply data. A host that issues a command (VS_CMD) by referring to BIOS (BIOS) setting information stored in the ROM; And And a solid state drive operating at a performance corresponding to a drive power mode (P_mode) in response to the command (VS_CMD).

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