KR101518172B1 - Method and apparatus for measureing on chip jitter tolerance for cdr circuits - Google Patents

Abstract

A method and an apparatus for measuring on chip jitter tolerance for evaluating the performance of CDR circuits are suggested. The method comprises the stages of: applying a jitter to a cluck in a CDR circuit; adjusting phase changing speed by preset jitter frequency by adjusting the applied setting value of the jitter and adjusting the size of a phase which changes to the maximum by preset jitter size; and resampling and recovering input data in a phase detector of the CDR circuit into a cluck which contains jitter components.

Description

METHOD AND APPARATUS FOR MEASUREING ON CHIP JITTER TOLERANCE FOR CDR CIRCUITS BACKGROUND OF THE INVENTION [0001]

The present invention relates to an on-chip jitter tolerance measurement method and apparatus for CDR performance evaluation. More particularly, to a method and apparatus for on-chip jitter tolerance measurement for CDR performance evaluation that measures jitter tolerance in a CDR circuit in a chip.

In a communication system, data transmission is performed at a high speed, and only data except clocks are sent to a receiving end because of hardware complexity, power consumption, and price. Therefore, it is necessary to extract the clock signal from the data received at a high speed, and research on a clock data recovery circuit (CDR) for recovering data using the extracted clock is actively conducted.

Such a clock data recovery circuit may include a high speed interface system for extracting accurate timing information from the data, such as Ethernet receivers, disk drive read and write channels, and digital mobile receivers. Is widely used.

In general, the Alexander Phase Detector (Alexander PD) is used for a general clock data restoration circuit widely used. In the case of the Alexander Phase Detector, the jitter characteristic is low, the power consumption is large, have.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and it is an object of the present invention to provide an on-chip jitter detector for CDR performance evaluation, which can measure jitter tolerance in a CDR circuit in a chip without external test equipment by resampling data with a clock including a jitter component. And to provide a method and apparatus for measuring the tolerance.

In one aspect, an on-chip jitter tolerance measurement method for evaluating CDR performance proposed in the present invention includes: applying jitter to a clock in a CDR circuit; Adjusting a set value of the applied jitter to adjust a speed at which the phase changes according to the set jitter frequency and adjusting a maximum changed phase size according to the set jitter size; And resampling and recovering the input data from the phase detector of the CDR circuit to a clock including a jitter component.

The jitter frequency range can be set up or down based on the CDR loop bandwidth with jitter tolerance characteristics.

Wherein the jitter modulation circuit is a jitter modulation circuit which is connected to the CDR circuit section in the chip to adjust a set value of a jitter frequency and a jitter size and includes a multi pulse generator and a modulation charge pump, The modulation charge pump can be switched and the triangular waveform can be outputted by the loop filter capacitor of the CDR circuit section.

In another aspect, an on-chip jitter tolerance measuring apparatus for CDR performance evaluation proposed in the present invention includes a CDR circuit unit including a phase detector, a charge pump, a loop filter, and a voltage-controlled oscillator; And a jitter modulation circuit section connected to the CDR circuit section in the chip to adjust a set value of a jitter frequency and a jitter size.

The jitter modulation circuit section includes a multi-pulse generator and a modulation charge pump. The square pulse generated by the multi-pulse generator switches the modulation charge pump and outputs a triangular waveform by the loop filter capacitor of the CDR circuit section .

According to the embodiments of the present invention, since the data is resampled to the clock including the jitter component, the jitter tolerance can be measured in the CDR circuit in the chip without the external test equipment. A method and apparatus for measuring a tolerance can be provided.

1 is a flowchart of an on-chip jitter tolerance measurement method for CDR performance evaluation according to an embodiment of the present invention.
2 is a circuit diagram illustrating an on-chip jitter tolerance measuring circuit for CDR performance measurement according to an embodiment of the present invention.
FIG. 3A illustrates a jitter modulator according to an exemplary embodiment of the present invention, and FIG. 3B illustrates a jitter frequency / amplitude modulation process according to an exemplary embodiment of the present invention. Referring to FIG.
4 shows a bit error detector according to an embodiment of the present invention.
5 is a diagram illustrating an example of a measured clock eye diagram according to an embodiment of the present invention.
6 is a diagram illustrating jitter tolerance and results measured using the proposed technique in a CDR circuit according to an embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

To ensure complete signal recovery in high-speed data transfer, the clock / data recovery circuit must allow input data that contains substantial jitter. Such jitter is caused by power noise, frequency mismatch, and device noise.

And, the jitter tolerance is defined as the input data jitter that is used as a standard in the CDR circuit and the tolerance of the bit error ratio (BER) is acceptable. To reduce cost, techniques for measuring jitter tolerance in the CDR circuitry within a chip are essential.

1 is a flowchart of an on-chip jitter tolerance measurement method for CDR performance evaluation according to an embodiment of the present invention.

Step 110 may apply a jitter to the clock in the CDR circuit. Here, the jitter may be a jitter modulation circuit connected to the CDR circuit in the chip to adjust the jitter frequency and the set value of the jitter size. The jitter is a jitter modulation circuit including a multi-pulse generator and a modulation charge pump. A square pulse generated by the multi-pulse generator switches the modulation charge pump and outputs a triangular waveform by the loop filter capacitor of the CDR circuit. have.

In step 120, the jitter modulation circuit adjusts the set value of the applied jitter, adjusts the rate at which the phase changes according to the set jitter frequency, and adjusts the phase size that changes the maximum according to the set jitter size. That is, the jitter modulation circuit can digitally adjust the jitter frequency and magnitude respectively.

At this time, the jitter frequency range can be set up or down based on the CDR loop bandwidth as a jitter tolerance characteristic. Typical jitter tolerance tests allow the CDR to track data modulated with external jitter within the target bit error ratio (BER). In the proposed method, the CDR ignores the internal modulation jitter because the data is not modulated by external jitter. This externally or internally, the jitter modulation has an equivalent mechanism and is interrelated.

In step 130, the phase detector of the CDR circuit can resamplify the input data by resampling the clock with the jitter component.

That is, when jitter is applied to the clock in the CDR circuit, a phase size at which the phase changes according to the set jitter frequency is changed and a phase size at which the maximum varies according to the set jitter size can be adjusted. Since the phase detector resamplifies the input data to the clock including the jitter component, the recovered data can also have the same jitter component as the clock.

2 is a circuit diagram illustrating an on-chip jitter tolerance measuring circuit for CDR performance measurement according to an embodiment of the present invention.

Referring to FIG. 2, a CDR circuit for measuring a jitter tolerance in a chip is composed of a general CDR circuit section 210 and a jitter modulation circuit section 220.

The CDR circuitry 210 may include a phase detector 211, a charge pump 212, a loop filter 213, and a voltage controlled oscillator 214. Here, the voltage-controlled oscillator 214 is a clock source of the CDR, and can sample and recover data using a clock. This sampling is performed through the phase detector 211, and the charge pump 212 can be driven using the up-down signal from the phase detector. Further, in order to perform jitter modulation in the chip, the output can be connected to the loop filter 213 to the triangular wave modulator.

More specifically, the phase detector 211 reduces the power consumption by reducing the up / down signal, and uses a bang-bang phase detector (BBPD) having improved jitter characteristics. .

A charge pump (CP) 212 converts the Up / Down signal having time information, which is made by the output of the phase frequency detector, into potential information in the capacitor in the loop filter. Here, when the up signal enters the input and the upper current path is formed, charge is supplied to the load capacitor to increase the control voltage. Conversely, when the Down signal is applied, the path is opened to the lower current source, and the charge is discharged to the capacitor, so that the control voltage is lowered.

A loop filter 213 converts the current output through the charge pump into a voltage to be used as a control signal of the voltage-controlled oscillator, and low-pass-filters the noise included in the input.

In addition, the loop filter can use an active filter or a passive filter, but it is preferable to use a passive filter. The additional use of the active elements of the active filter increases phase noise, complexity and cost. However, if the control voltage required by the voltage controlled oscillator is greater than the voltage generated by the charge pump, an active filter should be used. When a higher control voltage is used in a voltage controlled oscillator, the tuning range of the voltage controlled oscillator is widened or phase noise is reduced.

In addition, the voltage controlled oscillator 214 can improve the efficiency by using a ring voltage controlled oscillator (ring-VCO). And receives a voltage input signal as a frequency control signal and outputs a constant frequency corresponding to the control signal.

The jitter modulation circuit unit 220 is connected to the CDR circuit unit in the chip, and can digitally adjust the set values of the jitter frequency and the magnitude. The jitter modulation circuit unit 220 includes a multi pulse generator 221 and a modulation charge pump 222. The square pulse generated by the multi pulse generator 221 switches the modulation charge pump 222, The triangular waveform can be outputted by the loop filter capacitor of FIG.

At this time, the frequency range can be set up or down based on the CDR loop bandwidth as a jitter tolerance characteristic. Typical jitter tolerance tests allow the CDR to track data modulated with external jitter within the target bit error ratio (BER). In the proposed method, the CDR can ignore the internal modulation jitter because the data is not modulated by external jitter. This externally or internally, the jitter modulation has an equivalent mechanism and is interrelated.

The voltage-controlled oscillator can be the clock source of the CDR. These clocks can be used to sample and recover the data. Such sampling is accomplished through a phase detector and the charge pump can be driven using the up-down signal from the detector.

Further, the jitter measuring circuit unit 230 is further included to measure the jitter tolerance. Here, the jitter measuring circuit unit 230 may be implemented by a PRBS generator and a PRBS detector.

Then, in order to perform jitter modulation in the chip, the output can be connected to the loop filter with a triangular wave modulator. Here, the modulator can place a triangular waveform over the voltage-controlled oscillator control voltage. The phase can be periodically changed with respect to the clock output from the voltage-controlled oscillator according to the control voltage change.

That is, when jitter is applied to the clock in the CDR circuit, a phase size at which the phase changes according to the set jitter frequency is changed and a phase size at which the maximum varies according to the set jitter size can be adjusted. Since the phase detector resamplifies the input data to the clock including the jitter component, the recovered data can also have the same jitter component as the clock.

FIG. 3A illustrates a jitter modulator according to an exemplary embodiment of the present invention, and FIG. 3B illustrates a jitter frequency / amplitude modulation process according to an exemplary embodiment of the present invention. Referring to FIG.

Referring to FIG. 3 (a), the jitter modulator may be composed of a multi-pulse generator and a modulation charge pump. The square pulse generated by the multi-pulse generator can switch the modulation charge pump and output a triangular waveform by the CDR loop filter capacitor.

Referring to FIG. 3 (b), it can be shown how the frequency and magnitude are determined and generated in the modulated jitter. Here, a periodic change may occur by raising the triangular waveform to the control voltage. That is, a periodic change in the control voltage appears as a phase change in the clock and can output a jitter component.

If a square pulse input is applied to the modulation charge pump, the pulse period may appear as a modulated jitter frequency. Therefore, the modulation charge pump can perform the switching operation by the square pulse.

Depending on the set bias current in the charge pump, the amount of charge accumulated in the loop filter capacitor during one cycle can be varied to adjust the peak value in the triangular waveform. This value is proportional to the amount of movement of one phase to the maximum so that jitter can be sized. In addition, the delay current to the multi-pulse generator and the control current to the modulation charge pump are each digitally adjustable by a switch connected in parallel.

4 shows a bit error detector according to an embodiment of the present invention.

PRBS 패턴 데이터를 비교하여 비트 에러를 생성해 낼 수 있다. 이에 따라, 이 회로는 싱크(Sync) 신호에 따라 두 가지 동작으로 나누어질 수 있다. Referring to FIG. 4, data reconstructed in the CDR circuit and data

The bit error can be generated by comparing the PRBS pattern data. Accordingly, this circuit can be divided into two operations according to the sync signal.

Here, when Sync = 1, the restored data and the reference data are compared with each other and the sync can be aligned. It is possible to detect the pattern '1111111' in the restored data and reset the PRBS signal generator every moment.

In the case where Sync = 0 is set in synchronization with the restored data and the reference data, a bit error can be outputted by comparing two data patterns.

5 is a diagram illustrating an example of a measured clock eye diagram according to an embodiment of the present invention.

5A shows the measured clock eye diagram @ jitter frequency = 5 MHz, jitter size = 0, 0.34 UI, 068 UI, FIG. 5B shows measured data eye diagram @ jitter frequency = 5 MHz, = 0, 0.34 UI, and 068 UI.

PRBS 패턴을 입력으로 테스트를 하고, CDR에 루프 대역폭은 10MHz이며, H-SPICE를 이용하여 시뮬레이션을 진행할 수 있다. 기본적으로 CDR에 클럭과 데이터에 피크 투 피크 지터는 각각 18.93ps, 26.92ps이다.The proposed circuit

The PRBS pattern is tested as input, and the loop bandwidth of the CDR is 10 MHz, and the simulation can be performed using H-SPICE. Basically, the peak-to-peak jitter on the clock and data in the CDR is 18.93 ps and 26.92 ps, respectively.

As shown in FIG. 5, the eye diagram change can be represented by the (a) clock and the (b) data according to the jitter amplitude modulation (0, 0.34 UI, 0.68 UI) at the jitter frequency of 5 MHz. Therefore, it can be seen that as the size of the modulated jitter increases, the eye closes.

6 is a diagram illustrating jitter tolerance and results measured using the proposed technique in a CDR circuit according to an embodiment of the present invention.

Referring to FIG. 6, jitter tolerance and the results measured by the proposed technique are shown in the CDR circuit. Jitter tolerance of CDRs according to jitter frequency and the results measured by the proposed technique are shown. Here, the proposed CDR has a loop bandwidth of 10 MHz and can be designed to have a jitter frequency setting range of 100 KHz to 20 MHz as its center. Theoretically, the jitter tolerance decreases to -20dB at a jitter frequency lower than the loop bandwidth and constantly approaches a constant value when the frequency is large. Thus, it can be seen that the jitter tolerance values measured by the proposed technique are similar to the theoretical values near the loop bandwidth.

Therefore, the present invention can measure the jitter tolerance in the CDR circuit in the chip without the external test equipment. The analog method uses a jittering method, but is easy to implement, freely programmable according to design specifications, and digitally adjustable. Accordingly, this technique can be used for various analog / digital CDR technologies.

The apparatus described above may be implemented as a hardware component, a software component, and / or a combination of hardware components and software components. For example, the apparatus and components described in the embodiments may be implemented within a computer system, such as, for example, a processor, controller, arithmetic logic unit (ALU), digital signal processor, microcomputer, field programmable array (FPA) A programmable logic unit (PLU), a microprocessor, or any other device capable of executing and responding to instructions. The processing device may execute an operating system (OS) and one or more software applications running on the operating system. The processing device may also access, store, manipulate, process, and generate data in response to execution of the software. For ease of understanding, the processing apparatus may be described as being used singly, but those skilled in the art will recognize that the processing apparatus may have a plurality of processing elements and / As shown in FIG. For example, the processing apparatus may comprise a plurality of processors or one processor and one controller. Other processing configurations are also possible, such as a parallel processor.

The software may include a computer program, code, instructions, or a combination of one or more of the foregoing, and may be configured to configure the processing device to operate as desired or to process it collectively or collectively Device can be commanded. The software and / or data may be in the form of any type of machine, component, physical device, virtual equipment, computer storage media, or device , Or may be permanently or temporarily embodied in a transmitted signal wave. The software may be distributed over a networked computer system and stored or executed in a distributed manner. The software and data may be stored on one or more computer readable recording media.

The method according to an embodiment may be implemented in the form of a program command that can be executed through various computer means and recorded in a computer-readable medium. The computer-readable medium may include program instructions, data files, data structures, and the like, alone or in combination. The program instructions to be recorded on the medium may be those specially designed and configured for the embodiments or may be available to those skilled in the art of computer software. Examples of computer-readable media include magnetic media such as hard disks, floppy disks and magnetic tape; optical media such as CD-ROMs and DVDs; magnetic media such as floppy disks; Magneto-optical media, and hardware devices specifically configured to store and execute program instructions such as ROM, RAM, flash memory, and the like. Examples of program instructions include machine language code such as those produced by a compiler, as well as high-level language code that can be executed by a computer using an interpreter or the like. The hardware devices described above may be configured to operate as one or more software modules to perform the operations of the embodiments, and vice versa.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. For example, it is to be understood that the techniques described may be performed in a different order than the described methods, and / or that components of the described systems, structures, devices, circuits, Lt; / RTI > or equivalents, even if it is replaced or replaced.

Therefore, other implementations, other embodiments, and equivalents to the claims are also within the scope of the following claims.

210: CDR circuit unit 211: phase detector
212: charge pump 213: loop filter
214: voltage-controlled oscillator 220: jitter modulation circuit
221: Multipulse generator 222: Modulation charge pump
230: jitter measuring circuit part

Claims (5)

In an on-chip jitter tolerance measurement method for CDR performance evaluation,
Applying jitter to a clock in a CDR circuit;
Adjusting a set value of the applied jitter to adjust a speed at which the phase changes according to the set jitter frequency and adjusting a maximum changed phase size according to the set jitter size; And
Wherein the phase detector of the CDR circuit resamples and restores the input data to a clock including a jitter component,
Wherein the jitter is a jitter modulation circuit which is connected to the CDR circuit portion in the chip to adjust a jitter frequency and a set value of a jitter size and includes a multi pulse generator and a modulation charge pump,
The square pulse generated by the multi-pulse generator switches the modulation charge pump and outputs a triangular waveform by the loop filter capacitor of the CDR circuit portion
Chip jitter tolerance measurement method for CDR performance evaluation. The method according to claim 1,
The jitter frequency range is a jitter tolerance characteristic that is set up or down based on the CDR loop bandwidth
Chip jitter tolerance measurement method for CDR performance evaluation. delete delete An on-chip jitter tolerance measuring apparatus for CDR performance evaluation,
A CDR circuit portion including a phase detector, a charge pump, a loop filter, and a voltage controlled oscillator; And
And a jitter modulation circuit unit connected to the CDR circuit unit in the chip to adjust a jitter frequency and a set value of the jitter size,
The jitter modulation circuit section
A multi-pulse generator and a modulation charge pump,
The square pulse generated by the multi-pulse generator switches the modulation charge pump and outputs a triangular waveform by the loop filter capacitor of the CDR circuit portion
Chip jitter tolerance measurement device for CDR performance evaluation.

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