JP2003008431A - Clock data recovery ic and its jitter transmission band adjustment method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a clock data recovery (CDR) IC that can adjust a jitter transmission band at a DC test for an IC without the need for employing an expensive measurement device such as a pulse pattern generator and a jitter analyzer, and to provide its jitter transmission band adjustment method. SOLUTION: A sample-hold type phase comparator is employed for the CDR IC and the phase comparator receives input VCO output waveform signals whose phases are shifted by 90-degrees with each other so as to calculate the jitter transmission band only through the measurements of the frequency and a DC voltage thereby adjusting the jitter transmission band at the DC test for the IC.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock / data recovery IC (hereinafter referred to as CDR IC) and a jitter transfer band adjusting method thereof.

[0002]

2. Description of the Related Art FIG. 13 is a block diagram showing a conventional structure for adjusting a jitter transfer band, and FIG. 14 is a flowchart showing an example of a procedure from assembly to shipment of a conventional optical module. As shown in FIG. 13, the optical receiver module 65 is
PD or APD66 that converts an optical signal into an electrical signal
And a transimpedance amplifier 67 for performing current / voltage conversion, a voltage amplifier 68, and a CDR IC 27. Further, the CDRIC 27 has a phase comparator 4, a filter circuit 7, a PLL 13 including a VCO 12, a discriminator 14, a data output buffer 15, and a clock output buffer 16. The jitter band of the CDR IC 27 is adjusted by converting the output signal of the pulse pattern generator 76 into an optical signal by the standard optical transmission module 75, inputting it to the optical reception module 65 through the optical fiber 64, and jittering the clock output 65b of the optical reception module 65 with the jitter. Measure with the analyzer 77.

As shown in FIG. 14, a conventional optical module is manufactured by an optical module assembly process (CDR IC2).
7), adjustment process (optical module jitter transfer band adjustment process), and test process. That is, after the optical receiving module is assembled, the sensitivity of the APD is adjusted and the jitter transfer band is measured. If the jitter transfer band satisfies the standard, the receiving module is tested for operation and shipped. If the jitter transfer band does not meet the standard, the resistor R1 is replaced and the jitter transfer band is measured again. This was repeated until the jitter transfer band standard was satisfied.

For example, the catalog of Anritsu MP1777A (MP1777A-JA-1- (4.00), 20
November 22, 2000) p. 3 describes adjustment of the jitter transfer band using a pulse pattern generator and a jitter analyzer. Incidentally, in the conventional adjustment of the jitter transfer band, the CDR IC was operated at the actual speed.

[0005]

However, in the jitter transfer band adjustment of the conventional CDR IC, the expensive pulse pattern generator 76 and jitter analyzer 7 are used.
7 was needed. Also, since the CDR IC is assembled into the optical module and then the resistance is manually replaced,
It took about 10 minutes to adjust the jitter transfer band. That is, the pulse pattern generator and the jitter analyzer are expensive especially as the operating frequency becomes high, and the measurement time also takes several minutes, resulting in a high adjustment cost.

Further, in order to operate at the actual speed, it is necessary to input a signal having the same speed as that at the actual operation to the IC. Therefore, high-speed CDR I such as 2.5 Gbps or 10 Gbps
In C, 2.5 Gbps and 10 Gbps for normal probes
Since a high-speed signal such as ps cannot be passed, it is difficult to adjust the jitter transfer band by trimming the resistance in the IC during DC test of the IC. It was necessary to adjust the capacity and so on.

An object of the present invention is to solve the above problems.
C that allows adjustment of jitter transfer band during DC test of IC
DR IC and its jitter transfer band adjustment method (CDR
IC manufacturing method). Further, an object of the present invention is to provide a CDR IC capable of adjusting a jitter transfer band without using an expensive measuring device such as a pulse pattern generator or a jitter analyzer, and a jitter transfer band adjusting method thereof (a method for manufacturing a CDR IC). To provide.

[0008]

In order to achieve the above-mentioned object, the outline of a typical invention among the inventions disclosed in the present application will be briefly described as follows. In the clock / data recovery IC, the phase-locked loop of the clock / data recovery IC includes a voltage-controlled oscillator and a +45 phase shifter that advances the phase of one of the branched output signals of the voltage-controlled oscillator by 45 degrees. , A -45 phase shifter that delays the phase of the other branched output signal of the voltage controlled oscillator by 45 degrees, a selector that selects the data from the data input pad and the output of the -45 phase shifter, and the selector A phase comparator for comparing the phases of the selected output and the output of the phase shifter of +45 degrees; and a filter circuit having a lag lead characteristic for inputting the output of the phase comparator and outputting it to the voltage controlled oscillator. , The clock data recovery I
At the time of adjusting the jitter transfer band of C, the +45 is added to the phase comparator.
The output signal of the phase shifter and the output signal of the −45 phase shifter are input.

In the clock / data recovery IC, the phase-locked loop of the clock / data recovery IC advances the phase of the voltage-controlled oscillator and one of the branched output signals of the voltage-controlled oscillator by 90 degrees. Let +90
A phase shifter, a selector for selecting the other branched output signal of the voltage controlled oscillator and data from the data input pad, and a phase of the output selected by the selector and the output of the +90 degree phase shifter. A phase comparator for comparison, and a filter circuit having a lag lead characteristic for inputting the output of the phase comparator and outputting it to the voltage controlled oscillator;
When adjusting the jitter transfer band of the recovery IC, the output signal of the +90 phase shifter and the other branched output signal of the voltage controlled oscillator are input to the phase comparator.

Further, in the clock / data recovery IC, the phase-locked loop of the clock / data recovery IC delays the phase of the voltage-controlled oscillator and one of the branched output signals of the voltage-controlled oscillator by 90 degrees. Ru 90
A phase shifter, a selector for selecting data from the data input pad and the output of the −90 phase shifter, and a phase of the output selected by the selector and the other branched output signal of the voltage controlled oscillator. And a filter circuit having a lag lead characteristic for inputting the output of the phase comparator to the output of the voltage controlled oscillator and adjusting the jitter transfer band of the clock / data recovery IC. And the other branched output signal of the voltage controlled oscillator and the -90
The output signal of the phase shifter is input.

Clock data having a data input pad, a data output pad, a clock output pad, a phase comparator, a voltage controlled oscillator, and a phase shifter for changing the phase of the output waveform of the voltage controlled oscillator. Recovery IC
The method for adjusting a jitter transfer band according to claim 2, wherein the output is from a voltage controlled oscillator, and the phases are shifted from each other by about 90 degrees.
Two output waveforms are input to the phase comparator.

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION A CDR IC according to the present invention and a method for manufacturing the same, particularly a method for adjusting a jitter transfer band, will be described.
This will be described with reference to the drawings. First, CDR I according to the present embodiment
An example of an optical communication system using an optical module having C will be described with reference to FIG. In FIG. 11, the optical communication system includes a multiplexer 60 that time-multiplexes signals that have undergone processing such as switching, and an optical transmission module 6.
1, an optical fiber 64 that transmits the optical signal output from the optical transmission module 61, an optical receiving module 65 that receives the signal from the optical fiber 64, converts the optical signal into an electrical signal, and regenerates a clock; It has a demultiplexer 70 that separates the signals for ease of processing.

The optical transmission module 61 has a laser diode 63 and a driver IC 62 for driving the laser diode 63, receiving the data signal 61a and the clock signal 61b from the multiplexer. The optical receiving module 65 is a photodiode (hereinafter, P) for converting an optical signal into an electric signal.
D) or avalanche photodiode (hereinafter APD)
66, a transimpedance amplifier 67 for performing current / voltage conversion, a voltage amplifier 68, and a CDRIC 69.

Normally, only data signals are transmitted on the optical fiber. Since the data signal and the clock signal are required to perform the processing in the digital system, the optical receiver module in the CDR IC extracts the clock signal from the data signal and reshapes the waveform with the clock.

The signal 64a transmitted through the optical fiber has a jitter tj due to the waveform distortion of the driver IC 62, the waveform distortion at the time of electric / optical conversion in the laser diode 63, the waveform distortion due to the dispersion characteristic of the optical fiber 64, and the like. Jitter is added when an optical communication system as shown in FIG. 11 is connected in cascade, and correct signal transmission becomes impossible. Therefore, it is necessary for the CDR IC to suppress the jitter above a certain frequency ft as shown in FIG. The frequency ft and the amount of jitter suppression are determined by the standard, and the optical receiving module must comply with the standard.

Next, the CDR IC according to this embodiment will be described with reference to FIGS. 1, 2 and 3. That is, FIG. 1 is a circuit diagram showing a first embodiment of a CDR IC according to the present invention. In FIG. 1, the CDR IC 27 includes a phase shifter 1 of +45 degrees, a phase shifter 2 of −45 degrees, and a data input pad 2.
Selector 3 for selecting the output of 0 and -45 phase shifter 2, sample-and-hold type phase comparator 5 for comparing the phase of the output of selector 3 and the output of phase shifter 1 of +45 degrees, and the resistance in the circuit The gain can be varied by trimming the value, and the output from the phase comparator 4 including the variable gain section 6 capable of changing the output to high impedance by the signal from the test pad 21 and the signal from the test pad 22. A high-impedance amplifier circuit portion 8, a resistor 9 in the IC, a filter circuit 7 having a lag lead characteristic as shown in FIG. , A phase-locked loop (PLL) 1 composed of a VCO (voltage controlled oscillator) 12
3, a discriminator 14, a data output buffer 15, and a clock output buffer 16.

In this embodiment, the CDR IC 27 has two operating states which can be switched by the test pad 21 and the test pad 22. One is a state where the optical signal is mounted on the optical module and the clock signal is reproduced from the input data signal (hereinafter, normal operation), and the other is a jitter transfer band at the time of DC test of the IC before mounted on the optical module. This is a state for measuring and adjusting (hereinafter, when the jitter transfer band is adjusted).

At the time of normal operation, the VCO 12 is applied to the phase comparator 4.
The selector 3 is set so that a signal obtained by advancing the output of the VCO by 45 degrees and a signal from the data input pad 20 are input, and when the jitter transfer is adjusted, the output of the VCO 12 is set to 4
The selector 3 is set so that the signal advanced by 5 degrees and the output of the VCO 12 delayed by 45 degrees are input.

The normal operation of the CDR IC 27 will be described with reference to FIG. FIG. 3 shows the waveform 40 of the input 4a of the phase comparator 4 obtained by advancing the output of the VCO 12 by 45 degrees, the input waveform 4b from the data pad 20 to the phase comparator 4, and the output of the phase comparator 5 of the phase comparator 4. It is a figure which shows the relationship of the waveform 4c. Although the waveform 4b from the data input pad 20 is originally a random pattern, it is shown as an alternating waveform of Hi and Low for easy explanation. The phase comparator 5 of the phase comparator 4 samples and holds the waveform 4a obtained by advancing the output of the VCO 12 by 45 degrees at the rising edge of the waveform 4b from the data input pad 20. Therefore, the output 4c of the phase comparator 5 of the phase comparator 4 at time t1 has the amplitude of the output waveform of the VCO 12. This voltage is input to the VCO 12 through the variable gain section 6 of the phase comparator 4 and the filter 7 to lower the oscillation frequency of the VCO 12 and advance the output of the VCO 12 by 45 degrees with respect to the waveform 4b coming from the data input pad 20. The phase of 4a is shifted. In this way, the PLL 13 is connected to the waveform 4b of the data input pad 20 and VC.
It operates so that the phase of the waveform 4a obtained by advancing the output of O12 by 45 degrees matches.

Next, the operation of the CDR IC 27 when adjusting the jitter transfer band will be described with reference to FIGS. 4, 5 and 6.
FIG. 4 shows a circuit diagram when adjusting the jitter transfer band of the CDR IC 27. In FIG. 4, a variable voltage source 52 and a switch 51 capable of selecting a voltmeter 50 are connected to the pad 23 provided at the output of the phase comparator 4 of the CDR IC 27, and the pad 24 provided in the filter circuit 7 is connected to the pad 23. Capacity 10,
A switch 5 capable of selecting a variable voltage source 54 and a resistor 55 having the same resistance value as the resistor 11 instead of the resistor 11.
Connect 3.

The jitter transfer band ωjt is expressed by the equation (1). ωjt = Kd × Ad × Kh × Ko Equation 1 Here, Kd is the detection sensitivity of the phase comparator 5 of the phase comparator 4,
Ad is the amplification factor of the variable gain section 6 of the phase comparator 4, and Kh is the filter circuit 7 having the lag lead characteristic as shown in FIG.
The amplification factor Ko at the frequency f2 or higher of is the modulation sensitivity of the VCO 12. To adjust the jitter transmission band, first adjust Kh × Ko.
Is measured, and the resistance of the amplification factor of the variable gain unit 6 of the phase comparator 4 is trimmed so as to obtain a desired jitter transmission band.

For the measurement of Kh × Ko, in FIG. 4, the test pad 22 is set so that the output of the variable gain section 6 of the phase comparator 4 becomes high impedance, and the switch 51 is set so that the variable voltage source 52 is connected. Then, the switch 53 is set so that the resistor 55 is connected. As shown in FIG. 4, the frequency of the signal output from the clock output pad 26 of the variable voltage source is the lock frequency f of the CDR IC 27.
The voltage V1 and the voltage V2 are set in the vicinity of the voltage V0 which becomes 0, and the frequency of the signal output from the clock output pad 26 is measured. When the frequency of the signal output from the clock output pad 26 at the voltage V1 is f1 and the frequency of the signal output from the clock output pad 26 at the voltage V2 is f2, Kh × Ko is expressed by Equation 2. Kh × Ko≈ (f2-f1) / (V2-V1) Equation 2 Next, referring to FIG. 4, a signal obtained by advancing the output of the VCO 12 by 45 degrees to the test pad 21 and the phase comparator 4 and the output of the VCO 12 are delayed by 45 degrees. Selector 3 so that the input signal is input
Is set and the output of the amplification section 8 of the filter circuit 7 is set to high impedance, and the test pad 2
2 is set so that the variable gain unit 6 of the phase comparator 4 operates as an amplifier circuit, the switch 51 is set to be connected to the voltmeter 50, and the switch 53 is set to be connected to the voltage source 54. The source 54 is set so that the frequency of the signal output from the clock output pad 26 is f0.
Since the value of the voltmeter 50 is equal to Kd × Ad, the value of the voltmeter 50 can be adjusted to ω to adjust to the desired jitter transfer band ωjt.
The amplification factor of the variable gain unit 6 of the phase comparator 4 is adjusted by trimming the resistance value or the like so as to be jt / (Kh × Ko).

The reason why the value of the voltmeter 50 is equal to Kd × Ad will be described with reference to FIG. The phase comparator 4 has a VCO1
The signal 4a obtained by advancing the output of 2 by 45 degrees and the signal 4b obtained by advancing the output of the VCO 12 by 45 degrees are input. Phase comparator 4
The phase comparator 5 of uses a sample-and-hold type,
When the output signal of the VCO 12 is a sine wave, the output of the VCO 12 is advanced by 45 degrees and the output of the VCO 12 is changed to 45.
Since the delayed signal 4b is deviated by 90 degrees, the output of the phase comparator 5 has the same value as the amplitude Vp of the output signal of the VCO 12. Further, when the output signal of the output of the VCO 12 is a sine wave, the detection sensitivity of the phase comparison unit 5 of the phase comparator 4 when the CDR IC 27 is phase locked as shown at t5 in FIG. Since it is the inclination at t5, its value becomes equal to the amplitude Vp of the output signal of the VCO 12.

Because when the output of the VCO 12 is a sine wave, the output 4a of the VCO 12 is expressed by the equation (3). 4a = Vpsin (ωt) Formula 3 Since the slope Δ of the waveform 4a is represented by the differential of Formula 3, Formula 4 is obtained. Δ = Vp cos (wt) Equation 4 Since t5 at the time of phase lock is equal to the point of t = 0, Δ = Vp Equation 5 Therefore, the detection sensitivity of the phase comparator 5 of the phase comparator 4 is the amplitude Vp of the output signal of the VCO 12 Is equal to Therefore, the value of the voltmeter 50 becomes equal to Kd × Ad, and the jitter transfer band of the CDR IC 27 can be adjusted to a desired value by adjusting the value of Ad by trimming.

In FIG. 1, the filter circuit 7 is composed of the amplifier circuit section 8, the resistor 9 in the IC, the external capacitor 10 and the external resistor 11, but the characteristics of the lag lead as shown in FIG. If the above is obtained, it is not necessary to adopt such a configuration. Further, when adjusting the jitter transfer band, the output of the VCO 12 shifted by 90 degrees may be input to the phase comparison unit 5 of the phase comparator 4, so that the phase difference between the VCO 12 and the phase comparator 4 is +90 degrees as shown in FIG. The phase shifter 17 may be connected. Further, as shown in FIG. 8, a -9 is provided between the VCO 12 and the selector 3.
The 0 degree phase shifter 18 may be connected. When +45 degree phase shifter and -45 degree phase shifter are used, the phase shift caused by the circuit characteristics of each phase shifter cancels each other.
A phase difference of 90 degrees can always be produced.

According to this embodiment, the jitter transfer band can be adjusted by changing the gain of the variable gain section 6 of the phase comparator 4 by resistance trimming during the DC test of the IC. Therefore, no adjustment is required when assembling the optical module, and the cost of the optical receiving module can be reduced. Further, as shown in FIG. 4, the adjustment of the jitter transfer band does not use the expensive pulse pattern generator 76 or jitter analyzer 77, but the voltage sources 52 and 54 and the voltmeter 5 are used.
0, and the frequency meter 90 can be used, so that the cost of the optical receiving module can be reduced.

FIG. 9 is a circuit diagram showing another embodiment of the CDR IC according to the present invention. CDR I in FIG.
C27 is a phase shifter 1 of +45 degrees and a phase shifter 2 of -45 degrees.
And a frequency divider 19 connected to the output of the -45 degree phase shifter 2.
And a selector 3 for selecting the output of the data input pad 20 and the frequency divider 19, and a sample-and-hold type phase comparing section 5 and a circuit for comparing the phases of the output of the selector 3 and the output of the phase shifter 1 of +45 degrees. The phase comparator 4 including the variable gain unit 6 capable of varying the amplification factor by trimming the resistance value in the inside and the output of the test pad 21 having a high impedance and the test pad 22 The amplifier circuit section 8 capable of making the output high impedance by a signal, the resistor 9 in the IC, and the pad 24
A PLL comprising a filter circuit 7 having a lag lead characteristic as shown in FIG. 2, which is composed of an external capacitor 10 and a resistor 11 connected through a VCO (voltage controlled oscillator) 12.
(Phase-locked loop) 13, discriminator 14, data buffer 15, and clock buffer 16.

In FIG. 9, a signal obtained by advancing the output of the VCO 12 by 45 degrees from the test pad 21 to the phase comparator 4 and VC
The selector 3 is set so that the signal obtained by delaying the output of O12 by 45 degrees and dividing the frequency is input, and the filter circuit 7
Is set so that the output of the amplifying section 8 becomes high impedance, and the test pad 22 is connected to the variable gain section 6 of the phase comparator 4.
Operate as an amplifier circuit, switch 51 is connected to voltmeter 50, switch 53 is connected to voltage source 54, and voltage source 54 is output from clock output pad 26. A waveform when the frequency of the signal is set to f0 is shown in FIG.

In FIG. 10, a waveform 40 is a waveform of the input 4a of the phase comparator 4 obtained by advancing the output of the VCO 12 by 45 degrees,
The waveform 43 is the phase shifter 2 in which the output of the VCO 12 is delayed by 45 degrees.
The waveform of the output 2a, the waveform 44 of the
3 is divided into 1/2, the waveform of the output 19a of the frequency divider 19 and the waveform 42 are the output 4c of the phase comparison unit 5 of the phase comparator 4.
Shows the waveform of. The points t1 and t2 sampled by the phase comparison unit 5 of the phase comparator 4 are the peak points of the waveform 40.
The output of the phase comparison unit 5 of the phase comparator 4 shows the same value as the amplitude Vp of the output signal of the VCO 12, and the detection sensitivity of the phase comparison unit 5 of the phase comparator 4 can be obtained.

In the configuration of FIG. 1, the frequency of the signal 4b during the normal operation is a data signal, and therefore is less than half that of the signal 4b during the adjustment of the jitter transfer band, which is a clock signal. That is, the circuit to which the signal 4b of the phase comparator 5 of the phase comparator 4 is input requires an operating frequency that is twice as high as that in the normal operation, and a large amount of current is supplied to enable high speed operation. Occurs. In the configuration of FIG. 9, the phase comparison unit 5 of the phase comparator 4 needs to sample and hold at half the period of the configuration of FIG. 1, and the circuit design becomes easy when the CDR IC handles a high-speed signal. Further, when the same circuit is used, up to twice the frequency can be used. In Figure 9, +45 degrees,
A phase shifter of −45 degrees was used, but +9 as in FIGS.
A 0 degree or -90 degree phase shifter may be used.

Up to now, the method of adjusting the jitter transfer band of the CDR IC and the case of using the same in the optical module have been described in detail. However, the CDR I according to the present invention
C is not limited to the optical module. Fig. 15
FIG. 8 is a configuration diagram showing another embodiment using the CDR IC according to the present invention. In FIG. 15, the server and router 88
Is a plurality of multiplexers 80 and transmission line drivers 81.
A substrate 86 on which the CPU is mounted, a plurality of receiving amplifiers 82 and a CD
It is composed of a substrate 87 on which the RIC 83 and the demultiplexer 84 are mounted, and a plurality of transmission lines 85 connecting them. In the case of a server, CPUs are used for the substrates 86 and 87
However, a switching IC is mounted in the case of a router.

The transmission line 85 is a coaxial or twisted pair cable, or a wiring formed on a substrate. In a server or a router, in order to increase the amount of data transmission between boards and reduce the number of signal lines on the boards or boards in order to reduce the manufacturing cost, signals exceeding 1 GHz are passed through the transmission path 85. 1
For signals exceeding GHz, it is difficult to match the phases of data and clock, so only data signals are transmitted,
The clock is reproduced by the CDR IC83. CDR IC
Similarly to the case of the optical receiving module, the standard of the jitter 83 is determined, and the jitter transmission band needs to be adjusted in order to comply with the standard. Since a plurality of CDR ICs are mounted on the board, the adjustment time requires several tens of minutes to several hours. However, according to the present invention, it is sufficient to mount the ICs, and the cost of the server or the router can be reduced. .

[0033]

According to the present invention, it is possible to provide a CDRIC capable of adjusting a jitter transfer band during a DC test of an IC and a method of adjusting the jitter transfer band thereof. Also,
According to the present invention, it is possible to provide a CDR IC capable of adjusting the jitter transfer band and a method for adjusting the jitter transfer band thereof, without using an expensive measuring device such as a pulse pattern generator or a jitter analyzer.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of a CDR IC.

FIG. 2 is a diagram showing characteristics of a filter circuit of the CDR IC shown in FIG.

FIG. 3 is a diagram showing waveforms at various parts during normal operation of the CDR IC shown in FIG.

FIG. 4 is a circuit diagram showing a circuit when adjusting a jitter transfer band of the CDR IC shown in FIG.

FIG. 5 is a diagram showing the V when the jitter of the CDR IC shown in FIG. 1 is adjusted.
It is a figure which shows the CO modulation sensitivity measuring method.

FIG. 6 is a diagram showing waveforms at various parts during jitter adjustment of the CDR IC shown in FIG.

FIG. 7 is a circuit diagram showing another embodiment of the CDR IC.

FIG. 8 is a circuit diagram showing another embodiment of the CDR IC.

FIG. 9 is a circuit diagram showing another embodiment of the CDR IC.

FIG. 10 is a diagram showing waveforms at various parts during jitter adjustment of the CDR IC shown in FIG.

FIG. 11 is a diagram showing a configuration of an optical communication system.

FIG. 12 is a diagram showing jitter transfer characteristics of an optical receiver module and a CDR IC.

FIG. 13 is a configuration diagram showing a configuration of a conventional optical module when adjusting a jitter transfer band.

FIG. 14 is a flowchart showing an example of a procedure from assembly to shipping of a conventional optical module.

FIG. 15 is a diagram showing another embodiment using a CDR IC.

[Explanation of symbols]

1 ... + 45-degree phase shifter 2 ...- 45-degree phase shifter 3 ... Selector 4 ... Phase comparator 5 ... Phase comparator phase comparator 6 ... Phase comparator variable gain section 7 ... Filter circuit 8 ... Filter circuit Gain unit 9 ... Filter IC internal resistance 10 ... Filter circuit external capacitance 11 ... Filter circuit external resistance 12 ... VCO (voltage controlled oscillator) 13 ... PLL (phase locked loop) 14 ... Discriminator 15 ... Data output Buffer 16 ... Clock output buffer 17 ... +90 degree phase shifter 18 ... -90 degree phase shifter 19 ... Frequency divider 20 ... Data input pads 21, 22 ... Test pad 23 ... Phase comparator output voltage measurement pad 24 ... Filter pad 25 ... Data output pad 26 ... Clock output pad 27 ... CDR IC 30 ... Characteristics of output frequency with respect to VCO input voltage 31 ... Output frequency with respect to VCO input voltage Inclination of wave number characteristic at lock frequency f0 50 ... Voltmeter 51 ... Switch 52 ... Variable voltage source 53 ... Switch 54 ... Voltage source 55 ... Resistor 60 ... Multiplexer 61 ... Optical transmission module 62 ... Driver IC 63 ... Laser diode 64 ... Optical Fiber 65 ... Optical receiving module 66 ... Photodiode or avalanche photodiode 67 ... Transimpedance amplifier 68 ... Voltage amplifier 69 ... CDR IC 70 ... Demultiplexer 75 ... Standard optical transmission module 76 ... Pulse pattern generator 77 ... Jitter analyzer 80 ... Multiplexer 81 ... Transmission line driver 82 ... Receiving amplifier 83 ... CDR IC 84 ... Demultiplexer 85 ... Transmission lines 86, 87 ... Board 88 ... Server or router

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Akio Osaki             292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa             Inside the Hitachi, Ltd. production technology laboratory (72) Inventor Katsunori Hirano             292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa             Inside the Hitachi, Ltd. production technology laboratory (72) Inventor Takayuki Nakao             216 Totsuka-cho, Totsuka-ku, Yokohama-shi, Kanagawa             Inside this Opnext Co., Ltd. (72) Inventor Tomoaki Shimodu             216 Totsuka-cho, Totsuka-ku, Yokohama-shi, Kanagawa             Inside this Opnext Co., Ltd. (72) Inventor Jun Hasegawa             216 Totsuka-cho, Totsuka-ku, Yokohama-shi, Kanagawa             Inside this Opnext Co., Ltd. (72) Inventor Tetsuya Aoki             216 Totsuka-cho, Totsuka-ku, Yokohama-shi, Kanagawa             Inside this Opnext Co., Ltd. (72) Inventor Takeshi Yamashita             216 Totsuka-cho, Totsuka-ku, Yokohama-shi, Kanagawa             Inside this Opnext Co., Ltd. F term (reference) 5J106 AA03 BB05 CC01 CC24 CC44                       CC58 DD09 GG04                 5K002 AA05 CA00 GA07

Claims (4)

[Claims] 1. A clock / data recovery IC, wherein a phase-locked loop of the clock / data recovery IC advances a phase of a voltage-controlled oscillator and one of the branched output signals of the voltage-controlled oscillator by 45 degrees. +45 phase shifter, -45 phase shifter for delaying the phase of the other branched output signal of the voltage controlled oscillator by 45 degrees, and selector for selecting data from the data input pad and output of the -45 phase shifter And a phase comparator that compares the phase of the output selected by the selector with the phase of the output of the phase shifter of +45 degrees, and a lag lead characteristic that inputs the output of the phase comparator and outputs it to the voltage controlled oscillator. A filter circuit is provided, and the output signal of the +45 phase shifter and the output signal of the −45 phase shifter are input to the phase comparator when adjusting the jitter transfer band of the clock / data recovery IC. Clock and data recovery IC, wherein the door. 2. A clock / data recovery IC, wherein the phase-locked loop of the clock / data recovery IC advances a phase of a voltage-controlled oscillator and one of the branched output signals of the voltage-controlled oscillator by 90 degrees. A +90 phase shifter, a selector for selecting the other branched output signal of the voltage controlled oscillator and data from the data input pad, and an output selected by the selector and an output of the +90 degree phase shifter. A phase comparator for comparing the phases, and a filter circuit having a lag lead characteristic for inputting the output of the phase comparator and outputting it to the voltage controlled oscillator, and at the time of adjusting the jitter transfer band of the clock / data recovery IC, A clock / data recovery circuit, wherein the output signal of the +90 phase shifter and the other branched output signal of the voltage controlled oscillator are input to the phase comparator. IC. 3. A clock / data recovery IC, wherein the phase-locked loop of the clock / data recovery IC delays the phase of a voltage-controlled oscillator and one of the branched output signals of the voltage-controlled oscillator by 90 degrees. -90 phase shifter, a selector for selecting the data from the data input pad and the output of the -90 phase shifter, the phase of the output selected by the selector and the other branched output signal of the voltage controlled oscillator And a filter circuit having a lag lead characteristic for inputting the output of the phase comparator and outputting to the voltage controlled oscillator, the phase comparator at the time of adjusting the jitter transfer band of the clock / data recovery IC. Clock / data recovery I characterized in that the comparator outputs the other branched output signal of the voltage controlled oscillator and the output signal of the −90 phase shifter. . 4. Clock data having a data input pad, a data output pad, a clock output pad, a phase comparator, a voltage controlled oscillator, and a phase shifter for changing the phase of the output waveform of the voltage controlled oscillator. A method for adjusting a jitter transfer band of a recovery IC, wherein at least two output waveforms output from a voltage controlled oscillator and having a phase difference of about 90 degrees are input to the phase comparator. A method for adjusting a jitter transfer band of an IC.