KR101516327B1 - Apparatus and method for analog integrated circuit - Google Patents

Abstract

The present invention relates to an apparatus and method for designing an analog integrated circuit, comprising steps of inputting input design specifications, separating the entire circuits on a block-by-block basis, constructing a circuit of a self-coded code structure for each block, Adjusting the channel length ratio of the self-cascode code in correspondence with the block size, combining the block-by-block circuit, and comparing the characteristics of the entire circuit with the design specification. According to the present invention, since the area increase rate is smaller than that of using a single MOSFET, the manufacturing cost can be reduced. In addition, the performance of the circuit can be improved with a simpler and less effort than a method of adding a circuit designed to improve the performance. In addition, since the number of circuits to be added is small, the reliability of the circuit can be improved. In particular, the proposed design method for the analog circuit design using the latest process, the low-voltage nanometer-scale process, has a great effect.

Description

[0001] APPARATUS AND METHOD FOR ANALOG INTEGRATED CIRCUIT [0002]

The present invention relates to an apparatus and method for designing an analog integrated circuit, and more particularly to an analog integrated circuit designing an analog integrated circuit using a channel length change in a self-cascode structure having different threshold voltages Design apparatus and method.

In an analog integrated circuit design using a metal oxide semiconductor field effect transistor (MOSFET), a short channel MOSFET has a problem of channel modulation phenomenon (channel length modulation) is large, there is a problem in that it is used in an analog circuit requiring a high gain. To increase the output resistance, a long channel MOSFET should be used, which is several times longer than the minimum channel length.

However, since the long channel MOSFET has a lower transconductance than the short channel MOSFET, the channel width must be increased to increase the transconductance. Consequently, in order to reach a desired design specification, the area of the entire analog integrated circuit becomes large, which causes a problem of increasing the manufacturing cost.

Meanwhile, other analog integrated circuit design techniques can increase the output resistance by applying a general cascode structure. However, this general cascode structure has a problem that it is difficult to use in a low voltage analog circuit due to the limitation of a threshold voltage (V _TH ) and a low output voltage in consideration of the current trend in which the supply voltage is reduced.

Korean Patent Publication No. 10-2009-0127432 (published on December 11, 2009)

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a transconductance (gm) optimized according to a channel length combination of two MOSFETs of a self-cascading code structure having different threshold voltages. And a method of designing an analog integrated circuit capable of applying a self-cased code structure having a channel length ratio corresponding to a characteristic optimized for each circuit block so as to obtain an output resistance (r _out ) have.

According to another aspect of the present invention, there is provided an apparatus for designing an analog integrated circuit, including: a design specification input processing unit for performing input processing on a design specification; A block circuit constituting a circuit for each block according to the design specification; A block circuit coupling unit for coupling circuitry for each block; A simulation unit for simulating the block circuit unit and the block circuit unit, respectively; And an output unit for outputting a simulation result.

Meanwhile, the analog integrated circuit design method of the present invention is characterized by designing an analog integrated circuit using a channel length ratio of a self-cascode code structure having different threshold voltages.

Further, the analog integrated circuit design method of the present invention includes the steps of: (a) inputting input design specifications; (b) separating all the circuits on a block-by-block basis, and constructing a circuit of a self-coded code structure for each block; (c) adjusting a channel length ratio of the self-coded code in accordance with the design specification; (d) combining circuits for each block; And (e) comparing the characteristics of the entire circuit with the design specification.

In the step (b), the circuit is temporarily designed with the channel length ratio of the self-cascode structure being 50: 50.

Preferably, the step (c) further includes a step of simulating in accordance with the design specification.

A MOSFET (Metal Oxide Semiconductor Field Effect Transistor) included in the self-cased code structure includes a process including channel doping, a gate work function, and a gate oxide thickness; Device characteristics including a short channel effect and a reverse short channel effect; And a bias including a forward body bias and a gate bias; The threshold voltage is different from the threshold voltage.

As described above, according to the apparatus and method for designing an analog integrated circuit according to the present invention, the manufacturing cost can be reduced because the area increasing ratio is smaller than that of using a single MOSFET. That is, if an entire circuit is designed by applying a channel length combination having characteristics of transconductance or output resistance optimized for each circuit block, it is possible to design an analog integrated circuit having a maximum performance and a small area.

In addition, the performance of the circuit can be improved more easily and relatively easily than the method of adding a circuit designed for improving the performance. That is, it can improve the performance of the entire analog integrated circuit, reduce the manufacturing cost, and can be designed in an easier way.

Since the number of circuits to be added is small, the reliability of the circuit can be improved.

Especially, the proposed design method for the analog circuit design using the latest process, low-voltage nanometer-scale process, can be applied to great effect. That is, the self-cascode structure can increase the output resistance in analog integrated circuits using low voltage.

1 is a diagram illustrating a self-cascode code structure having different threshold voltages.
FIG. 2 is a graph showing characteristics according to channel length combinations of two MOSFETs in a self-coded code structure.
3 is a block diagram of an analog integrated circuit designing apparatus according to an embodiment of the present invention.
4 is a flowchart of a method of designing an analog integrated circuit according to an embodiment of the present invention.
5 is a schematic diagram of a general two-stage operational amplifier to illustrate the proposed design technique.
6 is a circuit diagram of a two-stage operational amplifier using the proposed analog integrated circuit design technique.
7 is a graph comparing the frequency response characteristics of a circuit designed with the conventional circuit and the proposed design method.

Hereinafter, an apparatus and method for designing an analog integrated circuit of the present invention will be described in detail with reference to the accompanying drawings.

1 is a diagram illustrating a self-cascode code structure having different threshold voltages.

와 같이 드레인측 모스펫의 문턱전압이 소스측 모스펫의 문턱전압보다 낮다. 이 구조에서 적절한 바이어스가 인가되면 높은 출력저항을 얻을 수 있다. 그 때 소스측 모스펫은 선형영역(linear region)에서 동작하고, 드레인측 모스펫은 포화영역(saturation region)에서 동작하게 된다. 여기서 단일 모스펫 M의 채널길이(channel length)는 L이고, 셀프 캐스코드 구조에서 소스(Source, S)측 모스펫 MS의 채널길이는 L_S 이고, 드레인(Drain, D)측 모스펫 MD의 채널길이는 L_D 이다. 셀프 캐스코드 구조에서 두 모스펫의 채널길이 합은 단일 모스펫의 채널길이와 동일하게 유지하여 L_S + L_D = L 로 정의한다. 채널폭(channel width, W)은 동일하다.
Referring to FIG. 1, a self-coded code structure having different threshold voltages is connected to two MOSFETs with gates (Gate, G). The source side MOSFET and the drain side MOSFET may have different threshold voltages,

The threshold voltage of the drain side MOSFET is lower than the threshold voltage of the source side MOSFET. In this structure, a high output resistance can be obtained when an appropriate bias is applied. The source side MOSFET then operates in a linear region and the drain side MOSFET operates in a saturation region. Here, the channel length of the single MOSFET M is L, the channel length of the source (S, S) side MOSFET MS in the self-coded code structure is L _S, and the channel length of the drain (D, L _D. In the self-coded code structure, the sum of the channel lengths of two MOSFETs is defined as L _S + L _D = L by keeping the channel length of the single MOSFET at the same value. The channel width (W) is the same.

FIG. 2 is a graph showing characteristics according to channel length combinations of two MOSFETs in a self-coded code structure.

(

) 을 추가로 만족하여 L_S가 L_D보다 작은 비율보다 출력저항이 증가하게 되고, 또한 단일 모스펫보다 향상된다. 그러므로 최대의 출력저항을 갖는 채널길이 L_S와 L_D 조합을 찾을 수 있다. 회로 설계를 위해서 선택한 공정의 모스펫 소자를 이용한 셀프 캐스코드 구조의 채널길이 조합에 따른 특성이 도 2와 같다면, 트랜스컨덕턴스가 중요한 회로 블럭에는 L_S가 L_D보다 작은 비율을 갖는 셀프 캐스코드를 적용하고, 출력저항이 중요한 회로 블록에는 L_S가 L_D 보다 큰 비율을 갖는 셀프 캐스코드를 적용하면, 최적의 설계가 가능하다. 그리고, 트랜스컨덕턴스와 출력저항 모두 적절히 향상시켜야 된다면, 적절한 채널길이 비율을 선택하여 적용하면 설계하고자 하는 아날로그 회로의 성능을 향상시킬 수 있다.
Referring to FIG. 2, the graphs show changes in transconductance and output resistance depending on the ratio of L _S and L _D in the channel length sum L of the self-coded code structure in the applied bias, and the channel widths are the same as described above . As L _S becomes smaller than L _D , the transconductance increases more than a single MOSFET. The reason is that the total transconductance of the self-cascode is determined by the transconductance of the source-side MOSFET in the linear region, so that the shorter the source-side MOSFET channel length L _S , the greater the transconductance. Conversely, when the ratio of L _S increases, the transconductance decreases and the output resistance tends to increase. This is another condition of the self-cascading code structure

(

) Is satisfied so that the output resistance is higher than the ratio that L _S is smaller than L _D , and is also improved than that of a single MOSFET. It is therefore possible to find a combination of channel lengths L _S and L _D with maximum output resistance. If the characteristics of the self-cascode structure using the MOSFET device of the selected process for the circuit design are the same as those in FIG. 2, a circuit block in which transconductance is important includes a self-cascode having a ratio L _S smaller than L _D And a circuit block in which output resistance is important, an optimum design is possible by applying a self-coded code having a ratio of L _S to L _D. If both the transconductance and the output resistance need to be appropriately improved, the performance of the analog circuit to be designed can be improved by selecting an appropriate channel length ratio.

3 is a block diagram of an analog integrated circuit designing apparatus according to an embodiment of the present invention.

3, an analog integrated circuit designing apparatus according to the present invention includes a design specification input processing unit 1 for performing input processing on a design specification, a block circuit constituting a circuit for each block according to design specifications A simulation unit 4 for simulating the block circuit configuration unit 2 and the block circuit combination unit 3 and a simulation unit 4 for simulating the simulation results And an output unit 5 for outputting the output signal.

4 is a flowchart of a method of designing an analog integrated circuit according to an embodiment of the present invention.

Referring to FIG. 4, first, a design specification of an analog circuit to be designed is inputted (S1), and each circuit block necessary for the entire circuit is designed using a self-cascode code structure. First, a circuit is temporarily designed (S2) using the channel length ratio L _S : L _D = 50: 50 of the self-cascode code structure. Considering the design specifications, considering the function and characteristics of each circuit block, the block for high frequency characteristics and high transconductance should be changed to a high ratio of transconductance by adjusting the channel length ratio. do. On the other hand, a circuit block which requires a high gain or a high output impedance is adjusted so that the output resistance is optimized in comparison with the design specification by adjusting the channel length ratio (S3 to S4). The process of simulating the optimization in S3 to S4 may be selectively performed. Next, the optimized circuit blocks are connected to complete the entire circuit (S5), and the characteristics of the entire circuit are simulated and compared with the design specification (S6). If there is a deficiency in the comparison result, optimization of each circuit block is performed again, and the circuit is applied to the entire circuit and then compared with the design specification again. If the design specification matches the result, the design process is finished (S7).

5 is a schematic diagram of a general two-stage operational amplifier to illustrate the proposed design technique.

Referring to FIG. 5, in order to improve the performance of the circuit, the P-type MOSFETs MP3 to MP5 corresponding to the current mirror circuit blocks for the bias of the first and second stages require a large output resistance. channel length ratio is a maximum L _S: L _D = 80: applying a self-cascode structure 20, the differential input P-MOSFET MP1 ~ MP2 of the first stage transport from Figure 2 in order to increase the noise, and the operating frequency It is possible to increase the voltage gain and gain bandwidth, which are the main performance characteristics of the entire two-stage operational amplifier, by applying the self-cascode code structure with the channel length ratio L _S : L _D = 20: 80 at which the conductance becomes maximum.

6 is a circuit diagram of a two-stage operational amplifier using the proposed analog integrated circuit design technique.

Referring to FIG. 6, the conventional two-stage operational amplifier shown in FIG. 5 is a two-stage operational amplifier circuit applying the P-type MOSFETs MP1 to MP5 to the self-cascode code structure having the optimum characteristics with the proposed design technique. The N-type MOSFETs MN1 to MN3 can also apply a self-cascode code structure having optimum characteristics.

7 is a graph comparing the frequency response characteristics of a circuit designed with the conventional circuit and the proposed design method.

Referring to FIG. 7, a frequency response characteristic comparing the performance of the two-stage operational amplifier of FIG. 5 and FIG. 6 is shown. The red color is a response characteristic of the circuit proposed in the present invention. As in the graph, the low frequency voltage gain is increased by 10dB and the gain bandwidth is increased by 1MHz. In the experiment, all conditions such as power supply voltage, bias current, load capacitor, frequency compensation capacitor and resistance were applied equally.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the invention.

1: design specification input processing unit
2: Block circuit constituent part
3: Block circuit connecting part
4: Simulation section
5: Output section

Claims (6)

delete An analog integrated circuit design method for designing an analog integrated circuit using a channel length ratio of a self - coded code structure having different threshold voltages.
(a) inputting input design specifications;
(b) separating all the circuits on a block-by-block basis, and constructing a circuit of a self-coded code structure for each block;
(c) adjusting a channel length ratio of the self-coded code in accordance with the design specification;
(d) combining circuits for each block; And
(e) comparing the characteristics of the entire circuit with the design specification.
The method of claim 3,
Wherein the step (b) temporarily designs the circuit by setting the channel length ratio of the self-cascode structure to 50:50.
The method of claim 3,
Wherein said step (c) further comprises the step of simulating corresponding to said design specification.
The method of claim 3,
A MOSFET (Metal Oxide Semiconductor Field Effect Transistor) included in the self-
A process including channel doping, a gate work function, and a gate oxide thickness;
Device characteristics including a short channel effect and a reverse short channel effect; And
Bias including forward body bias, gate bias;
Wherein the threshold voltages are different from each other.

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