KR101506699B1 - Memory having column decoder precharge circuit for preventing program inhibit failure - Google Patents

Abstract

A memory including a column decoder divided into two or more sub-decoders is disclosed. The influence of the parasitic capacitance at one terminal of the switch of the highest level included in the column decoder is eliminated by the charging section that charges the terminal every time the least significant bit of the column address changes.

Description

[0001] The present invention relates to a memory including a column decoder precharge circuit for preventing a program inhibit malfunction,

The present invention relates to a column decoder structure for preventing inhibit data destruction caused by program inhibit in a memory.

1 shows an internal structure of a general NAND flash memory. The memory 101 includes an input / output pad 100, a control logic 200, an analog block 300, a cell array 400, address decoder blocks 510, 520 and 530, a multiplexer 610 , 620, 630).

The input / output pad 100 may be connected to the terminals exposed to the outside in the package of the memory 101. Although FIG. 1 illustrates a configuration in which a plurality of address and data input / output terminals are provided, it is also possible to receive addresses and data through only one terminal. The control logic 200 receives an address, a control signal, and data from the input / output pad 100 and analyzes the same to generate address decoders blocks 510, 520 and 530, an analog block 300, and input / output pads 100 Can be controlled. The analog block 300 may include circuitry for providing the necessary power to the cell array 400 and the address decoder blocks 510, 520 and 530 and may be controlled by the control logic 200.

In an embodiment of the present invention, the cell array 400 may be a NAND cell array, and may have a two-dimensional matrix structure including rows and columns. Each column is referred to as a word-line, and each row may be referred to as a bit-line. In addition, the cell array 400 may be divided into N sectors.

An address input to the memory 1 may indicate a specific area of the cell array 400, and the column address of the address may be decoded by the column decoder 530. One or more multiplexers 610, 620, and 630 may be interposed in the internal path through which the input data and output data of the memory 101 are transferred.

As the capacity of the NAND flash memory increases, the page size also increases. For example, if the page size of a 256M NAND flash memory is 512 bytes, the page size of a 1G NAND flash memory will increase to 2K bytes. As the page size increases, the number of bits representing the column address given externally is also increased. As a result, the column decoder is affected internally by the circuit, and a column decoder method different from that of the prior art is required.

First, the operation of the NAND flash memory included in the subject of the present invention will be described with reference to FIGS. 2 to 4B.

FIG. 2 shows a basic structure of a page buffer, a column decoder array, and a sense amplifier used in a NAND flash memory of the present invention, and FIG. 3 shows an example of a timing diagram of a program data load operation of a NAND flash memory.

After a program load command 80h is applied from the outside of the NAND flash memory, a column address and a low address are applied. For example, the column address may be input over two cycles, and the row address may be input over three cycles. Thereafter, data for a program data load operation is applied. 3, when the program load instruction 80h is applied, the PDRSTb signal is internally enabled to enable the PDDATA node of the write register 4 of the page buffer 1 to be set to logic high (logical high). In the NAND flash memory, cell data is made logic high by an erase operation and cell data is made logic low by a program operation. Therefore, when the data applied when the program data is loaded is logically high, an inhibit operation for leaving the cell data as it is is performed. When the program data is logic low, a program operation for making the cell data logic low is performed. Initially setting the write register to a high state implies performing in-bit operation on all cell data during program operation. Now, only when the program data input from the outside is logic low, the operation of making the PDDATA of the write register logic low is performed.

After the program load command, the column address, and the row address are applied, DLOADEN becomes logically high as shown in FIG. 3, and node A and node B are brought to a logic low state in FIG. At this time, the switches (transistors) controlled by the predecode signals YA, YB, and YC and the internal signal MAINPATH form an electrical path in the corresponding column. Now, when a logic low is applied as program data from the outside, the DI signal becomes internally a logic high and the nDI signal becomes a logic low, so that the PDDATA node becomes a logic low state. If the program data is externally applied to the logical high, the DI becomes the logic low and the nDI becomes the logic high state internally, so that the PDDATA initialized in the initial state remains unchanged.

FIG. 4A shows an example of a structure of a general column decoder used in a NAND flash, and FIG. 4B shows blocks for generating a pre-decoding signal for the column decoder. The symbols YA, YB, and YC shown in FIGS. 4A and 4B represent a pre-decoding signal generated from an externally applied column address. For example, if a column address ADD <0: 9> is externally applied as shown in FIG. 4B, YA <0:15> represents a predecoded signal generated from the column address ADD <0: 3> , YC <0: 7> represents a predecoded signal generated from a column address ADD <4: 6> and YC <0: 7> represents a predecoded signal generated from a column address ADD < .

The column decoder includes a plurality of page buffers PB [·] [· · · ·] and a plurality of switches (transistors). The page buffer is a temporary storage of data input and output through the input / output pads. The plurality of switches may be controlled by a first predecode signal YA < - >, a second predecoded signal YB < - >, and a third predecoded signal YC & , Or a transistor. Hereinafter, for the sake of convenience of explanation, it is assumed that control is performed by a first pre-decoded signal YA <->, a second pre-decoded signal YB <->, and a third predecoded signal YC < The first level switch, the second level switch, and the third level switch can be referred to as YA, YB, and YC, respectively.

When the column address input to the NAND flash memory is, for example, 10 bits (ADD <0: 9>), a total of 2 ^ 10 = 1024 page buffers shown in FIG. 4A may be provided. At this time, if a specific column address is input, only one page buffer corresponding to the address of 1024 page buffers can be selected. To this end, the column address may be converted into the pre-decoded signal. More specifically, by using the lower 1 bits of the 10-bit column address, 2 < n > pieces of the first pre-decoding signal YA < (1 + n + m = 1) can be generated by using 2 pre-decoding signals (YB < Number of bits of address = 10).

At this time, with respect to a specific column address, only one of the 2 1 1 pre-decoded signals YA < 1 > has a value of 1, and 2 n second pre-decoded signals YB &lt; Only one of them has a value of '1', and only one of 2 ^ m third predecoding signals YC <·> has a value of '1'.

The above-described pre-decoding signal can be used as a signal for controlling the plurality of switches 'YA', 'YB', and 'YC' shown in FIG. 4A. FIG. 4A illustrates a case where a pre-decoded signal with l = 4, m = 3, and n = 3 is generated using a 10-bit column address. 4A, a total of eight third-level switches under the control of the third predecoding signal YC <-> are present, and the control of the second predecoding signal YB < There are a total of 8 * 8 = 64 second level switches receiving the first pre-decoded signal YA &lt; - &gt;, and a total of 8 * 8 * 16 = 1024 first level switches under the control of the first pre- It is easy to understand. Here, 'c', 'b', and 'a' represent the page buffer to the reference potential unit 88, respectively, A first predecoding signal, a second predecoding signal, and an index of a third predecoding signal used for connection.

  As described above, only one signal for each of the first predecoded signal YA <->, the second predecoded signal YB <-> and the third predecoded signal YC <-> , Only one of the 1024 page buffers shown in FIG. 3 can be connected to the reference potential portion 88. In this case, In the example of FIG. 4A, one column address is converted into three levels of pre-decoded signals YA <·>, YB <·>, and YC < It can be understood that it may be.

Referring to FIG. 4A, the output signals of all transistors controlled by YA <0:15> are all collected at the drain input of the transistor under the control of YB <0> Is applied similarly. Signals gathering at the drain node of the transistor under control of YB <0> internally have parasitic junction capacitance and line loading. If the value of such parasitic capacitance is large, the undesired operation fatal It can cause defects.

More specifically, the YA <0> signal is commonly used in the page buffer PB [0] [0] [0] and the page buffer PB [0] [7] [0] . YB <0> is used for the page buffer PB [0] [0] [0], but YB <7> is used for the page buffer PB [0] [7] [0]. Here, it is assumed that serial data is written into the write registers of the respective page buffers after the program load instruction 80h is applied. In this case, the logical high data is written in the write register of the page buffer PB [0] [0] [0] (that is, the program inhibit bit) It can be seen that the logical low data (i.e., program) is written in the write register of the buffer PB [0] [7] [0]. In this case, while the predecode signal YA <0> is commonly enabled and the row data is written to the write register of the page buffer PB [0] [7] [0] ] [0] [0]) can be disturbed by the parasitic capacitance of node A. When the parasitic capacitance of the node A is large, the node PDDATA of the write register of the page buffer PB [0] [0] [0] becomes a logic low, causing malfunction.

The problem may not be serious if the PMOS size of the write register is large enough, but it is difficult to make the PMOS size sufficiently large because the size of the page buffer affects the net die. Therefore, when the parasitic capacitance value of the node C becomes large, the PDDATA is affected by the parasitic capacitance, and a logical failure occurs. This is called Program Inhibit Failure.

High or low values may be sequentially written to a plurality of page buffers provided in the NAND flash memory. At this time, a column decoder array is used to select one page buffer to be recorded. An operation for writing a page buffer may occur due to the parasitic capacitance existing in the column decoder array. In the present invention, a new column decoder structure is provided to minimize a parasitic capacitance value, thereby preventing a malfunction that may occur in program inhibit operation.

The precharge circuit provided to solve the above problem prevents erroneous operation due to parasitic capacitance by precharging the parasitic node in which the parasitic capacitance of the column decoder array exists at a necessary time. The driving of the precharge circuit is performed whenever there is a transition of LSB (Least Significant Bit) (e.g., A0) of the external input address when sequential program data is loaded. Each time there is an LSB transition, a short pulse is generated and used to operate the precharge circuit.

A memory according to one aspect of the present invention includes a plurality of page buffers, a column decoder array, and a sense amplifier, and is electrically connected to the sense amplifier side among terminals of one switch included in the column decoder array Terminal is precharged to an arbitrary potential value equal to or higher than the reference potential during a precharge pulse section generated every time the least significant bit of the column address is changed.

A memory according to another aspect of the present invention includes a plurality of page buffers, a column decoder array, and a sense amplifier. One terminal of the first switch of the highest level included in the column decoder array, which is electrically connected to the sense amplifier, is connected to a reference terminal during a precharge pulse section generated every time the least significant bit of the column address is changed. And is precharged to an arbitrary potential above the potential.

According to another aspect of the present invention, a memory includes a column decoder array including a plurality of subarrays, and a sense amplifier. At this time, a terminal electrically connected to the sense amplifier among the terminals of the switch of the highest level constituting each sub-array may be precharged to an arbitrary potential value equal to or higher than the reference potential every time the least significant bit of the column address is changed, .

The plurality of sub-arrays may be connected to different sense amplifiers, and one sub-array of the plurality of sub-arrays may be connected to the column (s) And may be selected by the n most significant bits of the address.

According to another aspect of the present invention, a memory includes a plurality of low-level switches controlled by low-order bits of a column address, and a high-level switch connected to the plurality of low- A column decoder array including a column decoder array; And a sense amplifier electrically connected to one terminal side of the high level switch. At this time, a switch is connected to the one terminal to precharge the one terminal to an arbitrary potential value above the reference potential whenever the least significant bit of the column address changes.

At this time, the switch is a transistor, and the transistor can be controlled by a pre-charge pulse that occurs during any time period each time the least significant bit changes.

At this time, the memory may further include a plurality of page buffers. When a program load instruction, a column address, and a plurality of external program data are sequentially input, the address of the page buffer is incremented by one unit from the column address every time the plurality of external program data is input, External program data can be recorded in the page buffer.

At this time, when the program load instruction is input, the write register included in the page buffer can be initialized to a logic high state.

According to the present invention, it is possible to prevent program inhibit malfunction which may occur in a column decoder of a memory.

1 shows an internal structure of a general NAND flash memory.
2 shows a basic structure of a page buffer, a column decoder array, and a sense amplifier used in the NAND flash memory of the present invention.
3 shows an example of a timing diagram of a program data load operation of a NAND flash memory in an embodiment of the present invention.
4A shows an example of the structure of a general column decoder used in NAND flash.
FIG. 4B shows blocks for generating a pre-decoding signal for the column decoder shown in FIG. 4A.
5A and 5B show an internal structure of a column decoder according to an embodiment.
6A shows a structure of a column decoder according to an embodiment of the present invention.
6B shows an example of a precharge pulse generating circuit for generating a precharge pulse PreATD used in the column decoder array of FIG. 6A.
FIG. 7A shows the structure of the input / output pads, the column decoder, and the cell array shown in FIG. 1 in more detail.
Fig. 7B shows an example in which the input / output pad of Fig. 7A is modified.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings, which will be readily apparent to those skilled in the art to which the present invention pertains. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. In addition, the singular forms used below include plural forms unless the phrases expressly have the opposite meaning.

The memory according to embodiments of the present invention may be a non-volatile memory element. A non-volatile memory device may also refer to a memory device that can retain data even when power is removed. For example, such non-volatile memory devices may include flash memory, EEPROM, phase change memory (PRAM), magnetic memory (MRAM), resistive memory (RRAM), and the like. On the other hand, the flash memory may be referred to as a floating gate memory, a charge trap memory, a SONOS memory or the like, and its name does not limit the scope of these embodiments.

In embodiments of the present invention, a NAND cell array may refer to an array of memory cells having a NAND structure.

As the page size of the NAND flash memory increases, the number of bits of the external address may increase. As the number of bits in the external address increases, the number of pre-decoded signals in the circuit increases. As the number of pre-decoded signals in the circuit increases, the size of the chip increases. The layout area in the design of the column decoder can be determined with the highest priority. Therefore, efforts are needed to reduce the number of pre-decoded signals generated from the number of bits of a given external address. An embodiment of a column decoder improved by such an effort will be described with reference to FIGS. 5A and 5B.

5A and 5B show an internal structure of a column decoder according to an embodiment.

The column decoder of FIG. 5A is divided into a column decoder on the left side dotted line box 61 side and a column decoder on the right side dotted line box 62 side. The column decoder shown in FIG. 5A has the same structure as the column decoder of FIG. 4A except for the content of the third predecoding signal YC <..> For controlling the third level switch. 5A and 5B, when the column address ADD <0: 9> is applied from the outside, the third predecoding signal YC <0: 3> is outputted from the column address ADD < But no signal corresponding to the third predecoded signal YC <4: 7> shown in FIG. 4B is generated. The internal signal MAINPATHH is generated using the column address ADD <9>, the internal signal MAINPATHH is connected to the source of the third level switch of the right dotted box 62, MAINPATHL is connected to the source of the third level switch of the left dotted box 61. [ It can be seen that a total of four third-level switches are present.

Comparing FIGS. 4A and 5A, it can be seen that the overhead of layout can be reduced by reducing the number of pre-decoding signals by changing the column decoder structure even when the same page size is used. In the case of FIG. 5A, the layout is made smaller than in FIG. 4A, and the number of net dies can be increased.

However, when the column decoder is configured as shown in FIG. 5A, the possibility of program inhibit malfunction increases. As shown in FIG. 5A, when the left side dotted line box 61 and the right side dotted line box 62 are compared, the left data or the right data is distinguished by a switch (transistor) under the control of the internal signal MAINPATHH / MAINPATHL, All have the same configuration.

Therefore, when the program data is written into the write register of the page buffer PB [4] [0] [0] of the right side dotted box 62, the page buffer PB [0] [0]), the node PDDATA of the write register experiences a program inhibit malfunction that is seriously disturbed by the parasitic capacitances of nodes A, B, and C.

6A shows a structure of a column decoder according to an embodiment of the present invention. FIG. 6B shows an example of a precharge pulse generating circuit for generating a precharge pulse PreATD used in the column decoder of FIG. 6A. FIG. 3 shows an example of a timing diagram for a column decoder according to an embodiment of the present invention shown in FIGS. 6A and 6B. 6A, 6B, and 3 will be described below together.

The column decoder shown in Fig. 6A is different from the column decoder shown in Fig. 5A except that the precharge circuit 102 controlled by the precharge pulse PreATD is connected to the source of the third level switch YC. Decoder. The precharge pulse circuit of FIG. 6B generates a precharge pulse PreATD every time an address transition by an LSB (ADD <0>) of an external input address is detected. The generated pre-charge pulse PreATD precharges (? V _CC -V _THN ) the node A, the node B, and the node C in which the parasitic capacitance exists. As a result, the PDDATA node of the write register in the page buffer to be program inhibited is kept in its initial state (logical high), and program inhibit malfunction is prevented.

At the time when the pre-charge pulse is generated, the internal signal MAINPATHH / MAINPATHL becomes a logic low, disconnecting between the sense amplifier and the page buffer, and simultaneously precharging node A, node B, and node C of FIG. . Since the NAND flash basically performs a continuous read / write operation, the LSB of the external input address can be used as a source for generating the pre-charge pulse.

Although FIG. 6A illustrates an embodiment in which the precharge circuit 102 is connected to node C, it is readily understood that the precharge circuit 102 may be provided and connected to one or more of node A, node B, . That is, when the precharge circuit 102 is connected to at least one of the nodes A, B, and C, the node A, the node B, and the node C are precharged to a desired value during the time period during which the precharge pulse is generated .

Herein, the node A can be regarded as a node formed by the terminals of the first level switches YA included in the column decoder array 14, which are electrically connected to the sense amplifier 3 side . Also, the node B can be regarded as a node formed by the terminals of the second level switches YB included in the column decoder array 14, which are electrically connected to the sense amplifier 3 side have. The node C can be regarded as a node formed by the terminals electrically connected to the sense amplifier 3 among the terminals of the third level switches YC included in the column decoder array 14 have.

FIG. 7A shows the structure of the input / output pads, the column decoder, and the cell array shown in FIG. 1 in more detail.

For example, eight data (DATA [0] to DATA [7]) can be input or output simultaneously via the input / output pad 100. [ The cell array 400 may include a plurality of subarrays 410 to 480 for storing the eight data. According to this configuration, each binary data input through different input / output pads may be temporarily stored in different page buffer blocks 501 to 508 and stored in the subarrays 410 to 480. The page buffer blocks 501 to 508 shown in FIG. 7A are included in the column decoder 530 of FIG.

Fig. 7B shows an example in which the input / output pad of Fig. 7A is modified. In the modified embodiment, the input / output pad 100 'is configured to receive addresses, commands, and data through only one pad. However, N consecutive data among the serial input data may be simultaneously provided to other blocks of the memory through a plurality of paths as shown in FIG. 7A.

The NAND flash memory according to the embodiment of the present invention may have an internal structure according to FIG. 7A or 7B. The column decoder shown in Figs. 4A, 5A, and 6A may be a column decoder included in any page buffer block among the eight page buffer blocks 501 to 508 shown in Fig. 7A.

Hereinafter, a NAND flash memory according to an embodiment of the present invention will be described with reference to FIGS. 3, 6A, and 6B.

This memory includes a page buffer 13, a column decoder array 14 and a sense amplifier 3. At this time, a terminal (ex: source) to be electrically connected to the sense amplifier 3 among the terminals of the highest level first switch YC included in the column decoder array 14 is connected to the least significant bit of the column address is precharged to an arbitrary potential value equal to or higher than the reference potential during a pre-charge pulse (PreATD) period generated every time the voltage (ex: ADD <0>) changes.

At this time, when a program load instruction 80h, one external column address C1 and C2 (ex: ADD <0: 9>), and a plurality of external program data D0 to Dx are sequentially inputted, Each of the external program data D0 to Dx is incremented by one unit from the external column addresses C1 and C2 each time the external program data D0 to Dx is input to the page buffer 13, As shown in Fig.

At this time, the column decoder array 14 includes 2 ^ n subarrays 71 and 72 (where n is a natural number), and one of the subarrays 71 and 72 has n uppermost Is selected by the bit (ex: ADD <9>). The first switch YC selects an upper bit (ex: ADD <7: 8) of the remaining bits (ex: ADD <0: 8>) excluding the n most significant bits (ex: ADD < : 8 &gt;).

Different sense amplifiers 31 and 32 are connected to the 2n subarrays 71 and 72 so that only one subarray of the 2n subarrays 71 and 72 is selected And the sense amplifier ex 31 connected to the one sub array ex 71 and the one sub array ex 71 are electrically short-circuited during the pre-charge pulse PreATD period. This paragraph can be made, for example, by a switch controlled by the internal signal MAINPATHL.

Hereinafter, a NAND flash memory according to another embodiment of the present invention will be described with reference to FIGS. 3, 6A, and 6B.

The memory includes a column decoder array 14 including a plurality of subarrays 71 and 72, and a sense amplifier 3. At this time, a terminal (ex: source) electrically connected to the sense amplifier 3 among the terminals of the highest level switch YC constituting each of the sub-arrays 71, And is precharged to an arbitrary potential value equal to or higher than the reference potential every time the least significant bit ADD <0> changes.

Hereinafter, a NAND flash memory according to another embodiment of the present invention will be described with reference to FIGS. 3, 6A, and 6B.

This memory is connected to a plurality of lower level switches YA controlled by the lower bit (ex: ADD <0: 3>) of the column address and to the plurality of lower level switches YA, A column decoder array 14 including an upper level switch YC controlled by a bit ex: ADD <7: 8>; And a sense amplifier 3 adapted to be electrically connected to one terminal (source) side of the high level switch YC. The switch 102 is connected to the one terminal to precharge the one terminal to an arbitrary potential above the reference potential whenever the least significant bit ADD <0> of the column address changes.

Although the embodiments of the present invention have been described with reference to the NAND flash memory, the present invention can include all the structures of the memory to which the above structure can be applied.

The memory according to the embodiment of the present invention can be used in a computer, a mobile phone, a mobile device, a personal digital assistant (PDA) navigation device, a home appliance, and the like.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is evident that many alternatives, modifications, and variations will readily occur to those skilled in the art without departing from the spirit and scope of the invention.

Therefore, it should be understood that the disclosed embodiments are to be considered in an illustrative rather than a restrictive sense, and that the true scope of the invention is indicated by the appended claims rather than by the foregoing description, and all differences within the scope of equivalents thereof, .

Claims (11)

A plurality of page buffers, a column decoder array, and a sense amplifier,
One terminal of the first switch of the highest level included in the column decoder array, which is electrically connected to the sense amplifier, is connected to the reference potential during a precharge pulse period generated every time the least significant bit of the column address is changed, And is precharged to an arbitrary potential value,
Memory. The method according to claim 1,
When the program load command, the one column address, and the plurality of external program data are sequentially input, an address indicating the page buffer is incremented by one unit from the column address every time the plurality of external program data is input, And to write the external program data to the page buffer,
Memory. The method according to claim 1,
The column decoder array includes 2 ^ n subarrays (where n is a natural number)
The plurality of sub-arrays being selected by the n most significant bits of the column address,
Wherein the first switch is controlled by an upper bit consisting of a part or all of remaining bits excluding the least significant bit among the remaining bits excluding the n most significant bits among the column addresses,
Memory. The method of claim 3,
The 2 &lt; n &gt; sub-arrays are connected to different sense amplifiers,
Only one of the 2 &lt; n &gt; sub-arrays is selected,
Wherein the sense amplifiers connected to the one sub array during the pre-charge pulse interval and the one sub array are electrically short-
Memory. A column decoder array including a plurality of subarrays, and a sense amplifier,
One terminal electrically connected to the sense amplifier among the terminals of the highest level switches constituting each sub array is precharged to an arbitrary potential value equal to or higher than the reference potential every time the least significant bit of the column address is changed there is,
Memory. 6. The method of claim 5,
The number of the plurality is 2 ^ n (where n is a natural number)
Each of the plurality of sub-arrays may be connected to different sense amplifiers,
Wherein one sub-array of the plurality of sub-arrays is selected by the n most significant bits of the column address,
Memory. A column decoder array including a plurality of lower level switches controlled by lower bits of a column address and an upper level switch connected to the plurality of lower level switches and controlled by upper bits of the column addresses; And
And a sense amplifier which is electrically connected to one terminal side of the high level switch,
/ RTI &gt;
The one terminal is connected to a switch for precharging the one terminal to an arbitrary potential value equal to or higher than the reference potential every time the least significant bit of the column address changes,
Wherein the least significant bit of the upper bit is a bit located higher than the most significant bit of the lower bit,
Memory. 8. The memory of claim 7 wherein the switch is a transistor and the transistor is controlled by a precharge pulse that occurs during any time period each time the least significant bit changes. 8. The method of claim 7,
Further comprising a plurality of page buffers,
When the program load instruction, the one column address, and the plurality of external program data are sequentially input, the address of the page buffer is incremented by one unit from the column address every time the plurality of external program data is input, And to write the program data to the page buffer,
Memory. 10. The memory of claim 9, wherein when a program load instruction is entered, the write register included in the page buffer is initialized to a logic high state. A plurality of page buffers, a column decoder array, and a sense amplifier,
One terminal of one switch included in the column decoder array is electrically connected to the sense amplifier. The one terminal is connected to the sense amplifier through a precharge pulse interval generated every time the least significant bit of the column address is changed. To-charge,
Memory.

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