KR20120005840A - Flash rom device - Google Patents

Flash rom device Download PDF

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Publication number
KR20120005840A
KR20120005840A KR1020100066516A KR20100066516A KR20120005840A KR 20120005840 A KR20120005840 A KR 20120005840A KR 1020100066516 A KR1020100066516 A KR 1020100066516A KR 20100066516 A KR20100066516 A KR 20100066516A KR 20120005840 A KR20120005840 A KR 20120005840A
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KR
South Korea
Prior art keywords
bit line
rom
precharge
node
sensing node
Prior art date
Application number
KR1020100066516A
Other languages
Korean (ko)
Inventor
김병영
Original Assignee
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1020100066516A priority Critical patent/KR20120005840A/en
Publication of KR20120005840A publication Critical patent/KR20120005840A/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/24—Bit-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/30—Power supply circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay

Abstract

Flash ROM device according to an embodiment of the present invention, ROM for storing data; First bit line precharge circuits for precharging a bit line selected according to the first precharge control signal and a bit line selection signal; Second bit line precharge circuits for precharging the sensing node in response to the second precharge control signal; Bit line selection circuits for transferring a voltage precharged to the sensing node to a bit line selected by the bit line selection signal; ROM latches for latching a potential of the sensing node changed in response to data stored in the ROM in response to first and second data loading signals; Outputs a bit line selection signal for selecting the bit line, the first and second precharge control signals, and prevents the voltage state of the sensing node from being transmitted to the ROM latches while the bit line is precharged; And a control logic for outputting the first and second data loading signals to control the potential of the sensing node to latch.

Description

Flash rom device

The present invention relates to a flash ROM device.

In general, a flash ROM refers to a chip that electrically erases and rewrites an existing content of a programmable ROM (PROM), which is a scan-only memory that can be updated, and is also called a flash electrically erasable PROM (EEPROM).

The EEPROM has the same function, but the flash ROM can be manufactured cheaper than the DRAM (Dynamic Random Access Memory) because the structure is simple and the chip can be made small. It is mainly used in the mass storage device of a portable computer, and it is advantageous in that it can be miniaturized compared to a hard disk drive. It does not need a backup power source and is also strong in shock.

In a flash ROM, memory cells are connected to a plurality of bit lines and word lines. When the data is read, the selected bit line is precharged, and a read voltage is applied to the selected word line to sense that the voltage of the bit line is changed to read the data.

An embodiment of the present invention provides a flash ROM device which shortens the time for precharging a bit line of a flash ROM, increases the precharge voltage level, and prevents data collision with the ROM latch during the bit line precharge operation.

Flash ROM device according to an embodiment of the present invention,

ROM for data storage; First bit line precharge circuits for precharging a bit line selected according to the first precharge control signal and a bit line selection signal; Second bit line precharge circuits for precharging the sensing node in response to the second precharge control signal; Bit line selection circuits for transferring a voltage precharged to the sensing node to a bit line selected by the bit line selection signal; ROM latches for latching a potential of the sensing node changed in response to data stored in the ROM in response to first and second data loading signals; Outputs a bit line selection signal for selecting the bit line, the first and second precharge control signals, and prevents the voltage state of the sensing node from being transmitted to the ROM latches while the bit line is precharged; And a control logic for outputting the first and second data loading signals to control the potential of the sensing node to latch.

The flash ROM device according to an embodiment of the present invention further comprises a precharge circuit for precharging the bit line to reduce the precharge time, prevent the precharge voltage from falling, and to prevent the ROM from evaluating the bit line. This can prevent the latch from affecting.

1 shows a flash ROM device according to an embodiment of the present invention.
FIG. 2 illustrates a portion of the second bit line precharge circuit group and ROM latch of FIG. 1.
3 illustrates a first bit line precharge circuit group of FIG. 2.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. It is provided to inform you.

1 shows a flash ROM device according to an embodiment of the present invention.

Referring to FIG. 1, a flash ROM device 100 according to an embodiment of the present invention may include a read only memory (ROM) 110, first and second bit line precharge circuit groups 120 and 130, and a ROM latch group. 140, peripheral circuit 150 and control logic 160.

ROM 110 includes memory cells for data storage. The memory cells are connected to a bit line BL and a word line WL.

The first and second bit line precharge circuit groups 120 include circuits for selecting and precharging bit lines, and the ROM latch group 140 is connected to the second bit line precharge circuit group 130 to form a bit line. ROM latches 141 are configured to sense and store data according to a line voltage.

Peripheral circuit 150 includes circuits that operate to select a word line of ROM 110 and to read data.

The control logic 160 controls operations of the first and second bit line precharge circuit groups 120 and 130, the ROM latch group 140, and the peripheral circuit 150 stored in the ROM 110.

FIG. 2 illustrates a portion of the second bit line precharge circuit group and ROM latch of FIG. 1.

Referring to FIG. 2, the second bit line precharge circuit group 130 includes a second bit line precharge circuit 131 and a bit line selection circuit unit 132.

The second bit line precharge circuit 131 and the bit line selection circuit unit 132 are connected to 16 bit lines BL <15: 0>, and the second bit line precharge circuit group 130 includes 16 The first bit line precharge circuit 131 and the bit line selection circuit unit 132 are connected to each bit line.

One second bit line precharge circuit 131 is connected to one ROM latch 141.

The first bit line precharge circuit group 120 is positioned up and down with the second bit line precharge circuit group 130 and the ROM 110 interposed therebetween.

For convenience of description, FIG. 2 is shown by changing the vertical arrangement of the first and second bit line precharge circuit groups 120 and 130 in comparison with FIG.

The control logic 160 inputs the ROM precharge signal ROMPRECH and the bit line selection signals CS <15: 0> to the second bit line precharge circuit group 120.

The control logic 160 inputs the precharge control signal PRECH_N and the bit line selection signals CS <15: 0> to the second bit line precharge circuit group 130.

The second bit line precharge circuit 131 includes first to fifth PMOS transistors P1 to P5 and first and second NMOS transistors N1 and N2.

The first and second PMOS transistors P1 and P2 are connected in series between the power supply voltage VCC and the node K1.

The power supply voltage VCC is input to the drain of the first PMOS transistor P, and the gate and the source of the first PMOS transistor P are commonly connected. The drain of the second PMOS transistor P2 is connected to the source of the first PMOS transistor P, and the source of the second PMOS transistor P2 is connected to the node K1. The gate of the second PMOS transistor P2 is connected to the ground node.

The third PMOS transistor P3 is connected between the power supply voltage VCC and the node K1, and the precharge control signal PRECH_N is input to the gate of the third PMOS transistor P3.

Bit lines BL <15: 0> are connected to node K1.

The bit line selection circuit unit 132 connects one of the bit lines BL <15: 0> to the node K1 by the bit line selection signals CS <15: 0>.

When one of the bit line selection signals CS <15: 0> CS <k> and the precharge control signal PRECH_N are input from the control logic 160, the bit line selection signal CS <k> is inputted to the bit line selection signal CS <k>. The selected bit line BL <k> is precharged.

The ROM latch 141 includes third to seventh PMOS transistors P3 to P7, first to fifth NMOS transistors N1 to N5, and first and second inverters IN1 and IN2.

The fourth and fifth PMOS transistors P4 and P5 and the first and second NMOS transistors N1 and N2 are connected in series between a power supply voltage and a ground voltage. The first data loading signal LOAD_MBUS_N is input to the gate of the fourth PMOS transistor P4.

Gates of the fifth PMOS transistor P5 and the first NMOS transistor N1 are commonly connected to the node K1. The connection point of the fifth PMOS transistor P5 and the first NMOS transistor N1 is connected to the node K2.

The second data loading signal LOAD_MBUS_D is input to the gate of the second NMOS transistor N2.

The first data loading signal LOAD_MBUS_N and the second data loading signal LOAD_MBUS_D are inverted signals.

The sixth and seventh PMOS transistors P6 and P7 and the third and fourth NMOS transistors N3 and N4 are connected in series between a power supply voltage and a ground voltage.

The second data loading signal LOAD_MBUS_D is input to the gate of the sixth PMOS transistor P6, and the gates of the seventh PMOS transistor P7 and the third NMOS transistor N3 are commonly connected to the node K2. The connection point of the seventh PMOS transistor P7 and the third NMOS transistor N3 is connected to the node K3.

The first data loading signal LOAD_MBUS_N is input to the gate of the fourth NMOS transistor N4.

The fifth NMOS transistor N5 is connected between the node K2 and the ground voltage, and a reset signal RESET is input to the gate of the fifth NMOS transistor N5.

In the ROM latch 141, the sixth and seventh PMOS transistors P6 and P7 and the third and fourth NMOS transistors N3 and N4 are controlled by the first and second data loading signals LOAD_MBUS_N and LOAD_MBUS_D. It is an inverter. Thus, a latch circuit is connected to the node K2 and the node K3 together with the first inverter IN1.

The first and second inverters IN1 and IN2 are connected in series between the node K2 and the data output line MBUS. The output terminal of the first inverter IN1 is the node K3.

The ROM latch 141 senses and stores the voltage of the node K1 and provides it to the data output line MBUS.

The bit line selection circuit unit 132 includes switching elements for connecting each of the bit lines BL <15: 0> to the node K1 by each of the bit line selection signals CS <15: 0>. The bit line selection circuit unit 132 is composed of, for example, NMOS transistors connected between the node K1 and each of the bit lines BL <15: 0>.

The second bit line precharge circuit 131 of the second bit line precharge circuit group 130 transfers the power supply voltage VCC to the node K1 in response to the precharge control signal PRECH_N.

The precharge voltage of the node K1 is provided to the bit line selected by the bit line selection circuit unit 132. The bit line selection circuit unit 132 generally uses an NMOS transistor. Therefore, when the power supply voltage VCC for the bit line precharge is provided to the bit line, it is transferred to VCC-Vth which is separated by the threshold voltage of the NMOS transistor.

Meanwhile, the first bit line precharge circuit group 120 is not connected to the ROM latch group 140 and may provide the bit line precharge voltage to the bit line without voltage drop.

3 illustrates a first bit line precharge circuit group of FIG. 2.

3 specifically shows only the first bit line precharge circuit group 120, which is connected to the bit lines BL <15: 0>, respectively.

Referring to FIG. 3, the first bit line precharge circuit group 120 includes first bit line precharge circuits 121 connected to each bit line.

The first bit line precharge circuit 121 includes a NAND gate NA and an eighth PMOS transistor P8.

One of the ROM precharge signals ROMPRECH and the bit line selection signals CS <15: 0> is input to the NAND gate NA. The eighth PMOS transistor P8 is connected between the power supply voltage and one of the bit lines BL <15: 0>.

The output of the NAND gate NA is input to the gate of the eighth PMOS transistor P8.

The operation of the first bit line precharge circuit 121 is as follows.

To precharge the bit line BL <15>, the control logic 160 pre-suppresses the high level ROM precharge signal ROMPRECH and the high level bit line selection signal CS <15>. Input to the charge circuit 121.

Accordingly, since the NAND gate NA outputs a low level signal, the eighth PMOS transistor P8 is turned on. The PMOS transistor P does not cause a voltage drop when the power supply voltage is transferred to the bit line BL <15>.

The operation of the first and second bit line precharge circuit groups 120 and 130 and the data read of the flash ROM device 100 by the ROM latch group 140 described above with reference to FIGS. 2 and 3 are performed as follows. .

For example, when reading data of a memory cell connected to the bit line BL <15>, the control logic 160 first starts the high-level ROM precharge control signal ROMPRECH and the bit line selection signal CS <15. >) And a low level precharge control signal PRECH_N.

The eighth PMOS transistor P8 of the first bit line precharge circuit 121 is turned on by the high level ROM precharge control signal ROMPRECH and the bit line selection signal CS <15> to turn on the bit line BL < 15>), the power supply voltage is input.

At the same time, the third PMOS transistor P3 of the second bit line precharge circuit 131 is turned on and a power supply voltage is applied to the node K1.

The bit line selection circuit unit 132 selects the bit line BL <15> and connects it to the node K1.

Since the bit lines BL <15> are precharged by the first and second bit line precharge circuits 121 and 131, they are quickly precharged as compared with those precharged by one bit line precharge circuit.

Since the first bit line precharge circuit 121 receives a power supply voltage without a voltage drop, it is precharged without a voltage drop.

The power supply voltage is applied to the node K1 while precharging the bit line. Accordingly, the first NMOS transistor N1 of the ROM latch 141 is turned on.

Even when the first NMOS transistor N1 is turned on, the data of the nodes K2 and K3 of the ROM latch 141 is not changed. The reason is that the control logic 160 outputs the high level first data loading signal LOAD_MBUS_N and the low level second data loading signal LOAD_MBUS_D while precharging the bit line.

Accordingly, the fourth PMOS transistor P4 and the second NMOS transistor N2 are turned off.

When the fourth PMOS transistor P4 and the second NMOS transistor N2 are turned off, the data of the node K2 is not changed regardless of the operation of the fifth PMOS transistor P5 and the first NMOS transistor N1. .

Since the sixth PMOS transistor P6 and the fourth NMOS transistor N4 are turned on, data is continuously maintained at the nodes K2 and K3 of the ROM latch 141.

After the precharge of the bit line is completed, the control logic 160 changes the ROM precharge signal ROMPRECH to a low level. The precharge control signal PRECH_N changes to a high level. A read voltage is applied to a word line connected to the memory cell for reading data, and a pass voltage is applied to the remaining word lines.

If the threshold voltage of the memory cell is greater than the read voltage, the bit line maintains a precharge state, and if the threshold voltage of the memory cell is less than the read voltage, the precharge voltage of the bit line is discharged.

As a result, the voltage level of the node K1 is changed.

If the threshold voltage of the memory cell is greater than the read voltage, the node K1 is at a high level since it is connected to the precharged bit line.

The first NMOS transistor N1 of the ROM latch 141 is turned on because the node K1 is at a high level.

After changing the bit line voltage, the control logic 160 outputs the low level first data loading signal LOAD_MBUS_N and the high level second data loading signal LOAD_MBUS_D for data latching.

When the control logic 160 outputs the low level first data loading signal LOAD_MBUS_N and the high level second data loading signal LOAD_MBUS_D, the state of the node K1 may be transmitted to the node K2. It's about a short time.

The control logic 160 changes the first data loading signal LOAD_MBUS_N to a high level and changes the second data loading signal LOAD_MBUS_D to a low level again.

Therefore, the state of the node K1 transferred to the node K2 may be stored in the ROM latch 141.

The data may be output to an external data output line MBUS through the second inverter IN2.

In the flash ROM device 100 according to the embodiment of the present invention described above, two bit line precharge circuits operate when precharging a bit line, thereby reducing the precharge time, and the first bit line precharge circuit. By 121, a power supply voltage without voltage drop is precharged to the bit line.

Since the voltage state of the node K1 is controlled without affecting the ROM latch 141 while the bit line precharge is performed by the first and second data loading signals LOAD_MBUS_N and LOAD_MBUS_D, The data state can be kept stable.

Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, it will be understood by those skilled in the art that various embodiments of the present invention are possible within the scope of the technical idea of the present invention.

110: ROM
120: first bit line precharge circuit group
130: second bit line precharge circuit group
140: ROM latch group
150: peripheral circuit
160: control logic

Claims (6)

ROM for data storage;
First bit line precharge circuits for precharging a bit line selected according to the first precharge control signal and a bit line selection signal;
Second bit line precharge circuits for precharging the sensing node in response to the second precharge control signal;
Bit line selection circuits for transferring a voltage precharged to the sensing node to a bit line selected by the bit line selection signal;
ROM latches for latching a potential of the sensing node changed in response to data stored in the ROM in response to first and second data loading signals;
Outputs a bit line selection signal for selecting the bit line, the first and second precharge control signals, and prevents the voltage state of the sensing node from being transmitted to the ROM latches while the bit line is precharged; And a control logic for outputting the first and second data loading signals to control the potential of the sensing node to be latched.
Flash ROM device comprising a. The method of claim 1,
Each of the first bit line precharge circuits includes:
A logic gate for NAND combining a first precharge control signal and a bit line selection signal from the control logic; And
And a first switching element coupled between a power supply voltage and each bit line, the first switching element operating in response to an output of the logic gate. The method of claim 2,
The ROM latches are each
A first inverter connected between the sensing node and a first node and inverting and outputting a voltage level of the sensing node in response to the first and second data loading signals;
A second inverter connected between the first node and a second node; And
And a third inverter connected between the second node and the first node in a direction opposite to the second inverter, the third inverter being operated by inverted signals of the first and second data loading signals. The method of claim 1,
And the first inverter and the third inverter alternately operate. The method of claim 1,
The first bit line precharge circuits are disposed on top of the ROM,
And the second bit line precharge circuits and a bit line selection circuit are disposed under the ROM. The method of claim 1,
And the first bit line precharge circuits, the second bit line precharge circuit, and the bit line selection circuit simultaneously precharge the bit line selected by the bit line selection signal.
KR1020100066516A 2010-07-09 2010-07-09 Flash rom device KR20120005840A (en)

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KR1020100066516A KR20120005840A (en) 2010-07-09 2010-07-09 Flash rom device

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Application Number Priority Date Filing Date Title
KR1020100066516A KR20120005840A (en) 2010-07-09 2010-07-09 Flash rom device

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9842654B2 (en) 2015-07-06 2017-12-12 Samsung Electronics Co., Ltd. Nonvolatile memory device with improved reliability and operating speed

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9842654B2 (en) 2015-07-06 2017-12-12 Samsung Electronics Co., Ltd. Nonvolatile memory device with improved reliability and operating speed
US10102910B2 (en) 2015-07-06 2018-10-16 Samsung Electronics Co., Ltd. Nonvolatile memory device with first and second precharge circuit

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