KR101489887B1 - System and method for processing interrupt - Google Patents

Abstract

A system for processing interrupt in an ARM processor includes: a secure area unit including an interrupt request (IRQ) handler to process fast interrupt request (FIQ) interrupt; a non-secure area unit including an IRQ handler to process IRQ interrupt; and a monitor module including an FIQ handler caller and an IRQ handler caller, and configured to determine whether the secure area unit is processing exceptions or not. The FIQ handler caller calls the IRQ handler of the secure area unit in order to process FIQ interrupt received from an external hardware device. The IRQ handler caller calls the IRQ handler of the non-secure area unit in order to process IRQ interrupt received from the external hardware device. When the monitor module determines that the secure area unit is processing exceptions, the FIQ handler caller inactivates the FIQ interrupt, and activates the FIQ interrupt again when the exception processing is ended. Therefore, even when the secure area unit of the ARM processor receives FIQ interrupt during exception handling, the secure area unit can process the FIQ interrupt without an error.

Description

[0001] SYSTEM AND METHOD FOR PROCESSING INTERRUPT [0002]

The present invention relates to an interrupt processing system and method.

As one of the System On Chip (SoC) technologies in ARM processors, there is ARM TrustZone technology to enhance hardware level security. This is divided into a secure area (Secure World) and a non-secure area (Normal World), and the memory and devices used in each area can be divided and used.

ARM TrustZone technology is a technique for improving security. However, since the memory and the device including the CPU are divided into two areas, it is utilized as a method for virtualizing an embedded device in a situation requiring two virtual machines come.

On the other hand, the ARM processor defines seven exceptions that can occur during execution: RESET, UNDEFINED INSTRUCTION, SWI, PREFETCH ABORT, DATA ABORT, IRQ, and FIQ. At this time, the ARM processor can provide two interrupt priority models separated by FIQ and IRQ. When the above exception occurs, the ARM processor changes the execution mode, processes the exception, and returns to the original execution mode.

Specifically, all devices connected to the SoC can generate interrupts, which can be configured to send interrupts to the processor in the form of either FIQ or IRQ. In particular, in the ARM TrustZone virtualization environment, it is possible to provide a separate interrupt handling method for the devices used in the two areas, by allowing the security area to transmit FIQ interrupts and the non-security area to transmit IRQ interrupts.

Hereinafter, a conventional interrupt processing method will be described with reference to FIG.

1 is a diagram showing a conventional interrupt processing method.

ARM TrustZone according to the related art can provide interrupts to FIQ and IRQ in each area in order to provide an interrupt to an operating system executed in two security areas and non-security areas. At this time, the FIQ interrupt is transferred to the security area, and the IRQ interrupt is transferred to the non-security area.

Linux, ported to ARM processors, is designed to receive all device interrupts in the form of IRQ interrupts. Therefore, in order to run Linux ported to the ARM processor in the operating system of the security realm, it must be modified to handle interrupts coming into the FIQ. However, the current ARM Linux has to make the IRQ handler of the ARM Linux handle the interrupts coming into the FIQ because it receives the interrupts as IRQs and processes them in IRQ mode.

Referring to FIG. 1, when an FIQ interrupt occurs in the hardware and is transmitted to the monitor module (S110), the monitor module calls the IRQ handler of the security area to process the FIQ interrupt (S111). Then, the FIQ interrupt is processed through the IRQ handler in the security area (S113). In this way, in the interrupt processing system according to the related art, if the security area section is not in exception processing, an error does not occur even if FIQ interrupt occurs.

However, if an operation for requesting exception processing occurs in hardware (S120), and an FIQ interrupt occurs in the security area appending exception handling process (S121) (S130), the monitor module transfers the FIQ interrupt to the IRQ handler (S131). In this way, if FIQ interrupt occurs when the security area is in exception processing, "BAD Mode in Interrupt" error occurs. This is because the ARM processor prohibits other exceptions from occurring while processing exceptions. However, when an interrupt is received and processed by an IRQ, the above problem does not occur due to a difference in mechanism that operates in hardware when an exception occurs.

[Table 1] below describes the relationship between activation and deactivation of FIQ interrupts or IRQ interrupts in hardware in each exception processing.

exception handling FIQ IRQ Reset Disabled Disabled Undefined Instruction Activation Disabled SWI Activation Disabled Prefetch Abort Activation Disabled Data Abort Activation Disabled IRQ Activation Disabled FIQ Disabled Disabled

Referring to Table 1 above, since the IRQ interrupt is set to be inactivated in all exception handling, the problem caused by the IRQ interrupt does not occur in exception handling. On the other hand, FIQ interrupts are disabled only for RESET and FIQ exception handling, so there is a problem that the "BAD Mode in Interrupt" error occurs when the FIQ interrupt occurs in the remaining exception handling.

Korean Patent Registration No. 10-2010-0052477 (entitled " Method of Determining Interrupt Processing Mode of Embedded Operating System Kernel ") discloses an interrupt handling method of an embedded operating system kernel in which a plurality of interrupt processing modes can be performed. A mode determination method is disclosed.

Korean Unexamined Patent Application Publication No. 10-2013-0012126 (entitled " exception event processing apparatus and method ") discloses a processing circuit, an exception return register, a stack pointer register, a stack pointer selection circuit, And a data processing apparatus.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems of the conventional art, and it is an object of the present invention to provide a monitor module in which the FIQ handler of the monitor module can be modified so that even when an FIQ interrupt occurs during the exception processing in the security area of the ARM processor, And to provide an interrupt processing system and method for enabling an FIQ interrupt to be handled.

According to a first aspect of the present invention, there is provided an interrupt processing system in an ARM processor, the interrupt processing system including an interrupt request (IRQ) handler for processing a Fast Interrupt reQuest (FIQ) interrupt, And a monitor module including a non-security area unit including an IRQ handler for processing an IRQ interrupt, an FIQ handler calling unit and an IRQ handler calling unit, for discriminating whether or not the security area unit is under exception processing, Calling the IRQ handler of the security area to process the FIQ interrupt received from the hardware device, and the IRQ handler calls an IRQ handler of the non-security area to process the IRQ interrupt received from the external hardware device, The monitor module includes a security zone If it is determined that the in-process, after the call handler FIQ FIQ unit disables the interrupt and the exception processing is completed thereby re-enable the FIQ interrupts.

A method for processing a FIQ interrupt in a virtualization environment of an ARM processor according to the second aspect of the present invention includes receiving an FIQ interrupt from an external hardware device, Determining whether an exception is being handled in the ARM processor divided into a security area section and a non-security area section each including an IRQ (Interrupt ReQuest) handler; if the ARM processor is determined to be in exception processing, The FIQ handler call unit activating the deactivated FIQ interrupt, the FIQ handler call unit calling the IRQ handler of the security area unit; The IRQ handler in the secure area performs the FIQ interrupt Comprising the step of, IRQ handler of said security zone is IRQ handler processes the interrupt FIQ, and the non-secure region of the process an IRQ interrupt.

According to the above-described embodiment of the present invention, the FIQ interrupt can be handled through the IRQ handler in the secure area using ARM TrustZone virtualization. That is, it is possible to solve a problem occurring in the FIQ interrupt processing required for operating a general-purpose operating system such as Linux in both the security area and the non-security area.

Accordingly, even if the FIQ interrupt is received during the exception processing in the security area of the ARM processor, the FIQ interrupt can be processed without generating an error.

You can also handle FIQ interrupts in the secure area without modifying the Linux IRQ handler.

1 is a diagram showing a conventional interrupt processing method.
2 is a block diagram of an interrupt processing system in an ARM processor in accordance with an embodiment of the present invention.
3 is a diagram illustrating an example of an algorithm applied to the FIQ handler call unit according to the prior art and the present invention.
4 is a flowchart of a method of processing an interrupt in an ARM processor according to an embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings, which will be readily apparent to those skilled in the art. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. In order to clearly illustrate the present invention, parts not related to the description are omitted, and similar parts are denoted by like reference characters throughout the specification.

Throughout the specification, when a part is referred to as being "connected" to another part, it includes not only "directly connected" but also "electrically connected" with another part in between . Also, when an element is referred to as "comprising ", it means that it can include other elements as well, without departing from the other elements unless specifically stated otherwise.

2 is a block diagram of an interrupt processing system 100 in an ARM processor in accordance with one embodiment of the present invention.

The interrupt processing system 100 according to an embodiment of the present invention includes a security area 110, a non-security area 120, and a monitor module 130.

2 refers to a hardware component such as software or an FPGA (Field Programmable Gate Array) or ASIC (Application Specific Integrated Circuit), and performs predetermined roles .

However, 'components' are not meant to be limited to software or hardware, and each component may be configured to reside on an addressable storage medium and configured to play one or more processors.

Thus, by way of example, an element may comprise components such as software components, object-oriented software components, class components and task components, processes, functions, attributes, procedures, Routines, segments of program code, drivers, firmware, microcode, circuitry, data, databases, data structures, tables, arrays, and variables.

The components and functions provided within those components may be combined into a smaller number of components or further separated into additional components.

The security area 110 includes an Interrupt ReQuest (IRQ) handler 115 for processing an FIQ (Fast Interrupt request) interrupt. And the non-secure region 120 includes an IRQ handler 125 for processing IRQ interrupts.

In this case, the security area 110 and the non-security area 120 may be managed by independent operating systems. In this case, the operating system may be Linux. That is, the TrustZone of the ARM processor can divide one physical processor core into the security area 110 and the non-security area 120. When the ARM TrustZone is booted, each area is booted do. Each area of the ARM TrustZone can be generated by dividing registers of the CPU and registers related to the page table and interrupts into the security area 110 and the non-security area 120, respectively. As described above, the security area 110 and the non-security area 120 can be independently operated for each area, and can be managed by a separate operating system.

The monitor module 130 plays an intermediate role between the security area 110 and the non-security area 120, and is responsible for switching and interrupt processing of each area. When a device interrupt occurs, the monitor module 130 moves the processor to the execution flow with an interrupt handler set in a specific address area called a monitor vector, and processes an FIQ interrupt and an IRQ interrupt in the interrupt handler. In addition, the SMC (Secure Monitor Call) command called through switching of each area is also processed by the monitor module 130, and is responsible for storing and restoring the processor context information for switching each area.

The monitor module 130 includes an FIQ handler calling unit 131 and an IRQ handler calling unit 133. At this time, the FIQ handler calling unit 131 calls the IRQ handler 115 of the security area unit 110 to process the FIQ interruption received from the external hardware device 10. The IRQ handler calling unit 133 calls the IRQ handler 125 of the non-security area unit 120 to process the IRQ interrupt received from the external hardware device 10.

Meanwhile, the monitor module 130 determines whether the security area 110 is under exception processing. At this time, when the monitor module 130 determines that the security area unit 110 is under exception processing, the FIQ handler calling unit 131 deactivates the FIQ interrupt, and activates the FIQ interrupt after the exception process is completed.

That is, before calling the IRQ handler 115 of the security area 110, the monitor module 130 determines whether or not the security area 110 of the currently executing processor is processing an exception. If the FIQ interrupt occurs in the security area 110 of the processor, the processor 110 forcibly disables the FIQ interrupt and waits for the currently generated FIQ interrupt for a while. After the next exception processing step is completed, the waiting FIQ interrupt is reactivated and processed.

The monitor module 130 determines whether or not the security area 110 is under exception processing before calling the IRQ handler 115 of the security area 110 to process the FIQ interrupt. Interrput "errors can be prevented. Accordingly, the security area unit 110 can process the FIQ interrupt without modifying the IRQ handler 115 of the secure area 110. [

Alternatively, when the monitor module 130 determines that the security area 110 is not under exception processing, the FIQ handler calling part 131 transmits the FIQ interrupt to the IRQ handler 115 of the security area 110 via the IRQ handler 115 You can call it to process.

Hereinafter, an example of an algorithm applied to the FIQ handler calling unit 131 of the monitor module 130 will be described with reference to FIG.

3 is a diagram illustrating an example of an algorithm applied to the FIQ handler call unit according to the prior art and the present invention.

In the case of the algorithm applied to the FIQ handler calling unit according to the related art, if the FIQ handler calling unit of the monitor module receives the FIQ interrupt in step S11, the FIQ handler calling unit issues an FIQ interrupt to process the IRQ handler in the security area unit .

At this time, the FIQ handler calling unit according to the related art has no step of discriminating whether or not the security area unit is under exceptional processing, and accordingly, there is a problem that a "BAD Mode in Interrupt" error occurs when the FIQ interrupt is received during exception processing.

Otherwise, in the case of the algorithm applied to the FIQ handler calling unit 131 according to the present invention, it is determined in step S21 whether the security area unit 110 is under exception processing. At this time, if it is determined that the security area unit 110 is under exception processing, the FIQ interrupt is disabled in step S23. That is, it waits for the FIQ interrupt until the exception processing ends. Next, the process returns to the exception process execution step through step S25 to perform exception processing.

As described above, when the FIQ interrupt occurs, the FIQ handler calling unit 131 included in the interrupt processing system 100 according to the present invention determines whether or not the security area unit 110 is under exception processing, It is possible to solve the error problem that has occurred in the FIQ handler calling unit according to the related art.

4 is a flowchart illustrating a method of processing an FIQ interrupt using the interrupt processing system 100 according to an embodiment of the present invention.

In the interrupt processing method according to the present invention, when an FIQ interrupt is generated from the hardware device 10 (S210), the monitor module 130 of the ARM processor receives the FIQ interrupt.

Next, the monitor module 130 determines whether or not an exception is being processed in the ARM processor divided into the security area 110 and the non-security area 120 including the IRQ handlers 115 and 125 (S220). That is, before the FIQ interrupt is transmitted to the IRQ handler 115 of the security area 110, an exception is generated from the hardware device 10 to determine whether or not the security area 110 is processing an exception .

At this time, if it is determined that the ARM processor is in exception processing, the FIQ handler calling unit 131 deactivates the FIQ interrupt (S230) and waits for the FIQ interrupt for a while. As a result, the ARM processor first handles the exception handling that it is performing.

Next, when the exception process being performed by the ARM processor is terminated (S240), the FIQ handler activates the disabled FIQ interrupt (S250). The FIQ handler calling unit 131 calls the IRQ handler 115 of the security area 110 in step S255 and the IRQ handler in the security area 110 processes the FIQ interrupt in step S260.

As described above, the interrupt processing method according to the present invention first determines whether or not an exception process is being executed in the ARM processor before delivering the FIQ interrupt to the IRQ handler 115 of the secure area 110, thereby determining whether the "BAD Mode in Interrput" The existing problems can be solved.

Alternatively, when it is determined that the ARM processor is not under the exception processing, the monitor module 130 transmits the IRQ handler 115 of the security area 110 through the FIQ handler calling part 131 to process the FIQ interrupt, (S255). Accordingly, the IRQ handler 115 of the secure area 110 processes the FIQ interrupt (S260).

The IRQ handler 115 of the security area 110 included in the monitor module 130 processes FIQ interrupts and the IRQ handler 125 of the non-security area 120 processes IRQ interrupts. At this time, the security area unit 110 and the non-security area unit 120 are managed by independent operating systems, and the operating system applied may be Linux. Meanwhile, the security area 110 and the non-security area 120 have been described in detail with reference to FIG. 2, and will not be described below.

One embodiment of the present invention may also be embodied in the form of a recording medium including instructions executable by a computer, such as program modules, being executed by a computer. Computer readable media can be any available media that can be accessed by a computer and includes both volatile and nonvolatile media, removable and non-removable media. In addition, the computer-readable medium may include both computer storage media and communication media. Computer storage media includes both volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data. Communication media typically includes any information delivery media, including computer readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave, or other transport mechanism.

It will be understood by those skilled in the art that the foregoing description of the present invention is for illustrative purposes only and that those of ordinary skill in the art can readily understand that various changes and modifications may be made without departing from the spirit or essential characteristics of the present invention. will be. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive. For example, each component described as a single entity may be distributed and implemented, and components described as being distributed may also be implemented in a combined form.

The scope of the present invention is defined by the appended claims rather than the detailed description and all changes or modifications derived from the meaning and scope of the claims and their equivalents are to be construed as being included within the scope of the present invention do.

10: Hardware device 100: Interrupt processing system
110: security area unit 115, 125: IRQ handler
120: Non-security area part 130: Monitor module
131: FIQ handler calling part 133: IRQ handler calling part

Claims (6)

In an interrupt processing system in an ARM processor,
A security area section including an IRQ (Interrupt ReQuest) handler for processing an FIQ (Fast Interrupt request) interrupt,
A non-security area section including an IRQ handler for handling an IRQ interrupt, and
And a monitor module including a FIQ handler calling unit and an IRQ handler calling unit and determining whether the security area unit is under exception processing,
The FIQ handler calling unit calls an IRQ handler of the security area to process the FIQ interrupt received from the external hardware device,
The IRQ handler calls an IRQ handler in the non-security area to process the IRQ interrupt received from the external hardware device,
Wherein the monitor module deactivates the FIQ interrupt and activates the FIQ interrupt after the exception process is terminated if it is determined that the secure area is under exceptional processing. The method according to claim 1,
The FIQ handler calling unit,
And when the monitor module determines that the secure area unit is not in exception processing, calls the FIQ interrupt to be processed through the IRQ handler of the secure area unit. The method according to claim 1,
Wherein the secure area unit and the non-security area unit are managed by an operating system that is independently operated, and the operating system is Linux. A method for handling an interrupt of an ARM processor,
The FIQ (Fast Interrupt request) handler of the monitor module receives the FIQ interrupt from the external hardware device,
Determining whether the monitor module is in exception processing in the ARM processor divided into the security area section and the non-security area section including the IRQ (Interrupt ReQuest) handler,
If the ARM processor is determined to be in exception processing, the FIQ handler caller deactivates the FIQ interrupt,
Activating the deactivated FIQ interrupt after the exception handling is completed;
The FIQ handler call unit calling the IRQ handler of the secure area unit;
Wherein the IRQ handler of the secure area handles the FIQ interrupt,
Wherein the IRQ handler of the secure area handles the FIQ interrupt and the IRQ handler of the non-security area handles an IRQ interrupt. 5. The method of claim 4,
Wherein the step of determining whether the ARM processor is exception-
Wherein the FIQ handler calling unit calls the FIQ interrupt to be processed through the IRQ handler of the secure area if it is determined that the ARM processor is not under exception processing. 5. The method of claim 4,
Wherein the secure area unit and the non-security area unit are managed by an operating system that is independently operated, and the operating system is Linux.

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