KR101484210B1 - Method of abnormal circuit inspection for plc based manufacturing system - Google Patents

Abstract

The present invention relates to an abnormal circuit checking method of an automatic line which can automatically check the state of an abnormal circuit detecting an abnormal operation of an automatic line in an automatic line control using a PLC (Programmable Logic Controller) signal pattern. An abnormal state alarm method of an automation line is disclosed. Forcing the PLC input signal on / off; Detecting an output signal of the abnormal circuit according to ON / OFF of the PLC input signal; And analyzing the change of the output signal of the abnormal circuit and verifying the state of the abnormal circuit.

Description

METHOD OF ABNORMAL CIRCUIT INSPECTION FOR PLC BASED MANUFACTURING SYSTEM BACKGROUND OF THE INVENTION [0001]

An embodiment of the present invention relates to a method of checking an abnormal circuit of an automatic line, and more particularly to a method of automatically detecting an abnormal circuit of an automatic line in an automatic line control using a PLC (Programmable Logic Controller) And an abnormal circuit checking method of an automation line that can be checked.

In general, PLCs are industrial computers that are programmed in a low-level language and used to control automation systems. The PLC program, which is the internal logic of the PLC, controls the automation system through Boolean operation. According to the standard of IEC6113-3,4, Ladder Logic Diagram (LD) is known as a language commonly used in PLC programs.

Meanwhile, the PLC program designed in the general manufacturing process undergoes the verification process and controls the actual automation system when the accuracy of the program is ensured.

Recently, the automation industry has a large control logic and a very complicated design as the complexity of the manufacturing line increases. As a result, the PLC program is also complicatedly logicized.

For this reason, it is becoming increasingly difficult to diagnose and monitor PLC programs, and the time to detect and correct errors is gradually increasing.

According to Operational Diagnostics, The holy grail of control automation, this diagnostic method and work delays due to the time it takes to identify errors are shown to exceed 80% of the total plant downtime.

In particular, in the case of an automobile body assembly line, the average cycle time is about one minute, and thus, when the line is stopped due to an equipment failure, it causes a great loss of profit for a short time.

In general, automation systems consist of numerous robots and automated transport devices. The robot and the transfer device perform various operations such as welding and transfer according to the logic of the PLC program.

Recent automation systems include large-scale automated production lines, which have high complexity, and thus include various operation failure factors such as errors caused by the equipment itself or errors due to external factors such as robot movement range interference.

Delays due to failure during operation cause significant economic losses due to error detection and increased set-up time of the device.

In order to diagnose these errors, the automation system is monitored by adding the code for diagnosis inside the PLC program that controls the flow of process and logistics.

The automotive industry, which is a representative of the automation system, monitors the PLC program through an expected abnormality display module when an error occurs in the automated manufacturing line.

In the conventional monitoring method, all signals can not be monitored because a code according to the object of error diagnosis is separately prepared in anticipation of an area where errors are likely to occur.

Therefore, the process to be monitored is very limited, and there is a limit to the monitoring method for detecting the error that occurs gradually. That is, there is a problem that it is difficult to cope with the phenomenon of work failure caused by gradual wear of the apparatus or the accessories in advance.

On the other hand, the existing PLC simulation verified only the normal flow of the equipment and the process, assuming that all the abnormal circuits proceed normally. Until now, the overcurrent circuit has been checked and corrected at the actual commissioning site.

In other words, it was only possible to perform sequence check with abnormal and safety circuit (utility, emergency stop, sensor status, etc.) assumed to be normal. However, it has been difficult to properly check the abnormality of the abnormal circuit in a tight test run schedule.

In addition, more than 40% of the PLC LD (Ladder Program) defines the abnormal circuit (abnormal conditions such as hydraulic pressure, air pressure, communication, cooling water, LS (Limit Sensor), emergency stop, Is present for each line, process, and device), and it takes a lot of time to verify the abnormal circuit during actual field start-up.

In addition, since the line commissioning personnel firstly operates the line normally, it is in the form of checking the relevant part only if a problem occurs. However, potential errors in the faulty circuit are very likely to lead to a major accident.

Embodiments of the present invention seek to shorten the entire test run period and improve the PLC program quality by pre-verifying an abnormal circuit in the off-line using a PLC signal pattern.

Also, embodiments of the present invention intend to provide a preliminary verification of an abnormal circuit by forcibly generating an error by expanding the verification range through an anomaly of a PLC program and a preliminary check of a safety circuit.

According to an embodiment of the present invention, a process of forcibly turning on / off a PLC input signal; Detecting an output signal of the abnormal circuit according to ON / OFF of the PLC input signal; And analyzing whether the output signal of the abnormal circuit is changed or not and verifying the state of the abnormal circuit.

According to an embodiment of the present invention, the status verification of the abnormal circuit is divided into a single generation abnormal circuit verification and a combination abnormal circuit verification, and the combination abnormal circuit verification is performed by LS or more circuit verification using a combination of bits; A method of inspecting an abnormal circuit of an automation line including a vehicle type and an over-part circuit verification is provided.

According to the embodiment of the present invention, in the single generation abnormal circuit verification, an input bit is input as "0 " in an initial state in which an input bit value is" 1 & Determining whether an error value has changed from "0" to "1 "; Determining that an error has occurred in the abnormal circuit if the error value is not changed from "0" to "1" when the input bit is input as "0"; If the error value changes from "0" to "1 " when the input bit is input as" 0 ", it is determined that the abnormal circuit is normal and the verification is terminated.

According to the embodiment of the present invention, in the LS over-circuit verification, the input bit B value is "1", the input bit B value is "0", and the error value is "0" Quot; 1 "and the error value is changed from" 0 "to" 1 "; Determining that an error has occurred in the abnormal circuit if the error value is not changed from "0" to "1" when the input bit B value is "1"; If the error value changes from "0" to "1 " when the input bit B value is" 1 ", the abnormal circuit is determined to be normal and the verification is terminated. do.

According to the embodiment of the present invention, the vehicle type and part-anomaly circuit verification is performed in the initial state in which the input word 1 value is "A", the input word 2 value is "A", and the error value is "0" Quot; 2 " is input as "B ", and the error value is changed from" 0 " If an error value is not changed from "0" to "1 " when the input word 2 value is input as" B " And if the error value changes from "0" to "1" when the input word 2 value is input as "B", it is determined that the abnormal circuit is normal and the verification is terminated. do.

The embodiments of the present invention can discriminate the abnormality of the abnormality circuit without having to test each line on the actual line, thereby preventing an accident that may occur during trial operation and actual factory operation.

These drawings are for the purpose of describing an exemplary embodiment of the present invention, and therefore the technical idea of the present invention should not be construed as being limited to the accompanying drawings.
FIG. 1 is a diagram showing a single ideal circuit test scenario of an automation line according to an embodiment of the present invention.
FIG. 2 is a diagram showing a LS test circuit test scenario of an automation line according to an embodiment of the present invention.
3 is a diagram showing a vehicle type and part-anomaly circuit test scenarios of an automation line according to an embodiment of the present invention.
4 is an exemplary diagram illustrating a single occurrence abnormal result report of an automated line according to an embodiment of the present invention.
5 is a diagram illustrating an example of an LS generation abnormal result report of an automated line according to an embodiment of the present invention.
FIG. 6 is a view illustrating an example of a vehicle type and part occurrence abnormality result report of an automation line according to an embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings, which will be readily apparent to those skilled in the art to which the present invention pertains. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein.

1 to 6, an abnormal circuit verification system of an automation line according to an embodiment of the present invention includes an abnormal circuit verification algorithm, a result reporting system, and a simulation interworking module.

The abnormal circuit verification algorithm can check whether the abnormal circuit is properly defined by checking whether the output signal is changed by forcibly turning on / off the PLC input signal.

This can be divided into a simple Abnormal Test and a Recipe Abnormal Test. Combination error circuit test can be classified into LS Abnormal Test consisting of a combination of bits and a Recipe Abnormal Test composed of a combination of Word Bit and a part bit circuit test. And Emergency Stop Abnormal Test, which allows the operator and someone to stop the line by pressing the emergency stop button.

The single-generation abnormal circuit test outputs an error signal when the abnormal signal is turned on or off as shown in FIG. 1, which will be described later. In the case where the signal occurs independently and an abnormal situation occurs, it occurs in automatic operation condition signals and CP (Circuit Protect) related signals related to the operation of process facilities.

Signals related to automatic operation are signals such as cooling water and air pressure of a robot or a facility. These signals change the state of the signal and an error occurs when a certain time passes. These are mainly signals for the Air SW (Air Switch).

The LS (Limit Sensor) Abnormal Circuit Test is a part that defines an abnormal situation of a related signal indicating the current state of the apparatus, as shown in Fig. 2, which will be described later. The signal is the most used input signal in the assembly line, and the whole PLC program is operated through on / off state change of these signals.

In general, abnormal signals defined above LS are signals that can indicate the state of various devices such as CLAMP, LOCK, PIN, and SLIDE. The LS signal can detect ON / OFF, UP / DOWN, and ADV / RET operation status of the corresponding device.

This test outputs an error signal if none of the relevant signals indicating the current state of the device have been input or if at least one of the signals has no relation to the current state of the device.

As shown in FIG. 3, which will be described later, the vehicle type and part abnormal circuit test are performed by combining the vehicle type information and the part sensor signal with the Word Bit value to check whether the corresponding vehicle type and the part sensor are matched, .

For example, the body assembly line adopts a mixed production system that produces several models together in one production line. In the actual assembly line, the vehicle information signal differs depending on the vehicle option and vehicle type, and the position and the number of the part detecting sensors for detecting the corresponding parts are also different.

For this reason, one facility takes different actions depending on each vehicle type. Therefore, it is necessary to confirm the vehicle type information and the part detection sensor for the process operation. Verifying the abnormal situation of these signals is the vehicle type and the circuit verification test.

Emergency Stop Abnormal circuit verification can be done by inputting this signal suddenly during sequence verification in order to check that the automatic operation is turned off and the line stops correctly.

Emergency stop is an abnormal situation signal generated by the field worker in addition to equipment, vehicle type, and part information. This is the case where an operator stops the process arbitrarily due to an unexpected situation during a normal process, and the operator can press the EM STOP button to force the line to stop.

At this time, if the EM STOP button is pressed, the automatic operation signal of the production line is turned off and all facilities must stop operating. The part defined to confirm this is the emergency stop abnormal circuit verification scenario.

As shown in FIGS. 4 to 6, the result report system should be able to express the final verification result in a report format. Report format can be divided into All Change type, Part Change type and Not Change type.

The classification preconditions of these formats are that the input signal to be verified and the output signal correlated with the input signal are correlated in the ideal circuit verification scenario, and the error signals correlated with the output signal are also combined have.

Based on these preconditions, the All Change type can be defined as the case where the corresponding input signal is forcibly turned on / off in the ideal circuit test and the expected output signal becomes On (Change).

In this case, the output signal state change during abnormal circuit test in the report can be identified as Change or Not Change, and can be analyzed visually.

If output signals and error signals that are not expected to occur in this report analysis process are turned on, errors in the PLC LD (Ladder Program) can be checked and corrected.

The Not Change type is defined as when the expected output signal and error signal are not On (Change) in contrast to All Change format.

In this case, it is also possible to check change of output signal status during abnormal circuit test by Change or Not Change in Report, and if output signal and error signals expected in report analysis are on, this also causes error in PLC LD (Ladder Program) You can check and fix it.

Finally, the Part Change format is defined as when a certain part of the expected output signal is changed (On). It is important to note that the output signal and error signals expected in the report analysis process should be changed to On (Change) and that the Off (Not_Change) should occur correctly.

If the on / off change of the signals is executed correctly in the report analysis process, it can be analyzed as a normal program in which there is no error in the PLC LD, but the PLC code analyzed as error is corrected and the completeness .

The above-mentioned abnormal circuit verification system can be created by linking with PLC simulation, and a simulation platform that can verify the PLC program of the virtual factory or virtual facility construction technology, plant or equipment corresponding to the actual site situation for the off-line test environment .

Then, it is checked whether or not the faulty circuit is stable by using the forced generation of the artificial process signal and the data intercept technique (Fault Injection: forced arbitrary error injection) in the virtual factory (facility) Use the Dynamic Test technique.

It also uses an automated regression testing technique that is iterative of regression testing for post-correction impact assessment and reduces time and human resource consumption.

1 is an example of a single ideal circuit test scenario for explaining a method of alarming an abnormal state of an automated line using a PLC signal pattern according to an embodiment of the present invention. , And the Error value is 0 (A1).

Subsequently, the input bit value is forcibly injected to 0 (A2), and it is determined whether the error value changes from the initial state 0 to 1 as a result of forcibly injecting the signal in the step (A2) (A3).

If it is judged to be false in the step (A3), the error can be confirmed in the abnormal situation test, and the regression test is performed by modifying the PLC program (A4).

If it is determined in the step (A3), the detection of the error signal for the input signal can be confirmed in the abnormal situation test and the test is finished (A5).

On the other hand, FIG. 2 is an LS or more circuit test scenario for explaining an abnormal state alarm method of an automated line using a PLC signal pattern according to an embodiment of the present invention. The Bit A value is 1, the Input Bit B value is 0, and the Error value is 0 (C1).

Thereafter, the input bit B value is forcibly injected at 1 (C2), and it is determined whether the error value changes from the initial state 0 to 1 (C3) as a result of forcibly injecting the signal in the step (C2).

If it is judged to be false in the step (C3), the error can be confirmed in the abnormal situation test, and the regression test is performed by modifying the PLC program (C4).

If it is determined in step (C3), the detection of the error signal for the input signal can be confirmed in the abnormal condition test (step C5).

FIG. 3 is a vehicle type and part abnormal circuit test scenario for explaining an abnormal state alarm method of an automated line using a PLC signal pattern according to an embodiment of the present invention. As an initial state in the combined vehicle type abnormal circuit test, The value is A, Input Word 2 is A, and Error is 0 (B1).

Thereafter, the value of Input Word 2 is forcibly injected into B (B2), and it is determined whether the error value changes from the initial state 0 to 1 as a result of forcibly injecting the signal in the step (B2) (B3).

If it is judged to be false in the step (B3), the error can be confirmed in the abnormal situation test, and the regression test is performed by modifying the PLC program (B4).

If it is determined in the step (B3), the detection of the error signal for the input signal can be confirmed in the abnormal condition test and the test is finished (B5).

<Examples>

The embodiment of the present invention is based on simulations of a virtual factory (facility) construction and a control program (PLC). The TEST CASE used in the test method is described as a single abnormal TEST CASE, LS TEST CASE, vehicle type and part TEST CASE according to the classification criteria of the abnormal circuit, and XML-based storable data format Respectively.

Among the dynamic testing methods based on the TEST CASE described above, the basis for smoothly supporting the regression testing corresponding to the black box testing technique is provided. Changes made during PLC program modification and maintenance will be used for checking to ensure that the abnormal circuit requirements specification is still met.

The Fault Injection test method is basically used to confirm the operation by injecting an arbitrary error into the corresponding symbols causing the cause of the PLC fault circuit. The value for causing the error is basically supported by the Boolean type of PLC symbols do.

Also, user input values are supported so that the input range test of the parameters can be performed so that the corresponding scenarios can be defined for verification of vehicle type and part abnormality.

This technique identifies all error messages and exceptions that occur on the basis of the Exception Testing technique in the black box test of the dynamic test method, as well as the conditions that trigger those results, TEST CASE is selected and tested.

In the embodiment of the present invention, by applying the single-phase abnormality and the emergency stop technique, the signals corresponding to the cause of the single abnormality in the PLC circuit are modeled by the input symbol of the I / O model, You can create a TEST CASE by selecting the Device object of the I / O model created in this form.

If LS is applied above, test with the scenario shown in Fig. Also check for changes in the Input Symbol that are in the state of the Input Symbols that are currently being tested and that are different from the current state in the current state.

When a vehicle type and a part are applied, a set of input symbols that define it is subjected to error injection, and a test case is created based on the I / O model and tested in the scenario shown in FIG.

While the single LS-related anomaly described above can be said to be a verification of connected anomalous circuits with respect to an independent signal, the vehicle / part anomaly is defined as a set of symbol values, The verification complexity is inherent in the fact that the condition for satisfying the condition must be preceded.

The abnormal circuit verification step and the contents of the abnormality modeling are performed by connecting the abnormality occurrence data and confirmation symbols using the I / O modeling data in the step 1 and 2 after the existing steps.

In the fourth step, when the simulation is performed, the abnormality modeling is generated, the result of the process is confirmed, and the abnormal circuit is verified.

The above 4 steps are utilized for single or more TEST CASE production user interface, LS or more TEST CASE user interface, vehicle type and part TEST CASE user interface, single or more TEST CASE user interface to input abnormal conditions, After the input output matching, test environment setting, and so on, the test starts.

LS Abnormal occurrence TEST CASE User interface starts the test after checking abnormal output and setting of test environment setting. Vehicle type and part abnormal TEST CASE The user interface starts the test after setting the vehicle type condition, part detection input, matching, abnormal output setting, test environment setting.

In the fifth step, the verification results are confirmed visually through signal charts generated in addition to the results obtained from the abnormal circuit verification. 5 is shown as in Fig. 4 (single occurrence abnormal result example report), Fig. 5 (LS occurrence abnormal result example report), and Fig. 6 (vehicle type and part occurrence abnormal result example report). Abnormal circuit trouble signal report is displayed in red, abnormal circuit normal signal report is displayed in green.

According to the abnormal state alarm method of the automated line using the PLC signal pattern according to the embodiment of the present invention as described above, the standard I / O model technique for the abnormal circuit verification and the easy abnormal situation test modeling tool .

Therefore, in the embodiment of the present invention, it is possible to derive an automation verification module for an abnormal situation in the PLC simulation with the test data created using the above-described tool, and to derive a visual reporting tool to easily read the verification result have.

In other words, in the embodiment of the present invention, it is checked whether or not the output signal is changed by forcibly turning ON / OFF the signal related to the abnormal circuit of the PLC program and verifying whether the abnormal circuit works properly. , LS or more circuit that can test the LS defined in each facility, vehicle type and part over circuit that can test the vehicle type and part sensor related signals, and the worker and someone to push the emergency stop button And emergency stop test that can stop the line by pushing it.

In the embodiment of the present invention, it is necessary to be able to express the final verification result in the form of a signal time chart. For the off-line test environment, a control program of a virtual factory, a virtual facility construction technique, Based on the control program simulation platform, it is possible to generate faulty data by using the artificial process signal force generation and the data interception technique on the sequential flow (Fault Injection: forced arbitrary error injection) in the virtual factory (facility) Use the Dynamic Test technique to check the stability of the circuit.

Also, in the embodiment of the present invention, an automatic regression test technique is used to reduce the repetition of the regression testing for the post-correction influence evaluation and to reduce the time and human resources consumption.

A method of alarming an abnormal state of an automated line using a PLC signal pattern according to an embodiment of the present invention based on the technical contents as described above includes the steps of generating a cycle according to an operation of an internal logic of a PLC (Programmable Logic Controller) A plurality of PLC signals are transmitted and received between a PLC and an automation line in units of a plurality of PLC signals, and a plurality of cycles are repeated in a normal driving state in which an automation line is sequentially controlled, a plurality of sequences are acquired.

In the embodiment of the present invention, a reference sequence indicating a change order among a plurality of PLC signals used for controlling an automation line in a normal driving state is obtained by using the plurality of change sequences.

In this process, each of the plurality of change sequences is arranged on the time axis, and a reference sequence is obtained by extracting only the common part from each other.

Then, in the embodiment of the present invention, it is checked whether or not the reference sequence and the reference sequence are matched with the sequence of change between a plurality of PLC signals used for control of the automated line driven, Identify abnormal output and output.

In the above process, a time interval between a plurality of PLC signals forming a reference sequence and a time interval between a plurality of PLC signals forming a change sequence between PLC signals used for controlling an automation line driven after the reference sequence is obtained It is further confirmed whether or not the automation line is in a normal or abnormal state.

The time interval between the plurality of PLC signals forming the reference sequence may be determined by arranging a plurality of PLC signals forming each of the plurality of change sequences in accordance with a time sequence, &Lt; / RTI &gt;

The time interval between the plurality of PLC signals forming the reference sequence may be determined by arranging a plurality of PLC signals forming each of a plurality of change sequences in accordance with a time sequence, extracting only a common portion between the PLC signals, The allowable time set by the user may be added.

Thus, in the embodiment of the present invention, it is possible to discriminate the abnormality of the abnormal circuit without testing the actual line, so that it is possible to prevent an accident that may occur during trial operation and actual factory operation.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, Other embodiments may easily be suggested by adding, changing, deleting, adding, or the like of elements, but this also falls within the scope of the present invention.

Claims (5)

delete delete Forcing the PLC input signal on / off;
Detecting an output signal of the abnormal circuit according to ON / OFF of the PLC input signal;
And checking the state of the abnormal circuit by analyzing whether the output signal of the abnormal circuit is changed or not,
The state verification of the abnormal circuit is divided into a single generation abnormal circuit verification and a combination abnormal circuit verification,
The above-mentioned combination abnormal circuit verification is a LS or more circuit verification made up of a combination of bits;
Word bit combinations and part-to-part circuit verification,
Wherein the single generation abnormal circuit verification comprises:
A process of inputting an input bit at "0" in an initial state where an input bit value is "1" and an error value is "0", and determining whether an error value changes from "0" to "1";
Determining that an error has occurred in the abnormal circuit if the error value is not changed from "0" to "1" when the input bit is input as "0";
If the error value changes from "0" to "1" when the input bit is input as "0", it is determined that the abnormal circuit is normal and the verification is terminated;
The method comprising the steps of: Forcing the PLC input signal on / off;
Detecting an output signal of the abnormal circuit according to ON / OFF of the PLC input signal;
And checking the state of the abnormal circuit by analyzing whether the output signal of the abnormal circuit is changed or not,
The state verification of the abnormal circuit is divided into a single generation abnormal circuit verification and a combination abnormal circuit verification,
The above-mentioned combination abnormal circuit verification is a LS or more circuit verification made up of a combination of bits;
Word bit combinations and part-to-part circuit verification,
The LS or more circuit verification may be performed,
Input bit B is set to "1" in the initial state where input bit A value is "1", input bit B value is "0" and error value is "0"Quot; 1 "
Determining that an error has occurred in the abnormal circuit if the error value is not changed from "0" to "1" when the input bit B value is "1";
If the error value changes from "0" to "1" when the input bit B value is "1", it is determined that the abnormal circuit is normal and the verification is terminated;
The method comprising the steps of: Forcing the PLC input signal on / off;
Detecting an output signal of the abnormal circuit according to ON / OFF of the PLC input signal;
And checking the state of the abnormal circuit by analyzing whether the output signal of the abnormal circuit is changed or not,
The state verification of the abnormal circuit is divided into a single generation abnormal circuit verification and a combination abnormal circuit verification,
The above-mentioned combination abnormal circuit verification is a LS or more circuit verification made up of a combination of bits;
Word bit combinations and part-to-part circuit verification,
The above vehicle type and part-
Input word 2 value is input as "B" in the initial state where input word 1 value is "A", input word 2 value is "A" and error value is "0"Quot; 1 "
If an error value is not changed from "0" to "1 " when the input word 2 value is input as" B "
If the value of the input word 2 is changed from "0" to " 1 " when the value of the input word 2 is input as "B "
The method comprising the steps of:

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