KR101466205B1 - 전기 회로, 디지털 뉴럴 프로세싱 유닛을 구현하기 위한 방법 및 장치 - Google Patents
전기 회로, 디지털 뉴럴 프로세싱 유닛을 구현하기 위한 방법 및 장치 Download PDFInfo
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- KR101466205B1 KR101466205B1 KR1020137003040A KR20137003040A KR101466205B1 KR 101466205 B1 KR101466205 B1 KR 101466205B1 KR 1020137003040 A KR1020137003040 A KR 1020137003040A KR 20137003040 A KR20137003040 A KR 20137003040A KR 101466205 B1 KR101466205 B1 KR 101466205B1
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N3/00—Computing arrangements based on biological models
- G06N3/02—Neural networks
- G06N3/04—Architecture, e.g. interconnection topology
- G06N3/049—Temporal neural networks, e.g. delay elements, oscillating neurons or pulsed inputs
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N3/00—Computing arrangements based on biological models
- G06N3/02—Neural networks
- G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
- G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N3/00—Computing arrangements based on biological models
- G06N3/02—Neural networks
- G06N3/04—Architecture, e.g. interconnection topology
- G06N3/047—Probabilistic or stochastic networks
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N3/00—Computing arrangements based on biological models
- G06N3/02—Neural networks
- G06N3/04—Architecture, e.g. interconnection topology
- G06N3/0495—Quantised networks; Sparse networks; Compressed networks
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N3/00—Computing arrangements based on biological models
- G06N3/02—Neural networks
- G06N3/04—Architecture, e.g. interconnection topology
- G06N3/0499—Feedforward networks
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N3/00—Computing arrangements based on biological models
- G06N3/02—Neural networks
- G06N3/08—Learning methods
- G06N3/088—Non-supervised learning, e.g. competitive learning
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Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US12/831,871 US9129220B2 (en) | 2010-07-07 | 2010-07-07 | Methods and systems for digital neural processing with discrete-level synapes and probabilistic STDP |
| US12/831,871 | 2010-07-07 | ||
| PCT/US2011/043259 WO2012054109A1 (en) | 2010-07-07 | 2011-07-07 | Methods and systems for digital neural processing with discrete-level synapses and probabilistic stdp |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20130036313A KR20130036313A (ko) | 2013-04-11 |
| KR101466205B1 true KR101466205B1 (ko) | 2014-11-27 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020137003040A Expired - Fee Related KR101466205B1 (ko) | 2010-07-07 | 2011-07-07 | 전기 회로, 디지털 뉴럴 프로세싱 유닛을 구현하기 위한 방법 및 장치 |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US9129220B2 (enExample) |
| EP (1) | EP2591452A1 (enExample) |
| JP (1) | JP5680751B2 (enExample) |
| KR (1) | KR101466205B1 (enExample) |
| CN (1) | CN102959566B (enExample) |
| TW (1) | TW201209735A (enExample) |
| WO (1) | WO2012054109A1 (enExample) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11250320B2 (en) | 2017-05-25 | 2022-02-15 | Samsung Electronics Co., Ltd. | Neural network method and apparatus |
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| WO2009113993A1 (en) | 2008-03-14 | 2009-09-17 | Hewlett-Packard Development Company, L.P. | Neuromorphic circuit |
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2010
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2011
- 2011-07-07 TW TW100124090A patent/TW201209735A/zh unknown
- 2011-07-07 EP EP11817445.7A patent/EP2591452A1/en not_active Withdrawn
- 2011-07-07 KR KR1020137003040A patent/KR101466205B1/ko not_active Expired - Fee Related
- 2011-07-07 WO PCT/US2011/043259 patent/WO2012054109A1/en not_active Ceased
- 2011-07-07 JP JP2013518844A patent/JP5680751B2/ja not_active Expired - Fee Related
- 2011-07-07 CN CN201180031038.XA patent/CN102959566B/zh not_active Expired - Fee Related
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2009113993A1 (en) | 2008-03-14 | 2009-09-17 | Hewlett-Packard Development Company, L.P. | Neuromorphic circuit |
Non-Patent Citations (4)
| Title |
|---|
| Bernhard Nessler et al. STDP enables spiking neurons to detect hidden causes of their inputs. NIPS 2009, Vancouver, Canada, 2009. 12. 7-10. * |
| Bernhard Nessler et al. STDP enables spiking neurons to detect hidden causes of their inputs. NIPS 2009, Vancouver, Canada, 2009. 12. 7-10.* |
| Terry Elliott. Discrete States of Synaptic Strength in a Stochastic Model of Spike-Timing-Dependent Plasticity. Neural Computation, Vol.22, No.1, pp.244-272, 2009.12.11. * |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11250320B2 (en) | 2017-05-25 | 2022-02-15 | Samsung Electronics Co., Ltd. | Neural network method and apparatus |
| US12511535B2 (en) | 2017-05-25 | 2025-12-30 | Samsung Electronics Co., Ltd. | Neural network method and apparatus |
Also Published As
| Publication number | Publication date |
|---|---|
| EP2591452A1 (en) | 2013-05-15 |
| WO2012054109A1 (en) | 2012-04-26 |
| KR20130036313A (ko) | 2013-04-11 |
| CN102959566A (zh) | 2013-03-06 |
| CN102959566B (zh) | 2016-04-27 |
| JP5680751B2 (ja) | 2015-03-04 |
| TW201209735A (en) | 2012-03-01 |
| US9129220B2 (en) | 2015-09-08 |
| JP2013534018A (ja) | 2013-08-29 |
| US20120011093A1 (en) | 2012-01-12 |
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