KR101442176B1 - Semiconductor device with reduced thickness, electronic products employing the same, and method of fabricating the same - Google Patents

Semiconductor device with reduced thickness, electronic products employing the same, and method of fabricating the same Download PDF

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KR101442176B1
KR101442176B1 KR20080083457A KR20080083457A KR101442176B1 KR 101442176 B1 KR101442176 B1 KR 101442176B1 KR 20080083457 A KR20080083457 A KR 20080083457A KR 20080083457 A KR20080083457 A KR 20080083457A KR 101442176 B1 KR101442176 B1 KR 101442176B1
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Prior art keywords
pattern
gate
conductive
cell
region
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KR20080083457A
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Korean (ko)
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KR20090029637A (en
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김대익
김용일
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삼성전자주식회사
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Priority to KR1020070094725 priority
Application filed by 삼성전자주식회사 filed Critical 삼성전자주식회사
Priority claimed from DE102008047591.2A external-priority patent/DE102008047591B4/en
Publication of KR20090029637A publication Critical patent/KR20090029637A/en
Priority claimed from US12/662,150 external-priority patent/US8120123B2/en
Publication of KR101442176B1 publication Critical patent/KR101442176B1/en
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Abstract

There is provided a semiconductor device having a reduced thickness, an electronic product employing the same, and a manufacturing method thereof. This method of manufacturing a semiconductor device includes preparing a semiconductor substrate having first and second active regions. A first transistor including a first gate pattern traversing the first active region and first impurity regions in the first active region on either side of the first gate pattern. A second transistor including a second gate pattern traversing the second active region and second impurity regions in the second active region on either side of the second gate pattern. During the formation of the second transistor, a first conductive pattern is formed on the first transistor.

Description

TECHNICAL FIELD [0001] The present invention relates to a semiconductor device having a reduced thickness, an electronic product employing the reduced thickness, and a method of fabricating the same.
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and an electronic product employing the same, and more particularly, to a semiconductor device with reduced thickness, an electronic product employing the same, and a manufacturing method thereof.
2. Description of the Related Art In recent years, studies have been made actively to reduce the size of elements constituting semiconductor chips while reducing the size of semiconductor chips used in electronic products and requiring low power consumption.
SUMMARY OF THE INVENTION The present invention provides a structure of a semiconductor device capable of reducing a thickness and an electronic product adopting the structure.
Another object of the present invention is to provide a method of manufacturing a semiconductor device capable of reducing a thickness.
According to one aspect of the present invention, there is provided a semiconductor device capable of reducing the thickness. The semiconductor device includes a semiconductor substrate having first and second active regions. A first transistor formed in the first active region of the semiconductor substrate is provided. The first transistor includes first impurity regions and a first gate pattern. And a second transistor formed in the second active region of the semiconductor substrate. The second transistor includes second impurity regions and a second gate pattern. And a first conductive pattern on the first transistor. At least a portion of the first conductive pattern is located at the same level as at least a portion of the second gate pattern.
In some embodiments of the present invention, the first transistor comprises: the first gate pattern of conductive conductivity provided in a gate trench transverse to the first active region; The first impurity regions in the first active region on both sides of the first gate pattern; And a first gate dielectric layer between the first gate pattern and the gate trench.
Still further, the device may further include a first gate capping pattern that is insulating and fills the gate trench with the first gate pattern. The first gate capping pattern may have a protruding portion having a higher level than the first active region.
In yet another embodiment, the first contact structure may further include a first contact structure for electrically connecting one of the first impurity regions and the first conductive pattern.
In yet another embodiment, the second transistor comprises: the second gate pattern across the second active region; A second gate dielectric layer between the second gate pattern and the active region; And the second impurity regions in the second active region on either side of the second gate pattern. Here, the second gate pattern may include a first gate electrode and a second gate electrode which are sequentially stacked, and the second gate electrode may be located at substantially the same level as the first conductive pattern.
In another embodiment, a cell contact structure electrically connected to one of the first impurity regions; And an information storage element on the cell contact structure.
The information storage element may be located at a higher level than the first conductive pattern.
And a conductive buffer pattern between the cell contact structure and the information storage element.
The information storage element may include one of an information storage material layer of a volatile memory element and an information storage material layer of a nonvolatile memory element.
A second conductive pattern located at a level higher than the first conductive pattern; And a second contact structure electrically connecting one of the second impurity regions to the second conductive pattern.
Meanwhile, the cell contact structure and the second contact structure may have upper surfaces positioned at different levels. Alternatively, the cell contact structure and the second contact structure may have upper surfaces positioned at the same level with each other.
And a connection structure for electrically connecting the first and second conductive patterns.
According to another aspect of the present invention, there is provided an electronic product including a semiconductor chip. The semiconductor chip of the electronic product includes a semiconductor substrate having a cell array region and a peripheral circuit region. A cell transistor formed on the semiconductor substrate of the cell array region and including first impurity regions and a first gate pattern is provided. A peripheral transistor including a first peripheral gate electrode and a second peripheral gate electrode which are formed on the semiconductor substrate of the peripheral circuit region and are sequentially stacked on the substrate between the second impurity regions and the second impurity regions do. There is provided a cell bit line formed on the cell transistor of the cell array region and having at least a part located at the same level as at least a part of the second peripheral gate electrode.
According to still another aspect of the present invention, there is provided a method of manufacturing a semiconductor device capable of reducing a thickness. The method includes preparing a semiconductor substrate having first and second active regions. A first transistor including a first gate pattern traversing the first active region and first impurity regions in the first active region on either side of the first gate pattern. A second transistor including a second gate pattern traversing the second active region and second impurity regions in the second active region on either side of the second gate pattern. During formation of the second gate pattern, a first conductive pattern is formed on the first transistor.
In some embodiments of the present invention, forming the first and second transistors and the first conductive pattern comprises forming the first impurity regions within the first active region, Forming a gate trench, forming the first gate pattern filling at least a portion of the gate trench, forming a gate conductive pattern on the second active region, forming a buffer insulation pattern on the first active region And forming a first conductive film covering the buffer insulating pattern and the gate conductive pattern, the first conductive film on the buffer insulating pattern, and the gate conductive pattern sequentially stacked on the second active region, The first conductive pattern is formed on the buffer insulating pattern, and the first conductive pattern is formed on the second active region, And the pole may include forming the second gate electrode.
Further comprising forming a first gate capping pattern to fill the gate trench with the first gate pattern on the first gate pattern after forming the first gate pattern, The pattern may have a protrusion higher in level than the first active area.
On the other hand, the buffer insulating pattern can be formed after the gate conductive pattern is formed. Alternatively, the gate conductive pattern may be formed after forming the buffer insulating pattern.
Further comprising forming a first contact structure through the buffer insulation pattern and electrically connected to one of the first impurity regions before forming the first conductive pattern, 1 < / RTI > conductive pattern.
In another embodiment, a first interlayer insulating film is formed on a substrate having the first conductive pattern, a cell contact structure electrically connected to one of the first impurity regions is formed through the first interlayer insulating film , And forming an information storage element on the cell contact structure.
Forming a peripheral contact structure which is electrically connected to one of the second impurity regions through the first interlayer insulating film while the cell contact structure is formed; and forming a peripheral contact structure electrically connected to the peripheral contact structure on the first interlayer insulating film To form a second conductive pattern connected to the second conductive pattern.
And forming a buffer pattern electrically connected to the cell contact structure on the first interlayer insulating layer while forming the second conductive pattern.
A second interlayer insulating film is formed on the first interlayer insulating film and a second contact structure electrically connected to one of the second impurity regions is formed through the first and second interlayer insulating films, And forming a second conductive pattern on the two-layer insulating film.
According to still another aspect of the present invention, there is provided a method of manufacturing a semiconductor device. The method includes preparing a semiconductor substrate having first and second regions. And an insulating pattern is formed on the semiconductor substrate of the first region. And a conductive pattern is formed on the semiconductor substrate of the second region. Thereby forming a conductive film covering the conductive pattern and the insulating pattern. The conductive film and the conductive pattern are patterned to form a wiring on the insulating pattern and a first gate electrode and a second gate electrode which are sequentially stacked on the semiconductor substrate of the second region are formed.
According to the embodiments of the present invention, a wiring such as a cell bit line can be formed in the cell array region while forming the first gate electrode and the second gate electrode which are sequentially stacked in the peripheral circuit region. Thus, the wiring may be located at substantially the same level as the second gate electrode of the peripheral circuit region. As a result, the overall thickness of the device can be reduced.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. However, the present invention is not limited to the embodiments described herein but may be embodied in other forms. Rather, the embodiments disclosed herein are provided so that the disclosure can be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the thicknesses of the layers and regions are exaggerated for clarity. Also, when a layer is referred to as being "on" another layer or substrate, it may be formed directly on another layer or substrate, or a third layer may be interposed therebetween. Like numbers refer to like elements throughout the specification.
FIG. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention, and FIG. 2 is a cross-sectional view illustrating a semiconductor device according to another embodiment of the present invention.
First, the structure of a semiconductor device according to an embodiment of the present invention will be described with reference to FIG.
Referring to FIG. 1, a semiconductor substrate 500 having a first region A, a second region A2, and an intermediate region B may be provided. The semiconductor substrate 500 may be a semiconductor wafer including a semiconductor material such as silicon. The first region A1 may be a memory cell array region, and the second region A2 may be a peripheral circuit region. The intermediate region B may be a predetermined region between a first element on the first region A1, for example, a cell transistor, and a second element on the second region A2, for example, a peripheral transistor.
The intermediate region B may be a predetermined region between a first element on the first region A1, for example, a cell transistor, and a second element on the second region A2, for example, a peripheral transistor. Therefore, in the drawing of this embodiment, the intermediate region B is shown as an independent region between the first region A1 and the second region A2, but this is not for convenience of explanation. For example, the intermediate region B may be located in a first region A1, such as a memory cell array region, or may be located in a second region A2, such as a peripheral circuit region.
The semiconductor substrate 500 may be provided with an element isolation region 503s which defines the active regions 503a and 503b. The device isolation region 503s may be a trench isolation film. The device isolation region 503s defines a first active region, for example, a cell active region 503a in the first region A1 and a second active region in the second region A2, for example, The peripheral active region 503b can be defined.
A first transistor AT1 may be provided in the first active region 503a. The first transistor AT1 includes first impurity regions 518a and 518b in the first active region 503a, a first channel region between the first impurity regions 518a and 518b, And may include a first gate dielectric layer 521 and a first gate pattern 524 which are sequentially stacked on the region. The first gate pattern 524 may be a cell gate electrode. The first gate pattern 524 may be provided in a gate trench 515 which intersects the first active region 503a. For example, the first gate pattern 524 may partially fill the gate trench 515. Then, a first gate capping pattern 527 filling the remaining portion of the gate trench 515 may be provided. The first gate capping pattern 527 may be formed of an insulating material layer.
The gate trench 515 may extend through the first active region 503a and into the trench isolation region 503s. Therefore, the first gate pattern 524 may also extend to the element isolation region 503s across the first active region 503a. The first gate dielectric layer 521 may be interposed between the inner wall of the gate trench 515 and the first gate pattern 514. The first impurity regions 518a and 518b may be provided in the upper regions of the first active region 503a on both sides of the gate trench 515. [ Accordingly, the first transistor AT1 may have a recess channel.
A second transistor AT2 may be provided in the second active region 503b. The second transistor AT2 is connected between the second impurity regions 548a and 548b in the second active region 503b, the second channel region between the second impurity regions 548a and 548b, A second gate dielectric layer 506a and a second gate pattern 540 that are sequentially stacked on the channel region. The second gate pattern 540 may include a lower gate electrode 509g and an upper gate electrode 539g which are sequentially stacked. An insulating second gate capping pattern 542g may be provided on the second gate pattern 540.
A buffer insulating pattern 536 may be provided on the substrate of the first area A1 and the middle area B to cover the first transistor AT1 and the first gate capping pattern 527. [ A first conductive pattern 539a is provided on the buffer insulating pattern 536. [ The first conductive pattern 539a may have a line shape. The first conductive pattern 539a may be defined as a cell bit line. At least a portion of the first conductive pattern 539a may be located at the same level as at least a portion of the second gate pattern 540. For example, at least a portion of the first conductive pattern 539a may be at the same level as at least a portion of the top gate electrode 539g. The first conductive pattern 539a may include the same conductive material film formed by the same process as the upper gate electrode 539g. The first conductive pattern 539a may be located at substantially the same level as the upper gate electrode 539g.
A first contact structure 538p for electrically connecting one of the first impurity regions 518a and 518b to the first conductive pattern 539a may be provided. The first contact structure 538p may penetrate the buffer insulation pattern 536. [
In some embodiments of the present invention, the upper gate electrode 539g may be made of a conductive material having a higher electrical conductivity than the lower gate electrode 509g. For example, the lower gate electrode 509g may include a doped polysilicon film, and the upper gate electrode 539g may include a metal material film such as a tungsten film. A metal silicide film may be interposed between the upper gate electrode 539g and the lower gate electrode 509g in consideration of an ohmic contact characteristic between the polysilicon film and the metal material film.
In another embodiment, the upper gate electrode 539g and the lower gate electrode 509g may be made of the same conductive material.
A first insulating capping pattern 542a may be provided on the first conductive pattern 539a. A first insulative spacer 545a may be provided on the sidewalls of the first conductive pattern 539a and the first insulative capping pattern 542a. A second insulative spacer 545g may be provided on the sidewalls of the second gate pattern 540 and the second gate capping pattern 542g. The first and second insulating spacers 545a and 545g may include the same insulating material film formed by the same process.
A first interlayer insulating film 551 covering the entire surface of the substrate of the first and second regions A1 and A2 and the intermediate region B may be provided. The first interlayer insulating layer 551 may have a flat upper surface located at a higher level than the first insulating capping pattern 542a and the second gate capping pattern 542g. Alternatively, the first interlayer insulating film 551 may have a flat upper surface located at substantially the same level as the first insulating capping pattern 542a and the second gate capping pattern 542g. A second interlayer insulating film 584 may be provided on the first interlayer insulating film 551.
A second conductive pattern 575 may be provided on the second interlayer insulating film 584.
A conductive connection structure 572a for electrically connecting the first and second conductive patterns 539a and 575 may be provided. The connection structure 572a may be interposed between the first and second conductive patterns 539a and 575 to pass through the second interlayer insulating layer 584 and the first insulating capping pattern 542a in order.
The second conductive pattern 575 is interposed between one of the second impurity regions 548a and 548b and the second conductive pattern 575 to electrically connect the region 548a and the second conductive pattern 575 A second contact structure 572b may be provided. The second contact structure 572b may include a lower contact structure 571a penetrating the first interlayer insulating layer 551 and an upper contact structure 571b penetrating the second interlayer insulating layer 584. [ The lower contact structure 571a and the upper contact structure 571b may be formed of conductive material layers formed by different processes. Alternatively, the lower contact structure 571a and the upper contact structure 571b may be formed of the same material layer formed by the same process.
The first interlayer insulating film 551 and the buffer insulating pattern 536 are electrically connected to one region 518b of the first impurity regions 518a and 518b in the first region A1, A cell contact structure 560 may be provided. That is, the first contact structure 538p is electrically connected to one region 518a of the first impurity regions 518a and 518b, and the cell contact structure 560 is electrically connected to the first impurity regions 518a, and 518b, respectively.
An information storage element 597 may be provided on the cell contact structure 560. The information storage element 597 may include first and second electrodes and an information storage material layer between the first and second electrodes. The information storage element 597 may be located at a higher level than the first conductive pattern 539a. At least a portion of the information storage element 597 may be located at the same or lower level as the second conductive pattern 575.
The information storage element 597 may include an information storage material layer of a volatile memory device, such as a DRAM, for example, a capacitor dielectric layer. However, it is not limited thereto. For example, the information storage element 597 may include an information storage material layer of a non-volatile memory device such as a ferroelectric material layer of an FeRAM or a material layer of a PRAM.
According to the present embodiment, since the distance between the information storage element 597 and the first transistor AT1 can be minimized, the overall thickness of the semiconductor device can be minimized. In other words, the first conductive pattern 539a, that is, the cell bit line, between the information storage element 597 and the first transistor AT1 is electrically connected to the second region A2, It is possible to minimize the distance between the cell bit line 539a and the first active region 503a as well as to minimize the distance between the information storage element 597 and the first active region 503a, 1 < / RTI > active areas 503a can be minimized. Therefore, not only the overall thickness of the semiconductor device can be minimized, but also a process margin for forming the cell contact structure 560 between the information storage liner 597 and the first active region 503a can be minimized. Can be increased.
Next, a semiconductor device according to another embodiment of the present invention will be described with reference to FIG.
Referring to FIG. 2, the first and second regions D1 and D2 and the intermediate region E corresponding to the first and second regions A1 and A2 and the intermediate region B of FIG. May be provided. The first transistor AT1 and the second transistor AT2 corresponding to the first and second active regions 503a and 503b, the element isolation region 503s, the first transistor AT1 and the second transistor AT2 in the embodiment of FIG. The first and second active regions 603a and 603b, the element isolation region 603s, the first transistor DT1, and the second transistor DT2 may be provided. The first transistor DT1 is connected to the first impurity regions 518a and 518b, the first gate dielectric layer 521, and the first gate pattern 524 of the first transistor AT1 of FIG. 618b, a first gate dielectric layer 621, and a first gate pattern 624, each of which corresponds to a first gate dielectric layer 618a, 618b, respectively. Also, the first gate pattern 624 may be provided in the gate trench 615 corresponding to the gate trench 515 of FIG. The second transistor DT2 is connected to the second impurity regions 548a and 548b of the second transistor AT2 in FIG. 1, the second gate dielectric layer 506a, and the second gate pattern 540, respectively The second gate dielectric layer 606a, and the second gate pattern 640. The second gate dielectric layer 606a may include a first gate dielectric layer 608a, a second gate dielectric layer 606a, The second gate pattern 640 may include a lower gate electrode 609g and an upper gate electrode 639g which are sequentially stacked. (603a) that fills the remaining portion of the gate trench (615) on the first gate pattern (624) of the first transistor (DT1) and is located at a level higher than the top surface of the first active region A first gate capping pattern 627 having a protruding portion may be provided. The first gate capping pattern 627 may be formed of an insulating material layer.
A buffer insulating pattern 636 covering the element isolation region 603s and the first impurity regions 618a and 618b may be provided on the substrate of the first region D1 and the intermediate region E . The buffer insulating pattern 636 may be formed of an insulating material layer having an etch selectivity with respect to the first gate capping pattern 627. For example, in the case where the first gate capping pattern 627 includes a silicon nitride film, the buffer insulating pattern 636 may include a silicon oxide film.
The first conductive pattern 639a corresponding to the first conductive pattern 539a, the first insulating capping pattern 542a, and the first insulating spacer 545a shown in FIG. 1 is formed on the buffer insulating pattern 636, ), The first insulating capping pattern 642a, and the first insulating spacer 645a may be provided. A first contact structure 638p which penetrates the buffer insulating pattern 636 and electrically connects one region 618a of the first impurity regions 618a and 618b to the first conductive pattern 639a, May be provided.
A second gate capping pattern 642g corresponding to the second gate capping pattern 542g and the second insulating spacer 645g of FIG. 1 and a second gate spacer pattern 642g corresponding to the second insulating spacer 645g are formed on the substrate of the second region D2 645g) may be provided. A first interlayer insulating film 651 corresponding to the first interlayer insulating film 551 of FIG. 1 is provided on the substrate having the first and second regions D1 and D2 and the intermediate region E .
A cell contact structure 660 electrically connected to one region 618b of the first impurity regions 618a and 618b is provided through the first interlayer insulating film 651 and the buffer insulating pattern 636 . The protruding portion of the first gate capping pattern 627 may be positioned between the cell contact structure 660 and the first contact structure 638p. Therefore, the protruded portion of the first gate capping pattern 627 can prevent an electrical short between the cell contact structure 660 and the first contact structure 638p.
A second contact structure 672b electrically connected to one region 648a of the second impurity regions 648a and 648b through the first interlayer insulating film 651 may be provided. The second contact structure 672b may be provided at substantially the same level as the cell contact structure 660. The second contact structure 672b and the cell contact structure 660 may include the same conductive material.
A conductive buffer pattern 675b covering the cell contact structure 660 may be provided on the first interlayer insulating film 651. [ A second conductive pattern 675a may be provided on the first interlayer insulating film 651 to cover the second contact structure 672b. A connection structure 672a interposed between the first and second conductive patterns 639a and 672b and electrically connecting the first and second conductive patterns 639a and 672b may be provided. The buffer pattern 675b and the second conductive pattern 675a may be located at substantially the same level. The buffer pattern 675b and the second conductive pattern 675a may be formed to include the same material.
A second interlayer insulating film 684 may be provided to surround the burr pattern 675b and the sidewalls of the second conductive pattern 675a. An information storage element 697 may be provided on the buffer pattern 675b. The information storage element 697 may correspond to the information storage element 597 of FIG.
Hereinafter, methods of manufacturing a semiconductor device according to embodiments of the present invention will be described. FIG. 3 is a plan view showing a semiconductor device according to embodiments of the present invention. FIGS. 4A, 4B, 5A, 5B, 6A, 6B, 7A, 7B, 8A, 8B, 9A, 9B, 10A, 13b, 14a, 14b, 15a, 15b, 16a, 16b, 17a and 17b are cross-sectional views showing another method of manufacturing a semiconductor device according to an embodiment of the present invention. Sectional views illustrating a method of manufacturing a semiconductor device according to an example, and FIGS. 18a, 18b, and 19 are cross-sectional views illustrating a method of manufacturing a semiconductor device according to another embodiment of the present invention.
In the figures, Figures 4a, 5a, 6a, 7a, 8a, 9a, 10a, 11a, 12a, 13a, 14a, 15a, 16a, 17a and 18a are cross- 4B, 5B, 6B, 7B, 8B, 9B, 10B, 11B, 12B, 13B, 14B, 15B, 16B, 17B, 18B and 19 are sectional views taken along line II-II in FIG. 3 to 19, reference character "C" represents a first region, reference symbol "M" represents an intermediate region, and reference character "P" represents a second region.
First, a method of manufacturing a semiconductor device according to embodiments of the present invention will be described with reference to FIGS. 3 and 4A to 12B.
3, 4A and 4B, a semiconductor substrate 1 having a first region C, a second region P and an intermediate region M can be prepared. The semiconductor substrate 1 may be a semiconductor wafer comprising a semiconductor material such as silicon. The first region C may be a memory cell array region, and the second region P may be a peripheral circuit region. The middle region M may be a predetermined region between the first element on the first region C, for example, a cell transistor, and a second element on the second region P, for example, a peripheral transistor. Therefore, in the drawing of the present embodiment, the middle area M is displayed as an independent area between the first area C such as the memory cell array area and the second area P such as the peripheral circuit area. However, The present invention is not limited thereto. For example, the intermediate region M may be located in a first region C, such as a memory cell array region, or in a second region P, such as the peripheral circuit region.
An element isolation region 3s may be formed in the semiconductor substrate 1 to define the active regions 3a and 3b. More specifically, the element isolation region 3s defines a first active region, for example, a cell active region 3a in the first region C, and a second active region 3b in the second region P, , For example, the peripheral active region 3b. The device isolation region 3s may be formed using a shallow trench isolation process.
A preliminary impurity region (not shown) of a conductive type different from that of the semiconductor substrate 1 of the first region C can be formed in the cell active region 3a. For example, when the cell active region 3a is a p-type, impurity ions are injected into the cell active region 3a to form an n < th > type impurity region (not shown) can be formed.
A dielectric film 6 and a gate conductive film 9 sequentially stacked on the semiconductor substrate 1 can be formed. The dielectric layer 26 may be formed to include at least one of a silicon oxide layer and a high-k dielectric layer. Here, "high-dielectric-constant film" may mean a dielectric having a higher dielectric constant than the silicon oxide film. The gate conductive film 9 may be formed of a conductive material film such as a polysilicon film.
The gate conductive film 9 and the dielectric film 6 on the first region C are patterned to form openings for exposing predetermined regions of the cell active region 3a and the device isolation region 3s, The gate trench 15 can be formed by etching the cell active region 3a and the device isolation region 3s exposed by the opening. The gate trench 15 may extend across the cell active region 3a and extend to the device isolation region 3s. The gate trench 15 may have a line width dimension less than the resolution limit of the lithographic process.
The gate trench 15 may be formed to cross the cell active region 3a where the preliminary impurity region (not shown) is formed. Thus, the preliminary impurity regions (not shown) may be divided into cell impurity regions, that is, cell source / drain regions 18a and 18b, which are spaced apart from each other by the gate trenches 15. [
The preliminary impurity region (not shown) in one cell active region 3a can be divided into three cell impurity regions 18a and 18b by a pair of gate trenches 15. [ Here, among the three cell impurity regions 18a and 18b, one impurity region located between the pair of gate trenches 15 is defined as a first cell impurity region 18a, Regions can be defined as the second cell impurity regions 18b.
Referring to FIGS. 3, 5A and 5B, a cell gate dielectric film 21 may be formed on a semiconductor substrate having the cell gate trenches 15. The cell gate dielectric layer 21 may be formed to cover at least the inner wall of the cell gate trench 15 in the cell active region 3a. The cell gate dielectric layer 21 may be formed to include at least one of a silicon oxide layer and a high-k dielectric layer.
A cell gate pattern 24 filling the cell gate trench 15 can be formed on a semiconductor substrate having the cell gate dielectric film 21. [ The cell gate pattern 24 may fill at least a portion of the cell gate trench 15. The cell gate pattern 24 may partially fill the cell gate trench 15 so as to be located at a lower level than the top surface of the cell active region 3a. The cell gate pattern 24 at a portion across the cell active region 3a can be defined as a cell gate electrode. The cell gate pattern 24 may be formed to include at least one of a metal film, a metal nitride film, a metal silicide film, and a polysilicon film. The cell source / drain regions 18, the cell gate dielectric layer 21, and the cell gate pattern 24 may form the cell transistors CT1 and CT2. That is, the cell transistors CT1 and CT2 may be a buried channel array transistor (BCAT).
A cell gate capping pattern 27 filling the remaining portion of the cell gate trench 15 can be formed. The cell gate capping pattern 27 may be formed to include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.
The mask pattern 30 can be formed on the gate conductive film 9 of the second region P. [ Therefore, the gate conductive film 9 of the first region C and the intermediate region M can be exposed by the mask pattern 30. [ The mask pattern 30 may be a photoresist pattern. Alternatively, the mask pattern 30 may be formed of an insulating film such as a silicon oxide film or a silicon nitride film.
Referring to FIGS. 3, 6A and 6B, the gate conductive film 9 on the first region C and the intermediate region M is etched using the mask pattern 30 (FIG. 5B) The gate conductive pattern 9a remaining on the second region P can be formed by etching.
In another embodiment, unlike the method of forming the first impurity regions 18a and 18b in the embodiment described above, the ion implantation process is performed on the substrate on which the gate conductive pattern 9a is formed, The first impurity regions, that is, the cell source / drain regions 18a and 18b, may be formed in the active region 3a.
On the other hand, during the etching of the gate conductive film 9 on the first region C and the intermediate region M, the dielectric film 6, the cell gate dielectric film 21, and the cell gate capping pattern 27 May also be etched together.
The mask pattern (30 in Fig. 5B) can be removed. The blocking film 33 may be formed on the semiconductor substrate from which the mask pattern 30 is removed. The stopper film 33 may be formed of an insulating material having an etch selectivity with respect to the element isolation region 3s. For example, when the element isolation region 3s is formed of a silicon oxide film, the stopper film 33 may be formed of a silicon nitride film. The stopper film 33 may be formed as a cone foam. The stopper film 33 covers the element isolation region 3s and the cell transistors CT1 and CT2 of the first region C and is electrically connected to the gate conductive pattern 9a .
A buffer insulating film can be formed on the blocking film 33. [ The buffer insulating film may be formed of a material film having an etch selectivity with respect to the stopper film 33. For example, when the blocking film 33 is formed of a silicon nitride film, the buffer insulating film may be formed of a silicon oxide film. The buffer insulating film is planarized until the blocking film 33 or the gate conductive pattern 9a of the second region P is exposed and the buffer insulating film 36 ) Can be formed.
Referring to FIGS. 3, 7A, and 7B, the capping insulating layer 37 may be formed on the semiconductor substrate having the buffer insulating pattern 36. The capping insulating film 37 may be formed of an insulating film such as a silicon oxide film or a silicon nitride film.
A bit line contact hole (not shown) for exposing one region 18a of the cell impurity regions 18a and 18b by patterning the capping insulating film 37, the buffer insulating pattern 36 and the stopping film 33 36a can be formed. For example, the bit line contact hole 36a may be formed to expose the first cell impurity region 18a shared by the cell transistors CT1 and CT2.
The first conductive layer 38 may be formed on the semiconductor substrate having the bit line contact hole 36a. The first conductive layer 38 may include at least one of a metal layer, a metal nitride layer, a metal silicide layer, and a polysilicon layer. For example, the first conductive layer 38 may be formed to include a sequentially stacked Ti film, a TiN film, and a W film. Here, the W film fills the bit line contact hole 36a, and the Ti film and the TiN film stacked in this order are interposed between the inner wall of the bit line contact hole 36a and the W film to serve as a diffusion barrier film can do.
In the first conductive layer 38, a portion of the first conductive layer 38 that contacts the first cell impurity region 18a exposed by the bit line contact hole 36a may be made of a metal silicide. For example, a metal silicide film may be formed on the first cell impurity region 18a, a metal material film may be formed to fill the bit line contact hole 36a and cover the semiconductor substrate to form the first conductive film 38, Can be formed. Alternatively, the first conductive layer 38 may be formed by sequentially forming a first metal material layer and a second metal material layer filling the bit line contact hole 36a and covering the semiconductor substrate, and performing a heat treatment process And reacting the metal of the first metal material layer and the silicon of the first cell impurity region 18a to form a metal silicide film.
Referring to FIGS. 3, 8A and 8B, the process of exposing the gate conductive pattern 9a on the second region P may be performed. For example, with respect to the semiconductor substrate having the first conductive film (38 in Figs. 7A and 7B), the chemical mechanical mechanical polishing process is performed until the stopper film (33 in Figs. 7A and 7B) on the second region P is exposed A planarization process such as a CMP process may be performed, and then a process of etching the stopper film (33 of FIGS. 7A and 7B) on the second region P may be performed. Alternatively, a chemical mechanical polishing process (CMP) may be performed on the semiconductor substrate having the first conductive film (38 in FIGS. 7A and 7B) until the gate conductive pattern 9a on the second region P is exposed. The planarization process can be performed. As a result, the first contact structure remaining in the bit line contact hole 36a, that is, the bit line structure structure 38p can be formed, and the capping film 37 (Figs. 7A and 7B) .
A second conductive film 39 covering the bit line contact structure 38p and the exposed gate conductive pattern 9a can be formed. The second conductive layer 39 may include at least one of a metal layer, a metal nitride layer, a metal silicide layer, and a polysilicon layer.
In some embodiments of the present invention, the second conductive layer 39 may be formed to include a conductive material different from the gate conductive pattern 9a. The second conductive layer 39 may be formed to include a conductive material layer having a higher electrical conductivity than the gate conductive pattern 9a. For example, the gate conductive pattern 9a may be formed of a dope polysilicon film, and the second conductive film 39 may be formed to include a metal material film such as a tungsten film. Here, considering the contact resistance characteristic between the metal conductive film 9a and the metal material film such as the tungsten film, the portion of the second conductive film 39 which contacts the gate conductive pattern 9a is formed on the metal silicide film 9a, .
In another embodiment, the gate conductive pattern 9a and the second conductive film 39 may be formed of the same conductive material film.
In yet another embodiment, after forming the buffer insulation pattern 36 in Figures 7a and 7b or during formation of the buffer insulation pattern 36, the gate conductive pattern < RTI ID = 0.0 > 9a are exposed. For example, during the planarization of the buffer insulating film using a chemical mechanical polishing (CMP) process to form the buffer insulating pattern 36, the buffer insulating film is planarized until the gate conductive pattern 9a is exposed So that the blocking film 33 on the second region P can be removed. Alternatively, after the buffer insulating film is planarized using the stopper film 33 on the second region P as a planarization stopper film, the stopper film 33 on the second region P is removed by etching can do. A bit line contact hole 36a is formed to expose the first cell impurity region 18a by patterning the buffer insulating pattern 36 and the stopper film 33. The bit line contact hole 36a, A conductive film covering the buffer insulating pattern 36 and the gate conductive pattern 9a may be formed, for example, a conductive film of the same material as the first conductive film 38 described with reference to FIGS. 7A and 7B. Therefore, the second conductive film 39 and the bit line contact structure 38p in FIGS. 8A and 8B may include the same material film formed by the same process.
Referring to FIGS. 3, 9A and 9B, a mask film may be formed on the second conductive film 39 (FIGS. 8A and 8B). The mask film may be formed to include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The mask pattern, the second conductive film (39 in Figs. 8A and 8B) and the gate conductive pattern (9a in Figs. 8A and 8B) are patterned to form a first conductive pattern The first peripheral gate electrode 9g and the second peripheral gate electrode 39g and the peripheral capping pattern 39a and the bit line capping pattern 42a are sequentially formed on the first region P, (42g) can be formed. Accordingly, the first conductive pattern 39a and the second peripheral gate electrode 39g may be formed simultaneously and formed of the same material layer. In addition, the first conductive pattern 39a and the second peripheral gate electrode 39g may be located at substantially the same level.
The first and second peripheral gate electrodes 9g and 39g may be defined as a peripheral gate pattern 40. [ The first conductive pattern 39a may be defined as a cell bit line. The peripheral gate pattern 40 and the first conductive pattern 39a may correspond to the peripheral gate patterns 540 and 640 and the first conductive patterns 539a and 639a described in FIGS. The cell bit line 39a may extend to the middle region M. [ The peripheral gate pattern 40 may be formed in a substantially line shape and may extend over the device isolation region 3s that defines the peripheral active region 3b across the peripheral active region 3b. The dielectric film between the peripheral gate pattern 40 and the peripheral active region 3b may be defined as a peripheral gate dielectric film 6a.
A bit line spacer 45a is formed on the sidewalls of the cell bit line 39a and the bit line capping pattern 42a which are sequentially stacked and the bit line spacer 45a is formed on the sidewall of the bit line capping pattern 42a, The peripheral gate spacers 45g may be formed on the sidewalls of the pattern 42b. The peripheral gate spacers 45g and the bit line spacers 45a may be formed to include at least one of a silicon nitride film, a silicon oxynitride film, and a silicon oxide film.
Dopant ions may be implanted and activated in the peripheral active region 3b on either side of the peripheral gate pattern 40 to form peripheral impurity regions, i.e., peripheral source / drain regions 48. [ Thus, a channel region in the peripheral active region 3b under the peripheral source / drain regions 48, the peripheral gate dielectric layer 6a, the peripheral gate pattern 40, and the peripheral gate pattern 40 is included The peripheral transistor PT1 can be formed.
Referring to FIGS. 3, 10A and 10B, a first interlayer insulating film 51 may be formed on the semiconductor substrate 1 having the cell bit line 39a and the peripheral transistor PT1. The first interlayer insulating film 51 may be formed to have a substantially flat top surface. For example, an insulating material film is formed on the semiconductor substrate 1 having the cell bit line 39a and the peripheral transistor PT1, and the insulating material film is subjected to a planarization process such as chemical mechanical polishing (CMP) The first interlayer insulating film 51 having a planarized upper surface can be formed. In the planarization step for forming the first interlayer insulating film 51, the bit line capping pattern 42a and the peripheral gate capping pattern 42g may be used as the planarization stopping film. 10, the first interlayer insulating film 51 is not limited to the bit line capping pattern 42a and the first interlayer insulating film 51 may have a planarized upper surface, And may have a planarized top surface to expose top surfaces of the peripheral gate capping pattern 42g.
In the first region C, the first interlayer insulating film 51, the buffer insulating pattern 36, and the stopping film 33 are sequentially patterned to form the first and second regions C of the first region C, Cell contact holes 54 exposing the second cell impurity regions 18b among the cell impurity regions 18a and 18b can be formed.
Since the cell bit line 39a is located at substantially the same level as the second peripheral gate electrode 39g of the peripheral transistor PT2 in the present embodiment, The overall thickness does not increase. Therefore, the cell contact holes 54 may be formed by etching the insulating films to a thickness substantially caused by forming the peripheral transistor PT1. This not only shortens the etching process time for forming the cell contact holes 54, but also increases the etching process margin. In addition, since the cell bit line 39a and the second peripheral gate electrode 39g are simultaneously formed without a separate process for forming the cell bit line 39a, the whole process time can be shortened.
The cell contact structures 60 filling the cell contact holes 54 can be formed. The cell contact structures 60 may be formed to include at least one of a metal film, a metal nitride film, a metal silicide film, and a polysilicon film. For example, the cell contact structures 60 may include a metal film filling the cell contact holes 54, and may include a diffusion barrier film interposed between the metal film and the inner walls of the cell contact holes 54 have. In addition, a portion of the cell contact structures 60, which contacts the second cell impurity regions 18b exposed by the cell contact holes 54, may be made of a metal silicide. For example, the cell contact structures 60 may be formed by forming a metal silicide film on the second cell impurity regions 18a and forming a conductive material film filling the cell contact holes 54. [ Alternatively, the formation of the cell contact structures 60 may be performed by subjecting the metal film and the metal nitride film, which sequentially cover the inner walls of the cell contact holes 54, to a heat treatment process so that the metal element of the metal film and the second cell impurity And reacting the silicon element of the regions 18b to form a metal silicide film formed.
Referring to FIGS. 3, 11A and 11B, a second interlayer insulating film 63 may be formed on the first interlayer insulating film 51. In the second region P, a peripheral contact hole 66b that penetrates the first and second interlayer insulating films 51 and 63 and exposes at least one of the peripheral impurity regions 48 may be formed. have. In the intermediate region M, a connection via hole 66a is formed through the second interlayer insulating film 63 and the bit line capping pattern 42a to expose a predetermined region of the cell bit line 39a. .
The conductive connection structure 72a filling the connection via hole 66a may be formed and the conductive peripheral contact structure 72b filling the peripheral contact hole 66b may be formed. The connection structure 72a and the peripheral contact structure 72b may be formed to include at least one of a metal film, a metal nitride film, a metal silicide film, and a polysilicon film.
Meanwhile, the peripheral contact structure 72b may include a conductive material different from the cell contact structure 60. For example, when the cell contact structure 60 includes a polysilicon film, the peripheral contact structure 72b may include a metal material film such as tungsten.
The second conductive pattern 75 and the wiring capping pattern 78 which are sequentially stacked on the second interlayer insulating film 63 can be formed. The second conductive pattern 75 may cover the connection structure 72a and the peripheral contact structure 72b. The second conductive pattern 75 may be formed to include at least one of a metal film, a metal nitride film, and a polysilicon film. The wiring capping pattern 78 may be formed of an insulating material film such as a silicon nitride film. The formation of the wiring capping pattern 75 may be omitted.
In another embodiment, the second conductive pattern 75, the connection structure 72a and the peripheral contact structure 72b may be formed of a conductive material formed at the same time. For example, a conductive material film filling the connection via hole 66a and the peripheral contact hole 66b and covering the second interlayer insulating film 63 is formed, and the conductive material film is patterned to form the second conductive pattern 75 ), The connection structure 72a and the peripheral contact structure 72b may be integrally formed.
The cell transistors CT1 and the peripheral transistor PT1 may be electrically connected by the second conductive pattern 75. [ More specifically, one of the peripheral impurity regions 48 of the peripheral transistor PT1 and the first cell impurity region 18a of the cell transistors CT1 and CT2 are connected to the bit line contact structure 38p, The first conductive pattern 39a, the connection structure 72a, the second conductive pattern 75, and the peripheral contact structure 72b. The wiring spacer 81 may be formed on the sidewalls of the second conductive pattern 75 and the wiring capping pattern 78. [
Referring to FIGS. 3, 12A and 12B, a third interlayer insulating film 84 may be formed on the semiconductor substrate having the second conductive pattern 75. The third interlayer insulating film 84 can be planarized. The etching stopper film 87 may be formed on the third interlayer insulating film 84. [
The first interlayer insulating film 84 and the second interlayer insulating film 63 are electrically connected to the cell contact structures 60 and the etching stopper film 87, An information storage element 97 protruding upward can be formed. The information storage element 97 may include a first electrode 90, a second electrode 96 and an information storage material layer 93 between the first and second electrodes 90 and 96 .
When the present embodiment is used for a memory device such as a DRAM (DRAM), the information storage material film 93 may comprise a cell capacitor dielectric material of a DRAM (DRAM). However, this embodiment is not limited to the DRAM, but can be used for various semiconductor devices. Therefore, the information storage material layer 93 may be formed of various information storage materials such as a material layer on the top of a PRAM or a ferroelectric layer of an FeRAM, depending on characteristics of a desired device .
12A, the first electrode 90 is shown as a cylinder. However, the first electrode 90 may be formed in various shapes depending on the characteristics of the device. For example, the first electrode 90 may have various shapes such as a pillar shape or a plate shape.
Next, a method of manufacturing a semiconductor device according to another embodiment of the present invention will be described with reference to FIGS. 3 and 13A to 16B.
3, 13A, and 13B, a semiconductor substrate 100 having a first region C, a second region P, and an intermediate region M as shown in FIG. 4 can be prepared. The first and second active regions 3a and 3b, the element isolation region 3s, the dielectric film 6, the gate conductive film 9 (see FIG. 4) in FIGS. 4 and 5 are formed on the semiconductor substrate 100, ), The gate trench 15, the cell impurity regions 18a and 18b, the cell gate dielectric film 21, the cell gate pattern 24, the cell gate capping pattern 27, the cell transistors CT1 First and second active regions 103a and 103b and an isolation region 103s and a dielectric film 106 and a gate conductive film gate trench 115 and cell impurity regions 118a and 118b, The cell gate pattern 124 and the cell gate capping pattern 127 and the cell transistors CT3 and CT4 are fabricated in substantially the same manner as the methods in Figures 4 and 5, .
5B, a mask pattern 130 is formed on the gate conductive film of the second region P, and the gate conductive film is etched to form a gate conductive pattern (FIG. 5B) 109a can be formed. In this embodiment, during formation of the gate conductive pattern 109a, the cell gate capping pattern 127 may remain so as to have a portion protruding from the upper surface of the first active region 103a. That is, the cell gate capping pattern 127 may remain with the cell gate pattern 124 so as to have a protrusion that fills the gate trench 115 and is located at a higher level than the first active area 103a.
In another embodiment, the impurity regions 118a and 118b may be formed in the first active region 103a by performing an ion implantation process on the substrate on which the gate conductive pattern 109a is formed.
Meanwhile, during formation of the gate conductive pattern 109a, at least a part of the dielectric film 106 and the cell gate dielectric film 121 may be etched.
Referring to FIGS. 3, 14A and 14B, the mask pattern (130 in FIG. 13B) can be removed. Subsequently, the stopper film 133 may be conformally formed on the resultant of removing the mask pattern (130 in FIG. 13B). A buffer insulating film may be formed on the blocking film 133. [ The buffer insulating layer 136 may be formed by planarizing the buffer insulating layer 133 or the gate conductive pattern 109a on the second region P until the buffer insulating layer 136 is exposed.
On the other hand, when the blocking film 133 remains on the gate conductive pattern 109a while the buffer insulating pattern 136 is formed, the blocking film 133 on the gate conductive pattern 109a Can be removed.
On the other hand, when the buffer insulating layer is planarized using a chemical mechanical polishing (CMP) process, protrusions of the gate capping pattern 127 on the first region C may serve as a planarization stopper film. For example, in the case where the gate capping pattern 127 is formed of a silicon nitride film and the buffer insulating film is formed of a silicon oxide film, the gate capping pattern 127 may be used as a planarization stopping film. Therefore, since the dishing phenomenon in the first region C can be prevented during the planarization process for the buffer insulation layer, the buffer insulation pattern 136 can be formed in a flat upper surface with a significantly reduced dishing phenomenon Lt; / RTI >
Referring to FIGS. 3, 15A and 15B, on the first active region 103a of the first region C, the insulating material under the buffer insulating pattern 136 and the buffer insulating pattern 136, For example, the blocking film 133 may be patterned to form a bit line contact hole 136a exposing the first cell impurity region 118a. Some of the sidewalls of the bit line contact holes 136a may be defined by the protruding portions of the cell gate capping patterns 127. [ Therefore, in order to form the bit line contact hole 136a, the photolithography process margin at the time of forming the photoresist pattern on the buffer insulating pattern 136 can be increased.
A first conductive layer may be formed on the entire surface of the semiconductor substrate having the bit line contact hole 136. The first conductive film at a portion defined by the bit line contact hole 136 may be defined as the first contact structure 138p.
A bit line capping pattern 142a and a peripheral gate capping pattern 142b are formed on the first conductive film and the bit line capping pattern 142a and the peripheral capping pattern 142b are used as an etching mask, The first conductive film and the gate conductive pattern (109a in Figs. 14A and 14B) can be etched in turn. As a result, a first conductive pattern, that is, a cell bit line 139a is formed on the first region C and the middle region M, and a first conductive pattern is formed on the second region P, The peripheral gate electrode 109g and the second peripheral gate electrode 139g may be formed. The first and second peripheral gate electrodes 109g and 139g may constitute a peripheral gate pattern 140. Referring to FIG. Accordingly, at least a portion of the cell bit line 139a may be formed to be located at substantially the same level as at least a part of the peripheral gate pattern 140. [
The cell bit line 139a may cover the bit line contact hole 136a. Accordingly, the first contact structure 138a and the cell bit line 139a in the cell bit line contact hole 136a are connected to each other and may be formed of the same material. The dielectric film between the peripheral gate pattern 140 and the peripheral active region 103b may be defined as a peripheral gate dielectric film 106a.
A bit line spacer 145a is formed on the sidewalls of the cell bit line 139a and the bit line capping pattern 142a which are sequentially stacked and the bit line spacers 145a are formed on the sidewalls of the bit line capping pattern 142a, The peripheral gate spacers 145g may be formed on the sidewalls of the pattern 142b.
Drain regions 148 may be formed by implanting and activating impurity ions in the second active region 103b on either side of the peripheral gate pattern 140. [ Therefore, the channel region in the second active region 103b under the peripheral source / drain regions 148, the peripheral gate dielectric layer 106a, the peripheral gate pattern 140, The peripheral transistor PT2 can be formed.
Referring to FIGS. 3, 16A and 16B, a first interlayer insulating film 151 may be formed on a substrate having the peripheral transistor PT2. The first interlayer insulating layer 151 may be formed to have a flat upper surface. For example, an insulating material film may be formed on a substrate having the peripheral transistor PT2, and the insulating material film may be planarized to form the first interlayer insulating film 151 having a flat upper surface . The planarization process may use a chemical mechanical polishing (CMP) process using the bit line capping pattern 142a and the peripheral gate capping pattern 142g as a planarization stopping film.
In the first region C, a cell which penetrates the first interlayer insulating film 151, the buffer insulating pattern 136, and the stopping film 133 and exposes the second cell impurity regions 118b, The contact holes 154a can be formed. The cell contact structures 160a filling the cell contact holes 154a may be formed.
The peripheral contact hole 154b may be formed in the second region P to expose at least one of the peripheral impurity regions 148 through the first interlayer insulating film 151. [ The peripheral contact structure 160b filling the peripheral contact hole 154b may be formed. The cell and peripheral contact holes 154a and 154b may be formed at the same time. Also, the cell and the neighboring contact structures 160a and 160b may be simultaneously formed. Accordingly, the cell and the neighboring contact structures 160a and 160b may be formed of the same conductive material.
Referring to FIGS. 3, 17A and 17B, a connection via hole 161 is formed in the middle region M to expose a predetermined region of the cell bit line 139a through the bit line capping pattern 42a. Can be formed. A third conductive layer filling the connection via hole 161 is formed and the third conductive layer is patterned to form buffer patterns 175a covering the cell contact structures 160a, The second conductive pattern 175b covering the peripheral contact structure 160b while covering the hole 161 can be formed. The third conductive film in the connection via hole 161 may be defined as a connection structure 175p. The second conductive pattern 175b is electrically connected to the cell bit line 139a through the connection structure 175p and the peripheral transistor PT2 through the peripheral contact structure 160b, And may be electrically connected to one of the peripheral impurity regions 148.
In another embodiment, the connection structure 175p may be formed simultaneously with the cell and the surrounding contact structures 160a and 160b.
In another embodiment, the buffer patterns 175a and the second conductive pattern 175b may be formed using a damascene process. For example, a second interlayer insulating film 184 is formed on a substrate having the cell and the neighboring contact structures 160a and 160b, and the buffer patterns 175a and 175b are formed in the second interlayer insulating film 184, Forming a damascene structure of grooves for forming the second conductive pattern 175b, forming a conductive material film filling the grooves, and planarizing the conductive material film to form the buffer patterns 175a and 175a defined in the grooves, The second conductive pattern 175b can be formed.
The etching stopper film 187 covering the buffer patterns 175a and the second conductive pattern 175b may be formed. Information storage elements 197 electrically connected to the buffer patterns 184 may be formed on the buffer patterns 184. The information storage elements 197 may be used as information storage means for volatile memory devices or nonvolatile memory devices.
Next, another embodiment of the present invention will be described with reference to Figs. 18A, 18B and 19.
Referring to FIGS. 3, 18A and 18B, a semiconductor substrate 200 having a first region C, a second region P and an intermediate region M is prepared as shown in FIGS. 4A and 4B . The device isolation region 203s defining the first and second active regions 203a and 203b can be formed on the semiconductor substrate 200 by using the same method as in FIGS. 4A and 4B. A preliminary impurity region can be formed in the first active region 203a.
A stopper film 206 and a buffer insulating film 209 stacked in this order on the semiconductor substrate 200 can be formed. The stopper film 206 may include a material film having an etch selectivity with respect to the element isolation region 203s. The buffer insulating layer 209 may be formed of a single layer made of an insulating material. Alternatively, the buffer insulating layer 209 may have a multi-layer structure having different etch ratios, i.e., different material layers. For example, the buffer insulating layer 209 may include a first material layer such as a silicon oxide layer and a second material layer such as a polysilicon layer or a silicon nitride layer. Here, the second material layer may be formed on the first material layer.
The buffer insulating layer 209 on the semiconductor substrate of the first region C is patterned to form openings for exposing predetermined regions of the first active region 203a and the device isolation region 203s, The first active region 203a and the device isolation region 203s exposed by the first active region 203a may be etched to form the gate trench 215 as shown in FIG. By the gate trench 215, the preliminary impurity region may be formed as a first and a second cell impurity regions 218a and 218b.
The cell gate dielectric layer 221 and the cell gate pattern 224 may be sequentially formed in the cell gate trench 215 using the method as shown in FIG. 5A. Therefore, the cell transistors CT5 and CT6 may be formed in the first active region 203a.
A cell gate capping pattern 227 may be formed that fills the remaining portion of the cell gate trench 215 and has a portion protruding from the top surface of the first active region 203a. The cell gate capping pattern 227 may be formed to include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.
On the other hand, when the buffer insulating layer 209 includes a first material layer and a second material layer which are sequentially stacked, the second material layer is formed while forming the cell gate capping pattern 227, (227). ≪ / RTI >
Referring to FIGS. 3 and 19, the buffer insulating layer 209 is patterned to expose the second active region 203 of the second region P, and the first region C and the intermediate region The buffer insulating pattern 209a remaining on the buffer insulating layer 209a can be formed. Next, the gate dielectric layer 210 and the gate conductive pattern 211, which are sequentially stacked on the substrate of the second region P, may be formed.
The gate dielectric layer 210 and the gate conductive pattern 211 are formed on the dielectric layers 6 and 106 and the gate conductive patterns 9a and 109a which are sequentially stacked on the second active regions 3b and 103b of FIGS. Respectively. Although the method of forming the buffer insulating pattern 209a, the gate dielectric film 210 and the gate conductive pattern 211 in the embodiment of FIG. 19 is similar to the method of forming the buffer insulating pattern 209 in the embodiments of FIGS. 6B and 14B, The method of forming the gate conductive patterns 36 and 136, the dielectric films 6 and 106 and the gate conductive patterns 9a and 109a is somewhat different, but the results are similar. Therefore, the first conductive patterns 39a and 139a described in the previous embodiments are formed on the semiconductor substrate having the buffer insulating pattern 209a, the gate dielectric film 210, and the gate conductive pattern 211 in this embodiment, The second conductive pattern 175b, the information storage elements 97 and 197, and the like.
20 is a schematic diagram showing products using semiconductor devices according to embodiments of the present invention. Referring to FIG. 20, a semiconductor chip 710 using a semiconductor device according to the above-described embodiments may be provided. For example, for bulk semiconductor wafers having a plurality of chip areas, the integrated circuit and information storage means can be formed using the methods according to the embodiments described above. As described above, a plurality of semiconductor chips 710 can be formed by separating the chip regions of the semiconductor wafer on which the integrated circuit and the information storing means are formed. The semiconductor chip 710 may be formed as a package. The semiconductor chip 710 may be employed in the electronic product 720. The semiconductor chip 710 may serve as an information storage medium in the electronic product 720. For example, the semiconductor chip 710 may be used as a component in an electronic product 720 that requires an information storage medium, such as a digital TV, a computer, a digital camera, a communication device, an electronic dictionary, a portable memory device, For example, the packaged semiconductor chip 710 can be installed on a board or a memory module and can be adopted as a component constituting the electronic product 720.
1 is a cross-sectional view illustrating a semiconductor device according to an embodiment of the present invention.
2 is a cross-sectional view illustrating a semiconductor device according to another embodiment of the present invention.
3 is a plan view of a semiconductor device according to embodiments of the present invention.
4A to 12B are cross-sectional views illustrating a method of manufacturing a semiconductor device according to another embodiment of the present invention.
13A to 17B are cross-sectional views illustrating a method of manufacturing a semiconductor device according to another embodiment of the present invention.
18A, 18B, and 19 are cross-sectional views illustrating a method of manufacturing a semiconductor device according to another embodiment of the present invention.
20 is a schematic view showing a semiconductor chip and an electronic product according to embodiments of the present invention.

Claims (25)

  1. A semiconductor substrate having first and second active regions;
    A first transistor formed in the first active region of the semiconductor substrate, the first transistor including first impurity regions and a first gate pattern;
    A second transistor formed in the second active region of the semiconductor substrate, the second transistor including second impurity regions and a second gate pattern;
    A first conductive pattern on the first transistor;
    A cell contact structure electrically connected to one of the first impurity regions;
    An information storage element on the cell contact structure;
    A second conductive pattern located at a level higher than the first conductive pattern;
    A connection structure interposed between the first conductive pattern and the second conductive pattern, the connection structure electrically connecting the first and second conductive patterns; And
    And a peripheral contact structure interposed between one of the second impurity regions and the second conductive pattern and electrically connecting one of the second impurity regions to the second conductive pattern,
    Wherein at least a portion of the first conductive pattern is located at the same level as at least a portion of the second gate pattern,
    Wherein the information storage element has a top surface located at a higher level than the first and second conductive patterns.
  2. The method according to claim 1,
    The first transistor
    Said first gate pattern of conductive material provided in a gate trench transverse to said first active region;
    The first impurity regions in the first active region on both sides of the first gate pattern; And
    And a first gate dielectric layer between the first gate pattern and the gate trench.
  3. 3. The method of claim 2,
    Further comprising an insulating first gate capping pattern filling the gate trench with the first gate pattern, wherein the first gate capping pattern has a protruding portion at a level higher than the first active region.
  4. The method according to claim 1,
    And a first contact structure electrically connecting the first conductive pattern to the remaining one of the first impurity regions that is not connected to the cell contact structure.
  5. The method according to claim 1,
    The second transistor
    The second gate pattern traversing the second active region;
    A second gate dielectric layer between the second gate pattern and the active region; And
    And the second impurity regions in the second active region on both sides of the second gate pattern,
    Wherein the second gate pattern includes a first gate electrode and a second gate electrode which are sequentially stacked, and the second gate electrode is located at substantially the same level as the first conductive pattern.
  6. delete
  7. delete
  8. The method according to claim 1,
    Further comprising a conductive buffer pattern between the cell contact structure and the information storage element,
    Wherein the conductive buffer pattern is located at the same level as the second conductive pattern.
  9. delete
  10. delete
  11. The method according to claim 1,
    Wherein the cell contact structure and the peripheral contact structure have upper surfaces located at different levels.
  12. The method according to claim 1,
    Wherein the cell contact structure and the peripheral contact structure have upper surfaces positioned at the same level with each other.
  13. delete
  14. In an electronic product including a semiconductor chip,
    The semiconductor chip
    A semiconductor substrate having a cell array region and a peripheral circuit region;
    A cell transistor formed on the semiconductor substrate of the cell array region, the cell transistor including first impurity regions and a first gate pattern;
    A peripheral transistor formed on the semiconductor substrate of the peripheral circuit region, the peripheral transistor including a first peripheral gate electrode and a second peripheral gate electrode sequentially stacked on the substrate between the second impurity regions and the second impurity regions;
    A cell bit line formed on the cell transistor in the cell array region and having at least a portion located at the same level as at least a portion of the second peripheral gate electrode;
    A cell contact structure electrically connected to one of the first impurity regions;
    An information storage element on the cell contact structure;
    A second conductive pattern located at a level higher than the first conductive pattern;
    A connection structure interposed between the first conductive pattern and the second conductive pattern, the connection structure electrically connecting the first and second conductive patterns;
    A peripheral contact structure interposed between one of the second impurity regions and the second conductive pattern and electrically connecting one of the second impurity regions to the second conductive pattern; And
    And a conductive buffer pattern between the cell contact structure and the information storage element,
    Wherein at least a part of the conductive buffer pattern and at least a part of the second conductive pattern are located at the same level.
  15. Preparing a semiconductor substrate having first and second active regions,
    Forming a first transistor including a first gate pattern across the first active region and first impurity regions within the first active region on both sides of the first gate pattern,
    Forming a second transistor including a second gate pattern across the second active region and second impurity regions within the second active region on either side of the second gate pattern,
    And forming a first conductive pattern on the first transistor while forming the second gate pattern of the second transistor,
    The first and second transistors, and forming the first conductive pattern,
    Forming the first impurity regions in the first active region,
    Forming a gate trench across the first active region,
    Forming the first gate pattern filling at least a portion of the gate trench,
    Forming a gate conductive pattern on the second active region,
    Forming a buffer insulating pattern on the first active region,
    Forming a first conductive film covering the buffer insulating pattern and the gate conductive pattern,
    Forming the first conductive pattern on the buffer insulating pattern by patterning the first conductive film on the buffer insulating pattern and the gate conductive pattern and the first conductive film which are sequentially stacked on the second active region, And forming a first gate electrode and a second gate electrode sequentially stacked on the second active region.
  16. delete
  17. 16. The method of claim 15,
    After forming the first gate pattern,
    Further comprising forming a first gate capping pattern on the first gate pattern to fill the gate trench with the first gate pattern, wherein the first gate capping pattern comprises a protrusion higher in level than the first active area Wherein the semiconductor device is a semiconductor device.
  18. 16. The method of claim 15,
    Wherein the buffer insulating pattern is formed after the gate conductive pattern is formed.
  19. 16. The method of claim 15,
    Wherein the gate conductive pattern is formed after forming the buffer insulating pattern.
  20. 16. The method of claim 15,
    Before forming the first conductive pattern,
    Further comprising forming a first contact structure through the buffer insulation pattern and electrically connected to one of the first impurity regions, wherein the first contact structure comprises a semiconductor element electrically connected to the first conductive pattern Gt;
  21. delete
  22. delete
  23. delete
  24. delete
  25. delete
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US12/232,498 US8063425B2 (en) 2007-09-18 2008-09-18 Semiconductor device having reduced thickness, electronic product employing the same, and methods of fabricating the same
CN2008102152075A CN101393917B (en) 2007-09-18 2008-09-18 Semiconductor device having reduced thickness, electronic product employing the same, and methods of fabricating the same
JP2008239778A JP5544075B2 (en) 2007-09-18 2008-09-18 Semiconductor device with reduced thickness, electronic product employing the same, and method of manufacturing the same
US12/662,150 US8120123B2 (en) 2007-09-18 2010-04-01 Semiconductor device and method of forming the same
US13/241,716 US8450786B2 (en) 2007-09-18 2011-09-23 Semiconductor devices including buried gate electrodes
US13/900,910 US8766356B2 (en) 2007-09-18 2013-05-23 Semiconductor devices having bit line insulating capping patterns and multiple conductive patterns thereon

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KR101623123B1 (en) 2009-07-23 2016-05-23 삼성전자주식회사 Semiconductor device and method of fabricating the same
KR101131890B1 (en) * 2009-10-09 2012-04-03 주식회사 하이닉스반도체 Method for manufacturing semiconductor device with buried gate
KR101096875B1 (en) * 2009-12-09 2011-12-22 주식회사 하이닉스반도체 Method for manufacturing semiconductor having buried gate
KR20130053278A (en) * 2011-11-15 2013-05-23 에스케이하이닉스 주식회사 Semiconductor device for increasing bitline contact area and module and system using the device
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