KR101441533B1 - Apparatus for transmitting image signal - Google Patents

Abstract

A video signal transmission apparatus is disclosed. A video signal transmission apparatus according to an embodiment of the present invention includes a determination unit, a conversion unit, and a transmission unit. The determination unit determines whether the signal amplitude in the vertical driving period of the vertical synchronization signal of the video signal to be transmitted is a high logic state or a low logic state. According to the determination result of the determination unit, the conversion unit outputs the video signal in which the vertical synchronization signal is inverted if the signal size in the vertical driving period of the vertical synchronization signal of the video signal to be transmitted is high. The transmitting unit transmits an output signal from the converting unit.

Description

[0001] Apparatus for transmitting image signals [0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a video signal transmission apparatus, and more particularly, to an apparatus for receiving, processing, and transmitting a video signal from a host apparatus or a repeater.

The video signals basically include an image data signal, a clock signal, a vertical synchronization signal, a horizontal synchronization signal, and a data enable signal.

The kinds of video signals are variously set based on the resolution by the Video Electronics Standards Association (VESA).

In the transmission of the above-mentioned video signals, in most cases, the vertical synchronization signal and the horizontal synchronization signal are transmitted as a combined signal. For example, when video signals are transmitted in the form of a TMDS (Transition Minimized Differential Signaling) signal, a vertical synchronizing signal and a horizontal synchronizing signal are carried on a blue (B) data channel.

Here, there are video signals that make direct current balancing in the case where the vertical synchronizing signal and the horizontal synchronizing signal are combined according to the prescribed types of video signals, and the video signals that make direct current unbalancing .

When the vertical synchronizing signal and the horizontal synchronizing signal electrically transmit image signals constituting direct current balancing, the accuracy of transmission is not degraded.

However, when the vertical synchronizing signal and the horizontal synchronizing signal optically transmit a video signal having direct current unbalancing, the transmission accuracy is low. This is because, when the video signal is optically transmitted, the threshold value for determining whether the signal size is high logic state or low logic state is changed to the average threshold value of the latest period in most receiving apparatuses.

Korean Patent Laid-Open Publication No. 2005-0022268 (filed by Nippon Victor Kabushiki Kaisha, entitled: Transmission System)

Embodiments of the present invention provide a video signal transmission apparatus capable of preventing transmission accuracy from being degraded even when a vertical synchronizing signal and a horizontal synchronizing signal optically transmit a video signal having direct current unbalancing do.

An apparatus for transmitting a video signal according to an aspect of the present invention includes a determination unit, a conversion unit, and a transmission unit.

The discriminator discriminates whether the signal amplitude in the vertical driving period of the vertical synchronous signal of the video signal to be transmitted is a high logic state or a low logic state.

The converting unit outputs a video signal in which the vertical synchronizing signal is inverted if the signal size in the vertical driving period of the vertical synchronizing signal of the video signal to be transmitted is high according to the determination result of the determining unit.

The transmitting unit transmits an output signal from the converting unit.

Preferably, the determination unit detects the resolution of the input video signal Sim1 and refers to the video Electronics Standards Association (VESA) specification for the signal of the detected resolution to convert the input video signal Sim1 ) Is a high logic state or a low logic state.

Preferably, the determination unit includes a frame memory, a resolution detection unit, and a determination control unit.

The input video signal Sim1 is temporarily stored in the frame memory.

The resolution detector detects the resolution of the video signal Sim1 input from the frame memory and generates a resolution information signal Sre.

The discrimination control section refers to a built-in look-up table (LUT) according to the resolution information signal Sre from the resolution detecting section and determines whether or not the vertical synchronizing signal of the input video signal Sim1 And outputs a discrimination result signal Sde to control the output of the input video signal Sim1 stored in the frame memory.

Preferably, the conversion unit includes a frame memory, a conversion control unit, a signal separation unit, an inverting unit, a buffer memory, and a signal restoration unit.

In the frame memory, the input video signal Sim1 from the determination unit is temporarily stored, and the stored input video signal Sim1 is selectively output to the first output port and the second output port.

Wherein the conversion control unit performs control so that the input video signal Sim1 stored in the frame memory is selectively output to the first output port and the second output port in accordance with the determination result signal Sde from the determination unit do.

Wherein the signal separating unit separates the input video signal Sim1 into a video data signal DAT, a clock signal CLK, a vertical synchronizing signal SYNC, and a clock signal CLK when the input video signal Sim1 is output to the second output port in the frame memory. (VS1), a horizontal synchronizing signal (HS), and a data enable signal.

The inverting unit inverts the vertical synchronization signal VS1 from the signal separation unit under the control of the conversion control unit.

The buffer memory controls the image data signal DAT, the clock signal CLK, the horizontal synchronizing signal HS, and the data enable signal ENA during the propagation delay period of the inverting unit, And outputs it.

The signal restoring unit may include an inverted vertical synchronizing signal VS2 from the inverting unit and the video data signal DAT from the buffer memory, a clock signal CLK, a horizontal synchronizing signal HS, and generates a restored video signal Sim2 corresponding to the format of the input video signal Sim1 by combining the enable signal and outputs the generated restored video signal Sim2 to the transmission unit.

Preferably, the transfer unit transfers the input video signal (Sim1) from the first output port of the frame memory or the restored video signal (Sim2) from the signal restoring unit.

Preferably, when the video signal to be transmitted is an optical video signal, the optical signal receiving unit converts the optical video signal into an electrical video signal and inputs the converted electrical video signal to the discriminator.

Preferably, when the video signal to be transmitted is an optical video signal, the transmitting unit converts an output signal from the converting unit into an optical signal and transmits the optical signal.

According to the Video Electronics Standards Association (VESA), in all video signals, while the vertical synchronization signal is in the low logic state, the vertical synchronization signal and the horizontal synchronization signal form direct current balancing .

On the contrary, in all the video signals, while the vertical synchronizing signal is in the high logic state, the vertical synchronizing signal and the horizontal synchronizing signal make direct current unbalancing.

On the other hand, the vertical synchronization signal has a vertical synchronization section, which is an initial short pulse section, and a vertical driving section, which is a remaining long section.

Therefore, according to the kind of the video signal to be transmitted, when the signal size in the vertical driving period of the vertical synchronizing signal is high, the direct current unbalancing period of the vertical synchronizing signal and the horizontal synchronizing signal becomes long.

On the other hand, according to the video signal transmission apparatus of the embodiments of the present invention, when the signal size in the vertical driving period of the vertical synchronizing signal of the video signal to be transmitted is high, the video signal in which the vertical synchronizing signal is inverted is transmitted .

Accordingly, in the video signal to be transmitted, since the signal amplitude in the vertical driving period of the vertical synchronizing signal becomes low regardless of the type of the video signal to be transmitted, the direct current balance of the vertical synchronizing signal and the horizontal synchronizing signal balancing.

That is, when a vertical synchronizing signal and a horizontal synchronizing signal optically transmit a video signal having direct current unbalancing, the transmission of the video signal according to the embodiments of the present invention does not degrade the transmission accuracy.

For reference, it has been confirmed that most of the image receiving apparatuses, for example, the display apparatus can operate normally even if the vertical synchronizing signal of the received image signal is inverted. The vertical synchronization signal can be easily restored by referring to the transmission apparatus of the present invention.

1 is a block diagram showing a video signal transmission apparatus according to an embodiment of the present invention.
2 is a block diagram showing the internal configuration of the determination unit of FIG.
3 is a block diagram showing the internal configuration of the conversion unit of FIG.
FIG. 4 is a diagram illustrating a vertical synchronizing signal of an image signal of a 60 GHz (Hz), 1600 X 1200 resolution ultra-extended graphics array (UXGA) according to the Video Electronics Standards Association (VESA) VS and a horizontal synchronizing signal HS.
Fig. 5 is a waveform diagram showing in detail the "A" block of Fig.
6 shows a vertical synchronization signal VS of an image signal of an extended graphics array (XGA) having a resolution of 60 Hertz (Hz) and 1024 X 768 according to the Video Electronics Standards Association (VESA) And a horizontal synchronizing signal (HS).
7 is a waveform diagram showing in detail the block "B" in Fig.
8 is a block diagram showing a video signal transmission apparatus according to another embodiment of the present invention.

The following description and accompanying drawings are for understanding the operation according to the present invention, and parts that can be easily implemented by those skilled in the art can be omitted.

Furthermore, the specification and drawings are not intended to limit the present invention, and the scope of the present invention should be determined by the claims. The terms used in the present specification should be construed to mean the meanings and concepts consistent with the technical idea of the present invention in order to best express the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Fig. 1 shows a transmission apparatus of a video signal Sim1 according to an embodiment of the present invention.

Referring to FIG. 1, a transmission apparatus for a video signal (Sim 1) in an embodiment of the present invention includes a determination unit 11, a conversion unit 12, and a transmission unit 13.

The discrimination unit 11 discriminates whether the signal amplitude in the vertical driving period of the vertical synchronizing signal of the video signal Sim1 to be transmitted is a high logic state or a low logic state. In Fig. 1, reference symbol Sde indicates a signal of the determination result.

If the signal size of the vertical synchronizing signal of the video signal to be transmitted Sim1 in the vertical driving period is a logic state according to the determination result of the determining unit 11, the converting unit 12 converts the vertical synchronizing signal And outputs a signal Sim2.

The transmitting unit 13 transmits the output signal Sim1 or Sim2 from the converting unit 12. [

According to the Video Electronics Standards Association (VESA), in all video signals, while the vertical synchronization signal is in the low logic state, the vertical synchronization signal and the horizontal synchronization signal form direct current balancing .

On the contrary, in all the video signals, while the vertical synchronizing signal is in the high logic state, the vertical synchronizing signal and the horizontal synchronizing signal make direct current unbalancing.

On the other hand, the vertical synchronization signal has a vertical synchronization section, which is an initial short pulse section, and a vertical driving section, which is a remaining long section.

Therefore, according to the kind of the video signal to be transmitted, when the signal size in the vertical driving period of the vertical synchronizing signal is high, the direct current unbalancing period of the vertical synchronizing signal and the horizontal synchronizing signal becomes long.

On the other hand, according to the video signal transmission apparatus of the embodiment of FIG. 1, if the signal magnitude in the vertical driving period of the vertical synchronizing signal of the video signal to be transmitted Sim1 is high, ).

Thus, in the video signal (Sim1 or Sim2) to be transmitted, the signal size in the vertical driving section of the vertical synchronizing signal becomes low, regardless of the type of the video signal (Sim1 or Sim2) to be transmitted. And the direct current balancing section of the horizontal synchronization signal becomes longer.

That is, when a vertical synchronizing signal and a horizontal synchronizing signal optically transmit a video signal having direct current unbalancing, the transmission of the video signal according to the embodiments of the present invention does not degrade the transmission accuracy.

For reference, it has been confirmed that most of the image receiving apparatuses, for example, the display apparatus can operate normally even if the vertical synchronizing signal of the received image signal is inverted. The vertical synchronization signal can be easily restored by referring to the transmission apparatus of the present invention.

Fig. 2 shows the internal structure of the discrimination unit 11 of Fig. Here, the determination unit 11 detects the resolution of the input video signal Sim1 and refers to the specification of the Video Electronics Standards Association (VESA) for the signal Sim1 of the detected resolution, It is determined whether the waveform in the driving period of the vertical synchronizing signal of the input video signal Sim1 is a high logic state or a low logic state.

1 and 2, the determination unit 11 includes a frame memory 21, a resolution detection unit 22, and a determination control unit 23.

In the frame memory 21, the input video signal Sim1 is temporarily stored.

The resolution detector 22 detects the resolution of the video signal Sim1 input from the frame memory 21 and generates a resolution information signal Sre.

The discrimination control section 23 refers to the built-in look-up table (LUT) in accordance with the resolution information signal Sre from the resolution detecting section 22 and determines whether or not the vertical synchronizing signal of the input video signal Sim1 The discrimination result signal Sde is outputted and the input video signal Sim1 stored in the frame memory 21 is controlled to be outputted. In Fig. 2, reference symbol Sou designates an output control signal input from the discrimination control section 23 to the frame memory 21.

The contents of a look-up table (LUT) according to the Video Electronics Standards Association (VESA) are described as follows. In the following description, information "1" indicates that the waveform in the driving period of the vertical synchronizing signal is a high logical state, and information "0" indicates that the waveform in the driving period of the vertical synchronizing signal is in a low logical state.

1) 85 hertz ( Hz ), 640 x 350 resolution => information "1"

2) 85 Hertz (Hz), 640 X 400 resolution => information "0"

3) 85 Hertz (Hz), 720 X 400 resolution => information "0"

4a) 60 Hertz ( Hz ), 640 X 480 resolution => information "1"

4b) 72 Hertz ( Hz ), 640 X 480 resolution => information "1"

4c) 75 hertz ( Hz ), 640 X 480 resolution => information "1"

4d) 85 Hertz ( Hz ), 640 X 480 resolution => information "1"

5a) 56 Hertz (Hz), 800 X 600 resolution => information "0"

5b) 60 Hertz (Hz), 800 X 600 resolution => information "0"

5c) 72 Hertz (Hz), 800 X 600 resolution => information "0"

5d) 75 Hertz (Hz), 800 X 600 resolution => information "0"

5e) 85 Hertz (Hz), 800 X 600 resolution => information "0"

6a) 43 hertz (Hz), 1024 x 768 resolution => information "0"

6b) 60 Hertz ( Hz ), 1024 X 768 resolution => information "1"

6c) 70 Hertz ( Hz ), 1024 X 768 resolution => information "1"

6d) 75 Hertz (Hz), 1024 X 768 resolution => information "0"

6e) 85 Hertz (Hz), 1024 X 768 resolution => information "0"

7) 75 Hertz (Hz), 1152 X 864 resolution => information "0"

8a) 60 Hertz (Hz), 1280 X 960 resolution => information "0"

8b) 85 Hz (Hz), 1280 X 960 resolution => information "0"

9a) 60 Hertz (Hz), 1280 X 1024 resolution => information "0"

9b) 75 Hertz (Hz), 1280 X 1024 resolution => information "0"

9c) 85 Hz (Hz), 1280 x 1024 resolution => information "0"

10a) 60 Hertz (Hz), 1600 X 1200 resolution => information "0"

10b) 65 Hertz (Hz), 1600 X 1200 resolution => information "0"

10c) 70 Hertz (Hz), 1600 X 1200 resolution => information "0"

10d) 75 hertz (Hz), 1600 x 1200 resolution => information "0"

10e) 85 Hertz (Hz), 1600 X 1200 resolution => information "0"

11a) 60 Hertz (Hz), 1792 X 1344 resolution => information "0"

11b) 75 Hertz (Hz), 1792 X 1344 Resolution => Information "0"

12a) 60 Hertz (Hz), 1856 X 1392 resolution => information "0"

12b) 75 Hertz (Hz), 1856 X 1392 Resolution => Information "0"

13a) 60 Hertz (Hz), 1920 X 1440 resolution => information "0"

13b) 75 Hertz (Hz), 1920 X 1440 Resolution => Information "0"

Referring to the list, the objects to be inverted in the vertical synchronization signal in the conversion unit 12 are as follows.

1) 85 hertz ( Hz ), 640 X 350 resolution

4a) 60 Hertz ( Hz ), 640 X 480 resolution

4b) 72 Hertz ( Hz ), 640 X 480 resolution

4c) 75 hertz ( Hz ), 640 X 480 resolution

4d) 85 Hertz ( Hz ), 640 X 480 resolution

6b) 60 Hertz ( Hz ), 1024 X 768 resolution

6c) 70 Hertz ( Hz ), 1024 X 768 resolution

It should be noted that a user input unit may be used instead of the resolution detector 22 and a user setting signal may be input to the determination controller 23. [

Fig. 3 shows an internal configuration of the conversion unit 12 of Fig.

1 and 3, the conversion unit 12 of FIG. 1 includes a frame memory 31, a conversion control unit 32, a signal separation unit 33, an inverting unit 34, a buffer memory 35, And a restoration unit 36.

The frame memory 31 temporarily stores the input video signal Sim1 from the determining unit 11 and outputs the stored input video signal Sim1 to the first output port 31P1 and the second output port 31P2 And is selectively output.

The conversion control section 32 outputs the input video signal Sim1 stored in the frame memory 31 to the first output port 31P1 and the second output port 31P2 according to the determination result signal Sde from the determination section 11. [ And selectively outputs to the port 31P2.

When the input video signal Sim1 is outputted to the second output port 31P2 from the frame memory 31, the signal separator 33 divides the input video signal Sim1 into the video data signal DAT, the clock signal CLK ), A vertical synchronization signal (VS1), a horizontal synchronization signal (HS), and a data enable signal. The image data signal DAT includes parallel 8-bit red (R) gradation data, parallel 8-bit green (G) gradation data, and parallel 8-bit blue (B) gradation data for each pixel.

For example, when the input video signal Sim1 is in the form of a TMDS (Transition Minimized Differential Signaling) signal, the coding result of the TMDS is decoded to separate the input video signal Sim1.

The inversion section 34 inverts the vertical synchronization signal VS1 from the signal separation section 33 under the control of the conversion control section 32. [

The buffer memory 35 stores the video data signal DAT, the clock signal CLK, the horizontal synchronizing signal HS, and the video data signal DAT during the transmission delay period of the inverting unit 34 under the control of the conversion control unit 32. [ And outputs a data enable signal after storing the data enable signal.

The signal restoring unit 36 receives the inverted vertical synchronizing signal VS2 from the inverting unit 34 and the video data signal DAT from the buffer memory 35, the clock signal CLK, the horizontal synchronizing signal HS ) And a data enable signal to generate a restored video signal Sim2 conforming to the format of the input video signal Sim1 and outputs the generated restored video signal Sim2 to the transfer unit 13 .

The transfer unit 13 transfers the input video signal Sim1 from the first output port 31P1 of the frame memory 31 or the restored video signal Sim2 from the signal restoring unit 36. [

FIG. 4 is a diagram illustrating a vertical synchronizing signal of an image signal of a 60 GHz (Hz), 1600 X 1200 resolution ultra-extended graphics array (UXGA) according to the Video Electronics Standards Association (VESA) VS and a horizontal synchronizing signal HS.

Fig. 5 shows in detail the "A" block of Fig.

Referring to FIGS. 4 and 5, in a unit frame or unit field, a total of 1,250 horizontal pixel lines are scanned. In the vertical synchronization period VSP, three horizontal pixel lines are scanned. In the vertical back-porch interval (VBP), 46 horizontal pixel lines are scanned. In the vertical address period (VAD), 1,200 horizontal pixel lines are scanned. And one horizontal pixel line is scanned in the vertical front-porch section (VFP).

Accordingly, 1,247 horizontal pixel lines are scanned in the vertical driving period (VBP + VAD + VFP).

In the unit horizontal period, a total of 2,160 horizontal pixels are scanned. In the horizontal synchronization period (HSP), 192 horizontal pixels are scanned. In the horizontal back-porch section (HBP), 144 horizontal pixels are scanned. In the horizontal address period (HAD), 1,600 horizontal pixels are scanned. In the horizontal front-porch section (HFP), 64 horizontal pixels are scanned.

Therefore, 1,968 horizontal pixels are scanned in the horizontal driving period (HBP + HAD + HFP).

As described above, the vertical synchronization period VSP is a short time in which only three horizontal pixel lines are scanned, but the remaining vertical driving period VBP + VAD + VFP is long time in which 1,247 horizontal pixel lines are scanned .

According to the Video Electronics Standards Association (VESA), in all video signals, while the vertical synchronization signal is in the low logic state, the vertical synchronization signal and the horizontal synchronization signal form direct current balancing .

Therefore, in the case of an image signal of an ultra-extended graphics array (UXGA) having a resolution of 60 Hz and a resolution of 1600 x 1200 shown in FIGS. 4 and 5, only a very short vertical synchronization period VSP ) And the horizontal synchronizing signal HS form direct current unbalancing while the remaining vertical driving period VBP + VAD + VFP forms the vertical synchronizing signal VS and the horizontal synchronizing signal HS in direct current balance Current balancing.

Accordingly, in the case of a video signal of the ultra-extended graphics array (UXGA) having a resolution of 60 Hz and a resolution of 1600 X 1200, the video signal is passed through the first output port 31P1 in the frame memory 31 of FIG.

6 shows a vertical synchronization signal VS of an image signal of an extended graphics array (XGA) having a resolution of 60 Hertz (Hz) and 1024 X 768 according to the Video Electronics Standards Association (VESA) And a horizontal synchronization signal (HS).

Fig. 7 shows in detail the "B" block of Fig.

Referring to FIGS. 6 and 7, a total of 806 horizontal pixel lines are scanned in a unit frame or unit field. In the vertical synchronization period (VSP), six horizontal pixel lines are scanned. In the vertical back-porch interval (VBP), 29 horizontal pixel lines are scanned. In the vertical address period (VAD), 768 horizontal pixel lines are scanned. In the vertical front-porch section (VFP), three horizontal pixel lines are scanned.

Therefore, 800 horizontal pixel lines are scanned in the vertical driving period (VBP + VAD + VFP).

In the unit horizontal period, a total of 1,344 horizontal pixels are scanned. In the horizontal synchronization period (HSP), 136 horizontal pixels are scanned. In a horizontal back-porch section (HBP), 160 horizontal pixels are scanned. In the horizontal address period (HAD), 1,024 horizontal pixels are scanned. In the horizontal front-porch section (HFP), 24 horizontal pixels are scanned.

Therefore, 1,208 horizontal pixels are scanned in the horizontal driving period (HBP + HAD + HFP).

As described above, the vertical synchronization period VSP is a short time during which only six horizontal pixel lines are scanned, but the remaining vertical driving period VBP + VAD + VFP is a long time during which 800 horizontal pixel lines are scanned .

According to the Video Electronics Standards Association (VESA), in all video signals, while the vertical synchronization signal is in the low logic state, the vertical synchronization signal and the horizontal synchronization signal form direct current balancing .

Therefore, in the case of an image signal of an extended graphics array (XGA) having a resolution of 604 Hz and a resolution of 1024 X 768 in FIGS. 6 and 7, only a very short vertical synchronization period VSP is used for a vertical synchronization signal VS The vertical synchronization signal VS and the horizontal synchronization signal HS form a direct current unbalance in the long vertical driving period VBP + VAD + VFP, ).

Accordingly, in the case of an image signal of the expanded graphics array (XGA) having resolution of 60 Hz and 1024 X 768, the image signal is output from the frame memory 31 of FIG. 3 through the second output port 31P2, The synchronous signal VS is inverted.

FIG. 8 shows an apparatus for transmitting a video signal according to another embodiment of the present invention. In Fig. 8, the same reference numerals as those in Fig. 1 denote objects having the same function. Therefore, only the difference of the embodiment of FIG. 8 with respect to the embodiment of FIG. 1 will be described as follows.

In the embodiment of FIG. 8, the video signal to be transmitted is an optical video signal input through the optical fiber lines 801 to 80n.

The optical signal receiving unit 82 further converts the optical image signal to an electrical image signal Sim1 and inputs the converted electrical image signal Sim1 to the discriminating unit 11. [

The transmitting unit 83 includes an optical signal generating unit at its output terminal and converts the output signal Sim1 or Sim2 from the converting unit 12 (see Figs. 1 and 3 and the description thereof) into an optical signal . The converted optical signal is transmitted through the optical fiber lines 811 to 81n.

As described above, according to the provisions of the Video Electronics Standards Association (VESA), in all the video signals, while the vertical synchronization signal is in the low logic state, the vertical synchronization signal and the horizontal synchronization signal are supplied to the DC balance Direct current balancing.

On the contrary, in all the video signals, while the vertical synchronizing signal is in the high logic state, the vertical synchronizing signal and the horizontal synchronizing signal make direct current unbalancing.

On the other hand, the vertical synchronization signal has a vertical synchronization section, which is an initial short pulse section, and a vertical driving section, which is a remaining long section.

Therefore, according to the kind of the video signal to be transmitted, when the signal size in the vertical driving period of the vertical synchronizing signal is high, the direct current unbalancing period of the vertical synchronizing signal and the horizontal synchronizing signal becomes long.

On the other hand, according to the video signal transmission apparatus of the embodiments of the present invention, when the signal size in the vertical driving period of the vertical synchronizing signal of the video signal to be transmitted is high, the video signal in which the vertical synchronizing signal is inverted is transmitted.

Accordingly, in the video signal to be transmitted, since the signal amplitude in the vertical driving period of the vertical synchronizing signal becomes low regardless of the type of the video signal to be transmitted, the direct current balance of the vertical synchronizing signal and the horizontal synchronizing signal balancing.

That is, when a vertical synchronizing signal and a horizontal synchronizing signal optically transmit a video signal having direct current unbalancing, the transmission of the video signal according to the embodiments of the present invention does not degrade the transmission accuracy.

For reference, it has been confirmed that most of the image receiving apparatuses, for example, the display apparatus can operate normally even if the vertical synchronizing signal of the received image signal is inverted. The vertical synchronization signal can be easily restored by referring to the transmission apparatus of the present invention.

The present invention has been described above with reference to preferred embodiments. It will be understood by those skilled in the art that the present invention may be embodied in various other forms without departing from the spirit or essential characteristics thereof.

Therefore, the above-described embodiments should be considered in a descriptive sense rather than a restrictive sense. The scope of the present invention is defined by the appended claims rather than by the foregoing description, and the inventions claimed by the claims and the inventions equivalent to the claimed invention are to be construed as being included in the present invention.

There is a possibility of being used not only in a video signal transmission apparatus but also in a general video apparatus.

11: discrimination unit, 12: conversion unit,
13: transmission unit, 21: frame memory,
22: resolution detection section, 23: discrimination control section,
31: frame memory, 32: conversion control section,
33: signal separator, 34: inverting part,
35: buffer memory, 36: signal restoring section,
VS: vertical synchronizing signal, HS: horizontal synchronizing signal,
VSP: vertical synchronization section,
VBP + VAD + VFP: vertical driving period,
VBP: vertical back-porch section, VAD: vertical address section,
VFP: vertical front-porch section,
HSP: Horizontal sync interval,
HBP + HAD + HFP: horizontal driving section,
HBP: horizontal back-porch section, HAD: horizontal address section,
HFP: horizontal front-porch section,
801 to 80n: optical fiber lines, 811 to 81n: optical fiber lines,
82: Optical signal receiving section, 83: Transmission section.

Claims (7)

delete delete delete A discrimination unit for discriminating whether a signal size in a vertical driving period of a vertical synchronizing signal of a video signal to be transmitted is a high logic state or a low logic state;
A conversion unit for outputting a video signal in which the vertical synchronization signal is inverted when the signal size of the vertical synchronization signal of the video signal to be transmitted is a high logic state according to the determination result of the determination unit; And
And a transmitting unit for transmitting an output signal from the converting unit,
Wherein,
A frame memory for temporarily storing an input video signal Sim1 from the determination unit and selectively outputting the stored input video signal Sim1 to a first output port and a second output port;
A conversion control unit for selectively outputting the input video signal Sim1 stored in the frame memory to the first output port and the second output port in accordance with the determination result signal Sde from the determination unit;
When the input video signal Sim1 is output to the second output port in the frame memory, the input video signal Sim1 is converted into a video data signal DAT, a clock signal CLK, a vertical synchronization signal VS1, A synchronizing signal (HS), and a data enable signal;
An inverting unit for inverting the vertical synchronization signal VS1 from the signal separation unit under the control of the conversion control unit;
The image data signal DAT, the clock signal CLK, the horizontal synchronizing signal HS, and the data enable signal are stored in the transmission delay section of the inversion section under the control of the conversion control section, Buffer memory; And
A vertical synchronizing signal VS2 inverted from the inverting portion and a video data signal DAT, a clock signal CLK, a horizontal synchronizing signal HS, and a data enable signal from the buffer memory And generating a restored video signal (Sim2) corresponding to the format of the input video signal (Sim1), and outputting the generated restored video signal (Sim2) to the transfer unit. 5. The apparatus of claim 4,
And transmits the input video signal (Sim1) from the first output port of the frame memory or the restored video signal (Sim2) from the signal restoring section. A discrimination unit for discriminating whether a signal size in a vertical driving period of a vertical synchronizing signal of a video signal to be transmitted is a high logic state or a low logic state;
A conversion unit for outputting a video signal in which the vertical synchronization signal is inverted when the signal size of the vertical synchronization signal of the video signal to be transmitted is a high logic state according to the determination result of the determination unit; And
And a transmitting unit for transmitting an output signal from the converting unit,
If the video signal to be transmitted is an optical video signal,
And an optical signal receiving unit for converting the optical image signal into an electrical image signal and inputting the converted electrical image signal to the discriminating unit. 7. The method of claim 6, wherein when the video signal to be transmitted is an optical video signal,
Wherein the transmission unit includes an optical signal generation unit that converts an output signal from the conversion unit into an optical signal and transmits the optical signal.

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