KR101430169B1 - Programming method of non-volatile memory device - Google Patents

Abstract

Applying a program voltage to the memory cell; Applying a supplemental pulse to promote stabilization of charge after application of the program voltage; Applying a recovery voltage to the memory cell following the supplemental pulse; And applying and applying a verify voltage after applying the recovery voltage to the nonvolatile memory device.

Description

[0001] The present invention relates to a programming method of a non-volatile memory device,

The present invention relates to a nonvolatile memory device programming method, and more particularly, to a nonvolatile memory device programming method capable of effectively reducing a threshold voltage distribution in a program state.

A nonvolatile memory in a semiconductor memory is a storage device in which stored data is preserved without being lost even when power supply is interrupted.

As a nonvolatile memory with a large capacity, a floating gate type flash memory that operates by storing a charge in a floating gate made of polysilicon is currently commercialized.

A memory cell of a flash memory has a single level cell (SLC) recording two write states (1 and 0) in one cell and four or more states (for example, 11, 10, 00, 01), for example, may be divided into a multi level cell (MLC).

Multi-level cell technology is an important technology for increasing the capacity of NAND type and NOR type flash memory.

In the multi-level cell operation, the distances of the threshold voltage (Vth) values of the cells corresponding to the respective recording states must be small so that the respective recording states can be separated and recognized.

In general, in the flash memory, an incremental step pulse programming (ISPP) method is used in which repeatedly applying a program voltage Vpgm while raising the program voltage Vpgm in order to reduce the distribution of threshold voltages between memory cells.

As is well known, in the ISPP method, a program voltage pulse is applied while gradually increasing the magnitude of an applied program voltage pulse by? Vpgm, and then a verifying voltage pulse is applied to thereby increase the threshold voltage of the memory cell And the threshold voltage of the memory cell reaches a desired value by repeating the checking process. Since a plurality of memory cells constituting the flash memory have an initial threshold voltage distribution, the ISPP scheme is introduced in order to allow all the memory cells to reach a desired threshold voltage in consideration of the threshold voltage distribution for each memory cell.

However, in a flash memory using a floating gate, as the cell size becomes smaller, it becomes difficult to control the dispersion of such a threshold voltage due to coupling between cells, in particular, coupling between floating gates.

Recently, in order to solve this problem, an insulating layer including a charge trapping site such as silicon nitride (Si ₃ N ₄ ) capable of trapping charges, that is, a charge trap layer a charge trap flash (CTF) memory using a charge trap layer is being developed.

However, electrons injected into the charge trap type flash memory are trapped in the charge trap layer and localized. At this time, electrons in the nitride film are spatially spread as they are thermally trapped by a deep trap. As the electrons are stabilized and spatially spread, the threshold voltage value of the device changes. Therefore, it takes time to stabilize the threshold voltage (Vth) as the stabilized localized electron thermalization proceeds.

Thus, in the charge trap type flash memory, the threshold voltage value fluctuates with time after programming due to the charge movement trapped in the charge trap layer after programming.

The variation of the time-dependent Vth with time makes it difficult to control the threshold voltage value dispersion at the time of programming by the incremental step pulse programming (ISPP) method.

If the threshold voltage varies with time as described above, an error occurs in the operation of verifying the program state after a predetermined time after programming.

This verification error causes a problem that the dispersion of the threshold voltage value of the program state obtained by the ISPP type program increases.

That is, if the threshold voltage varies with time, a verification error is verified that the verify result memory cell does not reach the target threshold voltage even if the threshold voltage can reach the target value substantially over time . If it is verified that the target threshold voltage has not been reached as a result of the verification, the program voltage is increased again by DELTA Vpgm to be programmed, resulting in an over program in which the threshold voltage becomes excessively high. As a result, the dispersion of the threshold voltage value of the program state increases.

An object of the present invention is to provide a programming method of a nonvolatile memory device which can prevent over programming and reduce a threshold voltage distribution in a program state.

The present invention is a nonvolatile memory device capable of solving the problem that the saturation time of the threshold voltage is relatively longer than when the supplemental pulse is applied to the lower bulk or channel of the memory cell by applying the recovery pulse following the supplemental pulse, And a method of programming a memory device.

A method of programming a non-volatile memory device according to the present invention includes: applying a program voltage to a memory cell; Applying a supplemental pulse to promote stabilization of charge after application of the program voltage; Applying a recovery voltage to the memory cell following the supplemental pulse; And applying and applying a verify voltage after applying the recovery voltage.

The supplemental pulse may be adapted to apply an electric field having an opposite polarity to the electric field by the program voltage.

The supplemental pulse may be applied through the lower bulk or channel of the memory cell.

The recovery voltage may be a positive voltage having the same polarity as the verify voltage and the program voltage, and the supplemental pulse may be a voltage having a polarity opposite to the program voltage, the recovery voltage, and the verify voltage.

The program voltage, the verify voltage, and the recovery voltage may be applied to the control gate of the memory cell. The programming method of the non-volatile memory device according to the present invention includes: ) A first programming step of applying a program voltage to the memory cell and subsequently verifying with a first verify voltage; (B) applying a supplemental pulse to facilitate the stabilization of the charge for the memory cell which has passed the verification using the first verify voltage; (C) applying a recovery voltage to the memory cell following the supplemental pulse; (D) verifying the second verify voltage higher than the first verify voltage after the recovery voltage is applied.

Wherein the recovery voltage is a positive voltage that is greater than the first and second verify voltages and that is the same polarity as the program voltage and the first and second verify voltages and wherein the supplemental pulse comprises a program voltage, And may be a voltage having an opposite polarity to the second verify voltage.

A programming voltage is applied to the memory cell and a supplementary pulse for promoting charge stabilization is applied to the lower bulk or channel of the memory cell when the verification using the second verify voltage in step (d) And a second programming step of applying a recovery voltage and verifying the second verify voltage again.

In the second programming step, a program voltage is applied, a supplemental pulse is applied, a recovery voltage is applied, and a verify operation is performed by a second verify voltage, stepwise increasing the magnitude of the program voltage until the verification using the second verify voltage is passed Can be repeated.

In the first programming step, the verify operation using the program voltage and the first verify voltage may be repeated while increasing the magnitude of the program voltage step by step until the verification using the first verify voltage is passed.

The memory cell has a control gate and a charge storage layer, and the program voltage, the first and second verify voltages, and the recovery voltage may be applied to the control gate of the memory cell.

In the above, the memory cell may be any one of a floating gate type flash memory cell and a charge trap type flash memory cell.

The nonvolatile memory device has a NAND array structure of a plurality of memory cells formed on a bulk, and the memory cell may be a selected one of a plurality of memory cells arranged in a NAND array structure.

Here, the bulk is a p-well formed in a semiconductor substrate, and the plurality of memory cells may be formed in an array so as to share a source / drain with the p-well.

The NAND array structure may further include a plurality of strings each including a plurality of memory cell arrays, a ground selection transistor on both sides of each string, and a string selection transistor, the complement of the program voltage, the verify voltage, Pulse application may be accomplished by applying a voltage greater than 0V to a common source and a ground select transistor electrically coupled to a string where the selected memory cell is located and applying a ground voltage to the selected memory cell.

According to the programming method of the present invention, a supplemental pulse is applied to the lower bulk or channel of the memory cell after application of the program pulse, and then a recovery pulse is applied.

According to the programming method of the present invention, the stabilization of the charge is promoted, so that the threshold voltage reaches the saturation state within a short period of time, thereby preventing the over program due to the judgment error.

Further, according to the programming method of the present invention, when applying the recovery pulse to the bulk or the channel, the problem that the saturation time of the threshold voltage becomes relatively longer than when the supplementary pulse is applied to the gate can be solved.

When the program method of the present invention is applied, since the scattering of the threshold voltage value of the cells corresponding to each recording state is small, each recording state can be separated and recognized in the multi-level cell operation.

Hereinafter, preferred embodiments of a method of programming a non-volatile memory device according to the present invention will be described in detail with reference to the accompanying drawings.

The programming method according to the present invention can be applied to a nonvolatile memory device, such as a flash memory device, capable of data recording using charge storage. At this time, the flash memory device has a plurality of memory cells having a charge storage layer and a control gate, and the charge storage layer may be a floating gate or a charge trap layer. That is, the memory cell may be one of a floating gate type flash memory cell and a charge trap type flash memory cell.

FIG. 1 schematically shows an example of a flash memory cell in which a program operation can be performed by applying the programming method according to the present invention. This flash memory cell can constitute one memory cell of the NAND type flash memory device described later with reference to FIG.

Referring to FIG. 1, a flash memory cell 10 includes a bulk 11 and a gate structure 20 formed on the bulk 11.

In the bulk 11, first and second impurity regions 13 and 15 doped with a predetermined conductive impurity may be formed. One of the first and second impurity regions 13 and 15 may be used as the drain D and the other as the source S. [

When the flash memory device having the flash memory cell 10 is made to perform the erase operation on a block basis, the bulk 11 may be a p-well (p-well) in FIGS. 9B to 12B have. In addition, the bulk 11 may be a semiconductor substrate on which a flash memory device is formed.

The gate structure 20 includes a tunnel insulating film 21 formed on the bulk 11, a charge storage layer 23 formed on the tunnel insulating film 21 and a blocking insulating film 25 formed on the charge storage layer 23 ). A control gate 27 may be formed on the blocking insulating film 25. In Fig. 1, reference numeral 19 denotes a spacer.

The tunnel insulating film 21 is a film for tunneling charges and is formed on the bulk 11. The first and second impurity regions 13 and 15 are formed in the bulk 11 so as to be electrically connected to the tunnel insulating film 21. The tunneling insulating layer 21 may be formed of a tunneling oxide layer, for example, SiO ₂ or various high-k oxides or oxides thereof.

Alternatively, the tunnel insulating film 21 may be formed of a silicon nitride film, for example, Si ₃ N ₄ . At this time, it is preferable that the silicon nitride film is formed so as not to have a high impurity concentration (that is, the impurity concentration is comparable to the silicon oxide film) and to have an excellent interfacial property with silicon.

Alternatively, the tunnel insulating film 21 may have a bilayer structure of a silicon nitride film and an oxide film.

As described above, the tunnel insulating layer 21 may have a single-layer structure of oxide or nitride, or may have a multi-layer structure of materials having different energy band gaps.

The charge storage layer 23 is an area where information is stored by charge storage. The charge storage layer 23 may be formed of charge traps or formed of a floating gate.

For example, the charge storage layer 23 may be formed to include any one of nitride, high-k dielectrics having high dielectric constant, and nanodots to serve as a charge trap layer. For example, the charge storage layer 23 may be made of a nitride such as Si ₃ N ₄ or a high-k oxide such as HfO ₂ , ZrO ₂ , Al ₂ O ₃ , HfSiON, HfON or HfAlO. In addition, the charge storage layer 23 may include a plurality of nano dots disposed discontinuously as charge trap sites. At this time, the nanodots may be formed in a nanocrystal form. When the charge storage layer 23 is formed to serve as a charge trap layer, the flash memory cell 10 becomes a charge trap flash (CTF) memory cell.

Also, the charge storage layer 23 may be formed to include, for example, polysilicon. In this case, the charge storage layer 23 serves as a floating gate, and the flash memory cell 10 becomes a floating gate type flash memory cell.

The blocking insulating layer 25 may be formed of an oxide layer to prevent the charge from moving upward through the position where the charge storage layer 23 is formed.

The blocking insulating film 25 may be formed of SiO ₂ or a high-k material such as Si ₃ N ₄ , Al ₂ O ₃ , HfO ₂ , Ta ₂ O _5, or ZrO ₂ , which is a material having a higher dielectric constant than the tunneling insulating film 21. ₂ < / RTI > The blocking insulating film 25 may have a multi-layer structure. For example, the blocking insulating film 25 may include a dielectric layer made of a commonly used insulating material such as SiO ₂ and a high dielectric layer formed of a material having a higher dielectric constant than the tunneling insulating film 21, Lt; / RTI >

The control gate 27 may be formed of a metal film. For example, the control gate 27 may be formed of a silicide material such as TaN, aluminum (Al), Ru, or NiSi.

When the electrons are injected into the flash memory cell as described above, injected electrons are stored in the charge storage layer 23 to have a threshold voltage in the programmed state.

Here, the memory cell of the flash memory device has two states, that is, a program state and an erase state. The threshold voltage of the flash memory cell is reduced so that the ON state in which a current flows to the drain connected to the bit line by the voltage supplied to the control gate at the time of reading is referred to as an erase state, And an off state in which no current flows to the drain connected to the bit line by the voltage supplied to the read-out control gate 27 is referred to as a program state.

In FIG. 1, a top gate type flash memory cell in which a control gate is located on the upper side is shown as an example. However, the memory cell of the nonvolatile memory device to which the programming method according to the present invention is applied is not limited to this, And the control gate may be configured as a bottom gate type in which the control gate is located below the charge storage layer.

The programming method according to the present invention can be applied to programming a flash memory device to which the above-described floating gate type or charge trap type flash memory cell is applied.

The programming method according to the present invention can be applied when a supplemental pulse is applied through the lower bulk or channel of the memory cell.

2 schematically shows a circuit diagram of a NAND type flash memory device as an example of a nonvolatile memory device to which the programming method according to the present invention is applied.

Referring to FIG. 2, the flash memory device may include a plurality of cell strings. FIG. 2 shows two cell strings 30 and 31 as an example.

Each cell string includes a plurality of memory cell arrays adapted to share a source / drain with adjacent memory cells. Each memory cell of the cell string may be comprised of either a charge trapped flash memory cell or a floating gate type flash memory cell.

A ground selection transistor (GST), a plurality of memory cells, and a string selection transistor (SST) are connected in series to the cell string. One end of the cell string is connected to a bit line, and the other end is connected to a common source line CSL. The ground selection transistor (GST) is connected to a common source line (CSL), and the string selection transistor (SST) is connected to a bit line.

A word line (WL) is connected to the control gates of the plurality of memory cells in the crossing direction with the cell string, a string selection line (SSL) is connected to the gate of the string selection transistor (SST) And a ground selection line (GSL) is connected to the gate of the ground selection transistor GST. In FIG. 2, each of the strings 30 and 31 has 32 memory cells, and each memory cell is connected to the word lines WL0 to WL31.

The data programmed into the memory cell depends on the voltage of the bit line. If the voltage of the bit line is the power supply voltage (Vcc), the program is inhibited. On the other hand, if the voltage of the bit line is the ground voltage (OV), it is programmed. FIG. 2 illustrates an operation state in which the bit line BLn-1 is provided with a ground voltage (0 V) and the bit line BLn is provided with a power supply voltage Vcc.

In the program operation, the selected word line, e.g., word line WL29, is provided with the program voltage Vpgm. The unselected word lines, e.g., word lines WL31, WL30, WL28-WL0, are provided with a pass voltage (Vpass). The program voltage Vpgm may be stepwise increased by 0.5 V, for example, by setting the base voltage to 16 V, and a voltage of 8-10 V may be provided at the pass voltage Vpass, for example.

The memory cell corresponding to the bit line BLn-1 provided with the ground voltage at the selected word line WL29 is programmed. In Fig. 2, the memory cell A is programmed.

A programming method according to an embodiment of the present invention for programming a nonvolatile memory device is disclosed in FIG.

When a supplementary pulse is applied to a bulk or channel, that is, a bulk (substrate) or a channel pulse modulation, which accelerates the stabilization of the charge during programming, a supplemental pulse is applied to the control gate. That is, the saturation time of the threshold voltage This is because the discharge time after pulse application of the bulk or channel is required. To solve this problem, the present invention applies a recovery pulse through the control gate of the memory cell, for example, following the supplementary pulse. Of course, since the discharge time after applying the pulse to the channel is shorter than the discharge time after applying the pulse to the bulk, the recovery pulse applied after the application of the pulse to the channel can have a voltage value smaller than that of the recovery pulse applied after the pulse is applied to the bulk.

In the case where the nonvolatile memory device to which the programming method according to the embodiment of the present invention is applied is a flash memory device, since the erase operation is performed block by block, the bulk is the p-well p-well, or a semiconductor substrate on which a flash memory device is formed.

A programming method according to an embodiment of the present invention includes supplying a supplementary pulse to the lower bulk or channel of a memory cell to facilitate stabilization of the charge during programming in the ISPP scheme so as to prevent over- To which the recovery pulse is applied. Thus, since the charge is stabilized within a short time and the threshold voltage is stabilized quickly, over-programming can be prevented by once again executing the program due to a judgment error that the threshold voltage is judged to be lower than the desired reference value, The threshold voltage distribution of the programmed state can be greatly reduced compared with the case of programming with the general ISPP method.

3 is a flowchart illustrating a programming method of a nonvolatile memory device according to an embodiment of the present invention. FIG. 4 shows an improved incremental step pulse programming technique (ISPP scheme) according to the programming method of FIG.

3 and 4, a programming method according to an embodiment of the present invention includes applying a programming voltage to a memory cell, and then applying a complementary pulse for promoting charge stabilization through a bulk or channel formed with the memory cell, And then the recovery voltage is applied and then verified by the verify voltage Vref. At this time, it is preferable that the recovery voltage is a positive voltage similar to the verify voltage Vref and is larger than the verify voltage Vref. That is, the recovery voltage may be a positive voltage having the same polarity as the verify voltage and the program voltage. In the case of applying the ISPP method, the programming voltage, the supplementary pulse application, the recovery voltage application, and the verification voltage (Vref) are sequentially increased by gradually increasing the magnitude of the program voltage until the verification using the verification voltage (Vref) The verification operation is repeated.

The programming method according to one embodiment of the present invention when the ISPP scheme is applied will be described in more detail with reference to FIGS. 2 to 4 as follows.

When the program mode is started, a specific word line (WL), for example, a word line WL29 is selected by data input. Thereby, the memory cell connected to the selected word line and the bit line set to the ground voltage, for example, 0 V, is selected, and the program according to the present invention proceeds to the selected memory cell. As described above, FIG. 2 shows an example in which the memory cell A located on the word line WL29 is selected.

A program voltage Vpgm is applied to the selected memory cell and a supplemental pulse is applied to the bulk or channel in step S30 and a recovery voltage is applied in step S40 to verify the verify voltage Vref in step S50. The process of determining whether or not the verification using the verification voltage Vref is passed (S70) is repeated until the verification using the verification voltage Vref is passed while increasing the program voltage Vpgm step by step by? Vpgm.

That is, the n-th ISPP Vpgm is applied to the word line WL. ISPP Vpgm when n = 1 is the basic program voltage applied during ISPP. If the program voltage is increased stepwise by 0.5 V from 16 V, for example, the ISPP Vpgm at n = 1 becomes 16 V.

At this time, since the ISPP Vpgm, the recovery voltage, and the verify voltage Vref are applied to the word line WL, substantially the program voltage, the recovery voltage, and the verify voltage Vref are applied to the selected memory cell through the control gate.

It is determined whether the selected memory cell is programmed to have a desired threshold voltage, that is, a threshold voltage corresponding to the verify voltage Vref (S70). If it is determined that the selected memory cell has passed verification using the verify voltage Vref, The program is terminated (S80).

In the application of the supplemental pulse (S30), the supplemental pulse may be adapted to apply an electric field opposite to the electric field by the program voltage. For example, the supplemental pulse may be a DC supplemental pulse having the opposite polarity to the program voltage, as shown in FIG. At this time, since the program voltage may be a positive voltage having the same polarity as the recovery voltage and the verify voltage, the supplemental pulse may be a voltage having a polarity opposite to the program voltage, the recovery voltage, and the verify voltage. Of course, in the present invention, since the DC supplemental pulse is applied to the bulk or the channel, this DC supplemental pulse is applied with a positive voltage for the bulk or channel. At this time, the magnitude of the supplementary pulse is preferably smaller than the magnitude of the program voltage.

5A shows an embodiment in which a supplemental pulse is applied through a bulk when a program voltage, a recovery voltage, and a verify voltage are applied through the selected word line WL, i.e., the control gate of the selected memory cell.

The supplemental pulse may be applied through the bulk of the nonvolatile memory element in which a plurality of memory cells are formed as shown in FIG. 5A.

As described above, when the supplementary pulse is applied to the bulk, the charges injected into the charge storage layer are uniformly distributed at a high rate in the charge storage layer. Accordingly, the time from when the charges are injected into the charge storage layer to when the threshold voltage of the memory cell becomes constant can be significantly shortened, compared with the case where the supplementary pulse is not applied.

Further, since the recovery pulse Vr1 is applied through the control gate of the memory cell following the supplemental pulse, the discharge time required by applying the supplemental pulse to the bulk can be shortened, and the threshold voltage saturation time can be greatly shortened.

5B shows an embodiment in which a supplemental pulse is applied through a channel when a program voltage, a recovery voltage and a verify voltage are applied through the selected word line WL, i.e., the control gate of the selected memory cell.

The supplemental pulse may be applied through a channel of a nonvolatile memory element in which a plurality of memory cells are formed as shown in FIG. 5B.

When a supplementary pulse is applied to the channel as described above, the charges injected into the charge storage layer are uniformly distributed at a high rate in the charge storage layer. Accordingly, the time from when the charges are injected into the charge storage layer to when the threshold voltage of the memory cell becomes constant can be significantly shortened, compared with the case where the supplementary pulse is not applied.

Further, since the recovery pulse Vr2 is applied through the control gate of the memory cell following the supplemental pulse, the discharge time required by applying the supplemental pulse to the channel can be shortened, and the threshold voltage saturation time can be greatly shortened.

Of course, since the discharging time after applying the pulse to the channel is shorter than the discharging time after applying the pulse to the bulk, the recovery pulse Vr2 applied after the pulse is applied to the channel is smaller than the recovery pulse Vr1 applied after the pulse is applied to the bulk Lt; / RTI >

6 is a flowchart illustrating a method of programming a nonvolatile memory device according to another embodiment of the present invention. FIG. 7 shows an improved incremental step pulse programming technique (ISPP scheme) according to the programming method of FIG. The programming method according to another embodiment of the present invention is characterized by comparing the programming method according to the embodiment of the present invention with the verification voltage in two steps so that only when the memory cell reaches a state exceeding a certain threshold voltage By adding the supplementary pulse and the recovery voltage, it is possible to minimize the program time increase due to the supplementary pulse and the recovery voltage addition.

6 and 7, a programming method according to the present invention includes a first programming step (S100) of applying a program voltage to a memory cell and then verifying with a first verification voltage (Vref '), A step S200 of applying a supplemental pulse for promoting the stabilization of the charge through the bulk or the channel for the memory cell which has passed the verification using the reference voltage Vref ' (S300) with a second verify voltage (Vref) greater than the first verify voltage (Vref ') after application of the recovery voltage.

Further, the programming method according to the present invention further includes a second programming step (step S400) of determining whether or not the verification using the second verification voltage (Vref) has been passed (S400) (S500). In the second programming step (S500), a programming voltage is applied to the memory cell, followed by applying a supplemental pulse for promoting charge stabilization through the bulk or channel, then applying a recovery voltage, and then applying a second verify voltage Vref).

In the case of applying the ISPP method, in the first programming step S100, the magnitude of the program voltage is increased step by step until the verification using the first verify voltage Vref 'is passed, In the second programming step S500, the program voltage (Vref ') is gradually increased while gradually increasing the magnitude of the program voltage until the verification using the second verify voltage (Vref) And the verify operation by the second verify voltage Vref is repeated.

The programming method according to another embodiment of the present invention when the ISPP scheme is applied will be described in more detail with reference to FIGS. 2, 6, and 7. FIG.

When the program mode is started, a specific word line (WL), for example, a word line WL29 is selected by data input. Thereby, the memory cell connected to the selected word line and the bit line set to the ground voltage, for example, 0 V, is selected, and the program according to another embodiment of the present invention proceeds to the selected memory cell. As described above, FIG. 2 shows an example in which the memory cell A located on the word line WL29 is selected.

The program corresponding to the first programming step S100 is performed on the selected memory cell. In the first programming step S100, the program voltage Vpgm is applied (S110), the first verification voltage Vref 'is verified (S130), and the verification using the first verification voltage Vref' (S150) is repeated until the verification using the first verify voltage (Vref ') is passed while increasing the program voltage (Vpgm) step by step by ΔVpgm.

That is, the n-th ISPP Vpgm is applied to the word line WL. ISPP Vpgm when n = 1 is the basic program voltage applied during ISPP. If the program voltage is increased stepwise by 0.5 V from 16 V, for example, the ISPP Vpgm at n = 1 becomes 16 V.

At this time, since the ISPP Vpgm and the first verify voltage Vref 'are applied to the word line WL, substantially the program voltage and the first verify voltage Vref' are applied to the selected memory cell through the control gate.

If it is determined in the first programming step S100 that the verification using the first verify voltage Vref 'has been passed (S150), a supplemental pulse for promoting the stabilization of the charge in the bulk or channel is applied (S200). Then, a recovery voltage is applied to the selected memory cell through the word line WL (S250). The selected memory cell is then verified (S300) with a second verify voltage Vref that is greater than the first verify voltage Vref ', and the selected memory cell is tested for a desired threshold voltage, (S400). If the threshold voltage is not equal to the threshold voltage,

If the memory cell selected in the program determination step (S400) passes the determination using the second verify voltage (Vref), the program is terminated (S600). If the memory cell selected in the program determination step (S400) does not pass the determination using the second verify voltage (Vref), the second programming step (S500) proceeds further.

The second programming step S500 includes applying (S510) the n-th ISPP Vpgm to the word line WL, applying a supplemental pulse through the bulk or channel (S530), recovering through the word line WL (S540), verifying (S550) the second verify voltage (Vref) through the word line (WL), and determining whether the verification using the second verify voltage (Vref) has passed (S570). The second programming step S500 is repeated until the verification using the second verification voltage Vref is passed while increasing the program voltage Vpgm stepwise by DELTA Vpgm. If it is determined in the second programming step (S500) that the selected memory cell has passed the verification using the second verify voltage (Vref), the program is terminated (S600).

At this time, the ISPP Vpgm first applied to the word line WL in the second programming step (S500) may be increased by DELTA Vpgm than ISPP Vpgm lastly applied in the first program step (S100). Since the ISPP Vpgm, the recovery voltage and the second verify voltage Vref are applied to the word line WL in the second programming step S500, substantially the program voltage, the recovery voltage and the second verify voltage Vref are applied to the selected memory Is applied to the cell through the control gate.

In the step of applying the supplemental pulses (S200) (S530), the supplemental pulse may be one adapted to apply an electric field opposite to the electric field by the program voltage. For example, the supplemental pulse may be a DC supplemental pulse having an opposite polarity to the program voltage, as shown in FIG. Of course, in the present invention, since the DC supplemental pulse is applied to the bulk or the channel, this DC supplemental pulse is applied with a positive voltage for the bulk or channel. At this time, the magnitude of the supplementary pulse is preferably smaller than the magnitude of the program voltage.

FIG. 8A shows a case where the program voltage, the recovery voltage and the first and second verify voltages Vref 'and Vref are applied through the selected word line WL, that is, the control gate of the selected memory cell, Lt; / RTI >

The replenishment pulse may be applied through the bulk of the nonvolatile memory element in which a plurality of memory cells are formed as shown in FIG. 8A.

8B shows a state in which the program voltage, the recovery voltage and the first and second verify voltages Vref '(Vref) are applied through the selected word line WL, that is, the control gate of the selected memory cell, Lt; / RTI >

The supplemental pulse may be applied through a channel of a non-volatile memory element in which a plurality of memory cells are formed as shown in FIG. 8B. Similarly to FIGS. 5A and 5B, in the case of FIGS. 8A and 8B, Since the discharge time after the application of the pulse is shorter than the discharge time after the application of the pulse to the bulk, the recovery pulse Vr2 applied after application of the pulse to the channel may have a voltage value smaller than the recovery pulse Vr1 applied after application of the pulse to the bulk.

8A and 8B show an example in which the supplementary pulse is a DC pulse of the opposite polarity to the program voltage, which is only an example, and the supplementary pulse type is not limited thereto. For example, the supplemental pulse may be an AC pulse.

When a supplementary pulse is applied every step of applying ISPP Vpgm, the program time is increased by multiplying the number of times of application of the supplementary pulse by the application time of the supplementary pulse. In the programming method according to another embodiment of the present invention, in order to minimize such program time increase, only when the memory cell passes the verification using the first verify voltage Vref ' . The first verify voltage Vref 'is set in consideration of the threshold voltage difference between the verification and the stabilization.

The present inventors have found that the threshold voltage distribution of memory cells for the same measurement time is in the range of about 0.1V, and the threshold voltage value of each memory cell is varied from 0.5μs to 350μs by 0.528μV 0.01V over time. It was found that the threshold voltage value variation of the memory cell at the time of verification and stabilization is about 0.528V, and the difference of the threshold voltage value variation of the memory cells is within 0.03V.

As described above, the difference in the threshold voltage between the verify time and the stabilized time becomes a predetermined value, for example, about 0.528 V within the error range of 0.03 V. Therefore, the first verify voltage Vref 'can be determined in consideration of this.

Preferably, the first verify voltage Vref 'may be set to a value smaller than the second verify voltage Vref by a threshold voltage difference during verification and after the stabilization.

That is, the first verify voltage Vref 'may be set to Vref' = Vref-xV (V means volt). At this time, since the difference in threshold voltage value between verification and stabilization is within 1 V, x can be set to 0 <x <1. Here, x may vary within the above range depending on the program voltage or the recording page. Since the program is made on a word line basis, the page corresponds to a word line.

Meanwhile, the nonvolatile memory device to which the programming method according to the embodiment of the present invention is applied has a NAND array structure (see FIG. 2) of a plurality of memory cells formed on the bulk, and the programming method according to the embodiment of the present invention The selected memory cell programmed by the memory cell array may be selected from a plurality of memory cells arranged in a NAND array structure.

At this time, the bulk may be a p-well formed in a semiconductor substrate, and the plurality of memory cells may be formed as an array so as to share a source / drain with the p-well.

2, the NAND array structure includes a plurality of strings each including a plurality of memory cell arrays, a ground selection transistor and a string selection transistor on both sides of each string, and the program voltage, the verify voltage And the complementary pulse application of the reverse polarity to the recovery voltage apply a voltage greater than 0 V to a common source and a ground selection transistor electrically connected to the string where the selected memory cell is located and apply an operation to apply a ground voltage to the selected memory cell Lt; / RTI &gt;

Figs. 9A and 9B, Figs. 10A and 10B, Figs. 11A and 11B, Figs. 12A and 9B and 12B are diagrams showing one string of the NAND type flash device to which the programming method according to the embodiment of the present invention is applied, In the bit line direction. FIGS. 9A and 9B show an operation state in which a program pulse is applied to a selected word line, FIGS. 10A and 10B show an operation state in which a supplemental pulse is applied to a channel, FIGS. 10C and 10D show a p- 11A and 11B show an operation state in which a recovery pulse is applied to a selected word line, and FIGS. 12A and 12B show a state in which a verify pulse is applied to a selected word line It shows the operation status. 9B to 12B show an example in which only five memory cells are provided in a string for convenience. 9B to 12B, elements having the same functions as those in the flash memory cell described with reference to FIG. 1 are denoted by the same reference numerals, and repetitive description thereof is omitted.

In the NAND type flash memory device, one block includes a plurality of cell strings as shown in FIG. 2. When the erase operation is performed on a block-by-block basis, the block is formed in the p-well p- well 30 may be provided. 9B to 12B, for example, a plurality of memory cells 10 arrays are formed in a p-well 30 (p-well) formed in a semiconductor substrate, and between adjacent cells arranged in series in one string Source / drain regions 13 and 15 are shared. The source / drain regions 13 and 15 are formed in the p-well 30. When a plurality of memory cell strings constituting a block are formed in the p-well 30, the bulk to which the supplemental pulse is applied when applying the programming method according to the embodiment of the present invention described with reference to Figs. 5A and 8A, And may correspond to the p-well 30. Further, the bulk to which the supplemental pulse is applied may be a substrate on which the flash memory device is formed.

9B to 12B, SG represents the selected gate of the string selection transistor (GST) and the string selection transistor (SST) of the string where the program memory cell (A) is located. In FIGS. 9B to 12B, the SCG (Selected Control Gate) represents a selected control gate of a memory cell selected as a program target, and an unselected control gate of a memory cell not selected as a UCG (Un-selected Control Gate) .

9A and 9B, the operating state of one string of the NAND type flash memory device for applying the program pulse to the selected word line is as follows.

The program voltage Vpgm is provided to the selected control gate 27 (SCG) of the selected memory cell, for example, the memory cell A selected through the word line WL29.

Here, the selected memory cell A refers to a memory cell that is on a string to which a bit line voltage of 0 V is applied so as to be programmable during application of a program pulse and is connected to a selected word line.

The pass voltage Vpass is provided to the control gate UCG of the memory cell which is not selected through the unselected word lines WL31, WL30 and WL28-WL0 and the potential of the ground selection transistor GST through the ground selection line GSL The selected gate SG is provided with the ground voltage 0V and the selected gate SG of the string selection transistor SST is provided with the power supply voltage Vcc through the string selection line SSL. The drain is provided with a ground voltage (0V) through the bit line electrically connected to the string where the program memory cell is located. The common source 37 through the common source line CSL is provided with a power supply voltage Vcc to prevent drain-induced leakage. The power supply voltage Vcc may be about 2-3 V, for example.

The program voltage Vpgm may be stepwise increased by 0.5 V, for example, by setting the base voltage to 16 V, and a voltage of 8-10 V may be provided at the pass voltage Vpass, for example.

The operation state of the NAND type flash memory state for applying the supplemental pulse to the channel after applying the program pulse to the program target memory cell A through the selected word line as shown in FIGS. 9A and 9B is shown in FIGS. 10A and 10B &Lt; / RTI &gt;

10A and 10B, a power source voltage Vcc is applied to the common source 37 through the common source line CSL to raise the channel voltage, and the selection gate SG That is, the power supply voltage Vcc is also applied to the gate of the ground selection transistor GST through the ground selection line GSL.

In this manner, the program voltage applied to the selected word line is lowered from Vpgm to 0 V while the power supply voltage Vcc is applied to the common source 37 and the selection gate of the common source 37. (0V) to the selected control gate (SCG) of the selected memory cell (A) connected to the selected word line, e.g., word line WL29.

The unselected control gates UCG of the memory cells not selected through the unselected word lines WL31, WL30, WL28-WL0 are provided with the pass voltage Vpass. The selection gate SG of the string selection transistor SST is provided with the ground voltage (0 V) through the string selection line SSL.

The drain may be provided with a power supply voltage Vcc or a ground voltage (0V) through a bit line electrically connected to a string where the program target memory cell A is located.

9A and 9B, a program pulse is applied to the program target memory cell A through the selected word line, and an operation state of the NAND flash memory state for applying a supplemental pulse to the bulk (p-well) May be the same as in Figs. 10C and 10D.

Referring to Figs. 10C and 10D, a supplemental pulse is applied to the bulk (p-well).

At this time, a ground voltage (0 V) is applied to the common source 37 through the common source line CSL and the ground selection voltage Vs is applied to the common source 37 through the selection gate SG, A ground voltage (0 V) may be applied or floating to the gate of the transistor GST. Then, the program voltage applied to the selected word line can be lowered from Vpgm to 0V. That is, it can provide a ground voltage (0V) to the selected control gate (SCG) of the selected memory cell, for example, the selected memory cell A connected to the word line WL29. The ground voltage (0V) may also be provided to unselected control gates UCG of memory cells not selected through unselected word lines WL31, WL30, WL28-WL0. The grounding voltage (0 V) may be supplied or floated to the selection gate SG of the string selection transistor SST through the string selection line SSL. Then, the drain can be provided with a ground voltage (0 V) or can be floated through a bit line electrically connected to the string where the memory cell A to be programmed is located.

10A and 10B, a supplementary pulse is applied to the channel, or a supplementary pulse is applied to the bulk (p-well) as shown in FIGS. 10C and 10D, and then a NAND type flash The operating state of the memory device is the same as in FIGS. 11A and 11B.

Referring to FIGS. 11A and 11B, a selected control line (SCG) of a selected memory cell, for example, a memory cell A selected through word line WL29, is provided with a recovery pulse voltage Vrec. The read voltage Vread is provided to the unselected control gates UCG of the memory cells not selected through the unselected word lines WL31, WL30, WL28-WL0.

A read voltage Vread is provided to the selection gate of the ground selection transistor GST through the ground selection line GSL and a read voltage Vread is applied to the selection gate of the string selection transistor SST through the string selection line SSL. / RTI &gt;

The drain is provided with a ground voltage (0 V) through a bit line electrically connected to a string where the programmed memory cell A is located. The common source 37 is supplied with the ground voltage (0 V) through the common source line CSL. The read voltage Vread may be, for example, about 5-6V as a pass voltage at the time of reading.

The operating state of the NAND type flash memory device for applying the verify pulse to the selected word line after applying the recovery pulse to the selected word line as shown in FIGS. 11A and 11B is as shown in FIGS. 12A and 12B.

12A and 12B, a verify pulse voltage Vverify is provided to a selected control gate SCG of a selected memory cell, for example, a memory cell A selected through a word line WL29. The read voltage Vread is provided to the unselected control gates UCG of the memory cells not selected through the unselected word lines WL31, WL30, WL28-WL0. The selection gate SG of the ground selection transistor GST is provided with the read voltage Vread through the ground selection line GSL and the selection gate SG of the string selection transistor SST is provided through the string selection line SSL. A lead-out voltage Vread is provided. A bit line voltage Vbl is provided to the drain through a bit line electrically connected to the string where the program target memory cell A is located. The common source 37 is supplied with the ground voltage (0 V) through the common source line CSL. The read voltage Vread may be, for example, about 5-6V. The bit line voltage Vbl may be, for example, about 1-2 V as a bit line voltage at the time of verification. Hereinafter, the effect of improving the threshold voltage dispersion according to the application of the supplementary pulse and the recovery voltage in the programming method according to the present invention Will be described in comparison with a conventional programming method using a general ISPP method and a case where only supplementary pulses are applied to a control gate and a bulk (for example, a p-well or a substrate).

FIG. 13 shows a voltage pulse waveform diagram applied to a selected word line at the time of programming in a general ISPP method and a threshold voltage change at the time of programming a charge trap flash (CTF) memory cell with the ISPP voltage pulse. FIGS. 14A and 14B show a program scheme and a threshold voltage distribution of a memory cell when applying the conventional programming method. FIG.

Referring to FIG. 13, according to a general ISPP method, a program voltage is applied to a word line to program a selected memory cell, and then a verify voltage Vver is applied to verify the program. If it is determined that the selected memory cell does not reach the desired threshold voltage as a result of the verification, the program voltage is increased again by increasing the programming voltage by a predetermined magnitude, and the verification is again performed. In the general ISPP system as described above, the verify operation is performed once per one program operation while gradually increasing the program voltage until the memory cell is programmed to reach the set threshold voltage.

In the general ISPP method, the program voltage is gradually increased from 0.5 V to 1 V, for example, and the program voltage application operation and the verify operation are repeated alternately.

As described above, in the program, the charge trap type flash memory cell has a transient threshold voltage (transient Vth) characteristic in which the threshold voltage (Vth) increases with time after application of the program pulse. Therefore, even if it is determined that the threshold voltage is lower than the verify voltage Vref when programming with a program pulse of, for example, 17V, if the threshold voltage gradually increases with time and the threshold voltage exceeds the verify voltage Vref .

In this case also, as can be seen from Fig. 14A, in the verify operation, it is determined that the program fails (program fail) and the program pulse is again added, and eventually the memory cell is over programmed. Therefore, as shown in FIG. 14B, the threshold voltage distribution of the memory cell is larger than in the case where there is no threshold voltage change with time.

As described above, a sufficiently programmed memory cell at the time of programming using the general ISPP method is judged as a program failure at the time of verification due to the characteristic of the transient threshold voltage (transient Vth) and may be additionally programmed, The probability of occurrence becomes large.

FIG. 15 is a graph showing a state in which the threshold voltage of the memory cell changes after application of the program voltage when there is no supplemental pulse, that is, DC modulation. 15, the vertical axis on the left side represents the threshold voltage variation (Vth).

Referring to FIG. 15, consider a case where a program pulse (pgm pulse) of 13 V is applied for 100 μs, and then the memory cell is read with a read voltage (Vread) of 4.5 V. At this time, the amount of variation in the threshold voltage until saturation becomes about 0.1 V from the point of time when 40 μs elapses after application of the program voltage, and becomes about 0.01 V from the point of 500 μs elapse.

As described above, since it takes a long time to saturate the threshold voltage of the memory cell after application of the program voltage, it is necessary to shorten the time taken for the memory cell to reach the threshold voltage saturation state.

In the programming method according to the embodiment of the present invention, a supplementary pulse is applied through the bulk and a recovery voltage is applied to the selected memory cell to shorten the time for the threshold voltage of the memory cell to reach the saturated state.

FIG. 16 is a timing chart showing the change of the threshold voltage of the memory cell according to the application time of the DC supplementary pulse at the time of the gate pulse modulation for applying the DC pulse to the memory cell through the control gate, Fig. In Fig. 16, the vertical axis on the left side represents the threshold voltage variation (DELTA Vth).

Referring to FIG. 16, consider a case where a program voltage of 13V is applied for 100μs, a DC supplementary pulse of -2.9V is subsequently applied, and a memory cell is read by a read voltage (Vread) of 4.5V.

15 and 16, it can be seen that the amount of variation in the threshold voltage greatly decreases when the DC supplemental pulse is applied for 10 μs, 30 μs, and 50 μs. For example, when a DC replenishment pulse of -2.9V is applied for 30μs, the threshold voltage variation (ΔVth) is about 10mV after 40 μs has elapsed after application of the program voltage, and when the DC replenishment pulse is not applied And the threshold voltage variation (DELTA Vth) is greatly reduced compared with about 0.1 V.

As can be seen from the comparison of Fig. 15 and Fig. 16, the application of the DC supplemental pulse of the opposite polarity to the program voltage can greatly shorten the time for which the threshold voltage is stabilized.

Thus, when the DC supplemental pulse is applied to the selected memory cell through the word line (control gate), the time during which the threshold voltage is stabilized can be greatly shortened. However, in order to apply the DC supplemental pulse as a negative pulse through the selected word line (control gate), it is required to further include a voltage generator capable of generating a negative voltage in the circuit of the nonvolatile memory.

Therefore, it can be considered that, after application of the program voltage, the DC supplementary pulse is applied as a positive pulse through the bulk. However, in this case, there is a problem that the saturation time of the threshold voltage becomes relatively longer than when the supplemental pulse is applied to the control gate. Of course, even when the DC supplemental pulse is applied through the bulk, the threshold voltage saturation time can be greatly reduced compared with the conventional programming method in which the supplemental pulse is not applied at all.

Fig. 17 shows a comparison of the threshold voltage change with time when the positive pulse is not applied to the bulk and when the positive pulse is applied to the bulk. The change in the threshold voltage at the time of application of the positive pulse in FIG. 17 is a result obtained by applying the programming voltage 15V for 100 μs and then applying the positive pulse 9 V for 5 μs to the bulk.

17, when the positive pulse is applied to the bulk, the saturation time is shortened. Nevertheless, there is a phenomenon that the threshold voltage Vth gradually decreases with time after application of the positive pulse, and the saturation time It is relatively long, about 50-100 μs. This is because the bulk requires a discharge time after applying a positive voltage.

FIG. 18 shows a comparison of the threshold voltage change with time of the time when a recovery voltage is applied after applying a positive pulse to the bulk, as in the programming method according to the present invention, with the result of FIG.

In FIG. 18, the saturated Vth represents a threshold voltage measured in a saturated state after a delay of about 100 ms. The threshold voltage for the comparative example was measured by applying a programming voltage and then applying a DC supplemental pulse to the bulk and then applying a read voltage. The conventional threshold voltage is measured by applying a read voltage after applying a program voltage to the bulk without applying a DC supplemental pulse. The graph of the threshold voltage change for the comparative example in FIG. 18 and the conventional example is the same as that shown in FIG.

The threshold voltage for the present invention was measured by applying a DC supplemental pulse to the bulk after applying the program voltage, applying a recovery voltage of 12 V for 10 μs, and then applying a read voltage.

As can be seen from Figs. 17 and 18, in the comparative example, it takes about 100 mu s for the threshold voltage to drop. On the other hand, as in the present invention, when the recovery voltage is additionally applied to the selected memory cell for about 5 to 10 [micro] s after the DC replenish pulse applied through the bulk, the time for saturation of the threshold voltage is larger than that of the comparative example Can be shortened.

In the programming method according to the present invention, the supplemental pulses applied through the bulk may be, for example, a positive voltage (in terms of bulk) of about 10 V or less. In addition, the recovery voltage applied to the memory cell via the supplemental pulse followed by the word line may be in the form of a pulse, for example, a positive voltage of about 3-10V (in terms of the control gate).

As described above, according to the programming method of the present invention, stabilization of the charge is promoted by adding the recovery voltage to the supplementary pulse applied through the bulk or the channel so that the threshold voltage reaches the saturated state in a short time, An over program due to a judgment error can be prevented, and the threshold voltage dispersion can be improved.

In addition, when a supplemental pulse is applied to each ISPP, it is necessary to increase the program time by the number of times of applying the supplemental pulse (t supplementary pulse? M). In another embodiment of the present invention, Since the supplemental pulse is applied only after passing through the verification using the reference voltage Vref ', the program voltage can be reduced, and the programming time can be reduced more effectively than when the supplemental pulse is applied to the ISPP every time.

In addition, by applying the programming method according to the present invention as described above, since the threshold voltage value distribution of the memory cells corresponding to each recording state is small, it is possible to separately recognize the recording states in the multi-level cell operation.

In the above description, the programming method according to the present invention is applied to a flash memory device having a charge trap type flash memory cell or a floating gate type flash memory cell, but the present invention is not limited thereto. The programming method according to the present invention is applicable to all nonvolatile memory devices having a problem of charge stabilization.

FIG. 1 schematically shows an example of a flash memory cell in which a program operation can be performed by applying the programming method according to the present invention.

2 schematically shows a circuit diagram of a NAND type flash memory device as an example of a nonvolatile memory device to which the programming method according to the present invention is applied.

3 is a flowchart illustrating a programming method of a nonvolatile memory device according to an embodiment of the present invention.

FIG. 4 shows an improved incremental step pulse programming technique (ISPP scheme) according to the programming method of FIG.

5A shows an embodiment in which a supplemental pulse is applied through a bulk when a program voltage, a recovery voltage, and a verify voltage are applied through the selected word line WL, i.e., the control gate of the selected memory cell.

5B shows an embodiment in which a supplemental pulse is applied through a channel when a program voltage, a recovery voltage and a verify voltage are applied through the selected word line WL, i.e., the control gate of the selected memory cell.

6 is a flowchart illustrating a method of programming a nonvolatile memory device according to another embodiment of the present invention.

FIG. 7 shows an improved incremental step pulse programming technique (ISPP scheme) according to the programming method of FIG.

FIG. 8A shows a case where the program voltage, the recovery voltage and the first and second verify voltages Vref 'and Vref are applied through the selected word line WL, that is, the control gate of the selected memory cell, Lt; / RTI &gt;

8B shows a state in which the program voltage, the recovery voltage and the first and second verify voltages Vref '(Vref) are applied through the selected word line WL, that is, the control gate of the selected memory cell, Lt; / RTI &gt;

9A and 9B show an operation state in which a program pulse is applied to a selected word line.

FIGS. 10A and 10B show an operation state in which a supplemental pulse is applied to a channel, and FIGS. 10C and 10D show an operation state in which a supplemental pulse is applied to a bulk (p-well).

11A and 11B show an operation state in which a recovery pulse is applied to a selected word line.

12A and 12B show an operation state in which a verify pulse is applied to a selected word line.

13 shows a voltage pulse waveform diagram applied to a selected word line at the time of programming in a general ISPP method and a threshold voltage change at the time of programming a charge trap flash (CTF) memory cell with the ISPP voltage pulse.

FIGS. 14A and 14B show a program scheme and a threshold voltage distribution of a memory cell when applying the conventional programming method. FIG.

15 is a graph showing a state in which the threshold voltage of the memory cell changes after application of the program voltage when there is no DC modulation.

FIG. 16 is a graph showing the relationship between the voltage applied to the memory cell and the threshold voltage of the memory cell according to the application time of the DC supplementary pulse during the gate pulse modulation for applying the DC pulse to the memory cell through the control gate, Fig.

Fig. 17 shows a comparison of the threshold voltage change with time when the positive pulse is not applied to the bulk and when the positive pulse is applied to the bulk.

FIG. 18 shows a comparison of the threshold voltage change with time of the time when a recovery voltage is applied after applying a positive pulse to the bulk, as in the programming method according to the present invention, with the result of FIG.

Claims (23)

Applying a program voltage to the memory cell; Applying a supplemental pulse to promote stabilization of charge after application of the program voltage; Applying a recovery voltage to the memory cell following the supplemental pulse; And applying a verify voltage after the recovery voltage is applied to verify the nonvolatile memory device. The nonvolatile memory element programming method according to claim 1, wherein the supplemental pulse is adapted to apply an electric field of an opposite polarity to an electric field by the program voltage. 2. The nonvolatile memory device programming method according to claim 1, wherein the supplemental pulse is applied through a bulk or a channel in which the memory cell is formed. The nonvolatile semiconductor memory device according to claim 1, further comprising: a nonvolatile memory that repeats a program voltage application, a supplemental pulse application, a recovery voltage application, and a verify operation by a verify voltage while gradually increasing the magnitude of the program voltage until the verification using the verify voltage is passed Memory element programming method. delete delete delete The nonvolatile memory device according to claim 1, wherein the nonvolatile memory element has a NAND array structure of a plurality of memory cells formed on a bulk, Wherein the memory cell is a selected memory cell among a plurality of memory cells arranged in a NAND array structure. 9. The method of claim 8, wherein the bulk is a p-well formed in a semiconductor substrate, and the plurality of memory cells are formed in an array to share a source / drain in the p-well. 10. The semiconductor memory device according to claim 9, wherein the NAND array structure includes a plurality of strings each including a plurality of memory cell arrays, a ground selection transistor on both sides of each string, and a string selection transistor, The complementary pulse application of the opposite polarity to the program voltage, verify voltage and recovery voltage applies a voltage greater than 0 V to a common source and a ground selection transistor electrically connected to the string where the selected memory cell is located, And a voltage is applied to the nonvolatile memory element. (A) a first programming step of applying a program voltage to a memory cell and subsequently verifying with a first verify voltage; (B) applying a supplemental pulse to facilitate the stabilization of the charge for the memory cell which has passed the verification using the first verify voltage; (C) applying a recovery voltage to the memory cell following the supplemental pulse; (D) verifying the second verify voltage to be greater than the first verify voltage after applying the recovery voltage. delete 12. The method of claim 11, wherein the recovery voltage is a positive voltage that is greater than the first and second verify voltages and is the same polarity as the first and second verify voltages and the program voltage, Wherein the supplemental pulse is opposite in polarity to the program voltage, the recovery voltage, and the first and second verify voltages. delete 12. The method of claim 11, further comprising: applying a programming voltage to the memory cell when the verification using the second verify voltage in step (d) fails, and supplying a supplemental pulse for promoting charge stabilization to a bulk or channel And applying a recovery voltage and verifying again with the second verify voltage. &Lt; Desc / Clms Page number 21 &gt; delete delete delete delete delete delete delete delete

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