KR101429920B1 - Manufacturing method of thin film transistor substrate - Google Patents

Abstract

The present invention relates to a method of manufacturing a thin film transistor substrate which can simplify the process.

According to another aspect of the present invention, there is provided a method of manufacturing a thin film transistor substrate, including: forming a gate electrode pattern including a gate line, a gate electrode, a storage electrode and a gate lower electrode on a lower substrate; Forming a data metal pattern including a data line, a source electrode and a drain electrode, a data lower electrode on the insulating film, and a semiconductor pattern superimposed thereunder along the data metal pattern; Forming first and second photoresist patterns having different thicknesses on a protective film and a metal pass layer on a gate insulating film having a pattern formed thereon; forming gate contact holes and data contact holes using the first and second photoresist patterns; Forming a pixel contact hole, ashing the first and second photoresist patterns, Forming a lift-off path in an etching process using the first photoresist pattern thinned by the ashing process; and forming a transparent conductive film on the substrate including the first photoresist pattern, And forming a transparent conductive pattern including a pixel electrode, a gate upper electrode, and a data upper electrode by lifting-off the photoresist pattern and the transparent conductive film thereon.

Overhang, lift-off pass layer, mask process

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a thin film transistor substrate,

The present invention relates to a method of manufacturing a thin film transistor substrate which can simplify the process.

The liquid crystal display device displays an image by adjusting the light transmittance of liquid crystal having dielectric anisotropy using an electric field. Such a liquid crystal display device displays an image by adjusting the light transmittance of the liquid crystal using an electric field.

The liquid crystal display device includes a thin film transistor substrate and a color filter substrate which are bonded together to face each other, a spacer for keeping the cell gap constant between the two substrates, and a liquid crystal filled in the cell gap.

The color filter substrate is composed of a color filter for color implementation, a black matrix for preventing light leakage, and an alignment film coated thereon for liquid crystal alignment.

The thin film transistor substrate has a thin film transistor formed in each cell region defined by the intersection of a gate line and a data line, and a pixel electrode connected to the thin film transistor.

A number of mask processes are used to form such a thin film transistor substrate. One mask process includes a plurality of processes such as a thin film deposition process, a cleaning process, a photolithography process, an etching process, and the like.

Accordingly, a number of processes are required to form a thin film transistor substrate, which increases the manufacturing cost due to an increase in the number of processes.

Accordingly, since a plurality of processes are required to form a thin film transistor substrate, a process simplification technique is required to reduce the manufacturing cost.

In order to solve the above problems, the present invention provides a method of manufacturing a thin film transistor substrate which can simplify the process.

According to an aspect of the present invention, there is provided a method of manufacturing a thin film transistor substrate, including: forming a gate electrode pattern including a gate line, a gate electrode, a storage electrode, and a gate lower electrode on a lower substrate; A gate insulating film is formed on a lower substrate on which the gate electrode pattern is formed, and a data metal pattern including a data line, a source and a drain electrode, and a data lower electrode is formed thereon, and a semiconductor pattern ; ≪ / RTI > Forming a protective film and a lift off pass layer on the gate insulating film on which the data metal pattern and the semiconductor pattern are formed, first and second photoresist patterns having different thicknesses from each other; Forming a gate contact hole, a data contact hole, and a pixel contact hole by at least one etching process using the first and second photoresist patterns, ashing the first and second photoresist patterns; Forming a lift-off path in an etching process using the first photoresist pattern thinned by the ashing process; Forming a transparent conductive film on the substrate including the first photoresist pattern and then lifting off the first photoresist pattern and the transparent conductive film on the first photoresist pattern by a strip process to form a pixel electrode, And forming a transparent conductive pattern including the transparent conductive pattern.

The method of manufacturing a thin film transistor substrate according to the present invention can form a transparent conductive pattern by patterning a transparent conductive film in a lift-off process of a photoresist pattern used in patterning a thin film transistor substrate protective film.

Thus, the process for forming the thin film transistor substrate can be formed by the third mask process, thereby simplifying the process.

In addition, the method of manufacturing a thin film transistor substrate according to the present invention can further prevent the damage of the lower film by forming a lift-off pass layer in the third mask process and forming a lift-off path of the overrun structure by a wet process .

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to FIGS. 1 to 6F.

FIG. 1 is a plan view showing a thin film transistor substrate according to an embodiment of the present invention. FIG. 2 is a cross-sectional view of the thin film transistor substrate shown in FIG. 1 taken along the line I-I ', II-II', III- Sectional view taken along the line V-V 'in Fig.

The thin film transistor substrate shown in FIGS. 1 and 2 includes a thin film transistor 130 connected to each of the gate line 102 and the data line 104, a pixel electrode 122 formed in a pixel region provided with the crossing structure, A gate pad 150 connected to the gate line 102, a data pad 160 connected to the data line 104, a storage capacitor 160 for preventing variations in the pixel voltage signal charged in the pixel electrode 122, (Cst).

The thin film transistor 130 causes a pixel signal supplied to the data line 104 to be charged and held in the pixel electrode 122 in response to a scan signal supplied to the gate line 102. The thin film transistor 130 includes a gate electrode 106, a source electrode 108, a drain electrode 110, an active layer 114, and an ohmic contact layer 116.

The gate electrode 106 is connected to the gate line 102 so that a scan signal from the gate line 102 is supplied. The source electrode 108 is connected to the data line 104 so that the pixel signal from the data line 104 is supplied. The drain electrode 110 is formed to face the source electrode 108 with the channel portion of the active layer 114 interposed therebetween and supplies a pixel signal from the data line 104 to the pixel electrode 122. The active layer 114 overlaps the gate electrode 106 with the gate insulating film 112 interposed therebetween to form a channel portion between the source and drain electrodes 108 and 110. The ohmic contact layer 116 is formed on the active layer 114 between the source electrode 108 and the drain electrode 110 and the active layer 114, The ohmic contact layer 116 serves to reduce electrical contact resistance between each of the source and drain electrodes 108 and 110 and the active layer 114. The semiconductor pattern including the active layer 114 and the ohmic contact layer 116 may be formed in such a manner as to overlap the data metal pattern including the data line 104 and the data lower electrode 162 as well as the source and drain electrodes 108 and 110 in the process .

The pixel electrode 122 is connected to the drain electrode 110 of the thin film transistor 130 through the pixel contact hole 120. Accordingly, the pixel electrode 122 is supplied with the pixel signal from the data line 104 through the thin film transistor 130. [

The storage capacitor Cst is formed by overlapping the storage electrode formed on the substrate with the pixel electrode sandwiching the gate insulating film and the protective film. The storage capacitor Cst serves to prevent the voltage of the pixel electrode 122 from fluctuating.

The gate pad 150 supplies the gate line 102 with a scan signal from a gate driver (not shown). The gate pad 150 is connected to the gate lower electrode 152 through the gate contact hole 154 passing through the protective film 170 and the gate insulating film 112 and the gate lower electrode 152 connected to the gate line 102 And a gate upper electrode 156 connected to the gate electrode 152.

The data pad 160 supplies a pixel signal from a data driver (not shown) to the data line 104. The data pad 160 is connected to the data lower electrode 162 connected to the data line 104 and the data contact hole 164 passing through the protective film 118, And an upper electrode 166. The data lower electrode 162 is formed so as to overlap the semiconductor pattern including the ohmic contact layer 116 and the active layer 114 formed thereunder.

3A and 3B are a plan view and a cross-sectional view for explaining a method of manufacturing a gate metal pattern in a method of manufacturing a thin film transistor substrate according to an embodiment of the present invention.

A gate metal pattern including a gate line 102, a gate electrode 106, a gate lower electrode 152, and a storage electrode 142 is formed on the lower substrate 101.

Specifically, a gate metal layer is formed on the lower substrate 101 through a deposition method such as a sputtering method. As the gate metal layer, a metal material such as molybdenum (Mo), titanium (Ti), copper (Cu), aluminum neodymium (AlNd), aluminum (Al), chromium (Cr), Mo alloy, Cu alloy, Al alloy, Layer, or a structure in which two or more layers are stacked using the metal. Then, a gate metal layer is patterned by a photolithography process and an etching process to form a gate metal pattern including the gate line 102, the gate electrode 106, the gate lower electrode 152, and the storage electrode 142.

4A and 4B are a plan view and a cross-sectional view illustrating a method of fabricating a semiconductor pattern and a data metal pattern in a method of fabricating a thin film transistor substrate according to an embodiment of the present invention.

A gate insulating film 112 is formed on a lower substrate 101 on which a gate metal pattern is formed and a data line 104, a source electrode 108, a drain electrode 110, and a data lower electrode 162 A semiconductor pattern including a data metal pattern and an active layer 114 and an ohmic contact layer 116 which are superimposed thereunder along with a data metal pattern are formed. The semiconductor pattern and the data metal pattern are formed by a mask process using a slit mask or a halftone.

Specifically, a gate insulating layer 112, an amorphous silicon layer, an amorphous silicon layer doped with impurities (n + or p +), and a data metal layer are sequentially formed on a lower substrate 101 on which a gate metal pattern is formed. Then, a photoresist is coated on the data metal layer, and then the photoresist is exposed and developed by a photolithography process using a slit mask, thereby forming a photoresist pattern having a step.

The data metal layer is patterned by an etching process using a photoresist pattern having a step, thereby forming a data metal pattern and a semiconductor pattern below the data metal pattern.

Then, the photoresist pattern is ashed by an ashing process using an oxygen (O ₂ ) plasma. The source and drain electrodes 108 and 110 are separated and the active layer 114 is exposed by removing the exposed data metal pattern and the underlying ohmic contact layer 116 by an etching process using an ashed photoresist pattern . Then, the photoresist pattern remaining on the data metal pattern is removed by the strip process.

FIGS. 5A and 5B are a plan view and a cross-sectional view for explaining a protective film and a method of manufacturing a transparent conductive pattern in the method of manufacturing a thin film transistor substrate according to an embodiment of the present invention, and FIGS. 6A and 6F are cross- Sectional views for explaining the protective film and the transparent conductive pattern shown in FIG.

A pixel electrode 122 and a gate upper electrode 156 are formed on the protective film 170. The pixel electrode 122 and the gate upper electrode 156 are formed on the passivation film 170. The passivation film 170 includes the pixel contact hole 120 and the gate contact hole 154 and the data contact hole 164, And the data upper electrode 166 are formed.

Specifically, a protective film 170 is formed on the gate insulating film 112 on which the semiconductor pattern and the data metal pattern are formed by a method such as plasma enhanced chemical vapor deposition (PECVD), spin coating, or spinless coating. And a lift off pass layer 172 is formed on the passivation layer 170 by a vapor deposition method such as sputtering.

At this time, the lift off pass layer 172 is formed of a metal such as copper (Cu), molybdenum (Mo), aluminum (Al), or the like.

Then, a photoresist pattern is applied on the lift off pass layer 172, and then exposed and developed by a photolithography process using a slit mask or a halftone mask, thereby forming a photoresist pattern 174 having a step.

Specifically, as shown in FIG. 6A, the blocking region S1 of the slit mask is located in a region where a transistor is to be formed, and the first photoresist pattern 174a remains after development by blocking ultraviolet rays. The slit region S2 of the slit mask is located in the region where the pixel electrode is to be formed and diffracts the ultraviolet ray to leave a second photoresist pattern 174b thinner than the first photoresist pattern 174a after development. The transmissive region S3 of the slit mask is located in a region where the pixel contact hole 120, the gate contact hole 154, and the data contact hole 164 are to be formed, so that ultraviolet rays are completely transmitted, do.

The liftoff pass layer 172 is patterned by a first wet etching or a dry etching process using the first and second photoresist patterns 174a and 174b and the passivation layer 170 and the gate insulating layer 112 are sequentially patterned to form a gate contact hole 154, a data contact hole 164, and a pixel contact hole 120 as shown in FIG. 6B.

6B, the first photoresist pattern 174a is thinned and the second photoresist pattern 174b is etched by ashing the photoresist pattern 174 by an ashing process using an oxygen (O ₂ ) And the lift off pass layer 172 corresponding to the second photoresist pattern is exposed.

Thereafter, the second photoresist pattern 174b is removed, and the lift off pass layer 172 exposed by the third dry etching process or the wet etching process using the first photoresist pattern 174a is patterned, Off path 180 of the overrun structure as shown in FIG.

In other words, the first photoresist pattern 174a remains in the third dry etching or wet etching process, and the liftoff pass layer 172 formed under the first photoresist pattern 174a reacts with the metal material, . In the third dry etching or wet etching process, the gate lower electrode 152 and the data lower electrode 164 exposed in the region where the gate contact hole 154 and the data contact hole 164 are formed are also etched.

Therefore, the lift-off pass layer 172 is etched at a predetermined interval by the third dry etching or wet etching process, so that the lift off pass layer 172 is shorter than the first photoresist pattern 174a to form the lift-off path 180.

On the other hand, if the dry etching process is used in the third etching process, the lift off pass layer 172 may be damaged or the like, and it is difficult to form the lift-off path 180, The wet etching process is used as the process.

Thus, by using the lift off pass layer 172 as an etching process, damage to the lower film can be prevented while uniformly forming the lift-off path 180 of the overrun structure.

6D, a transparent conductive film is formed on the lower substrate 101 on which the lift-off path 180 is formed through a deposition method such as a sputtering method. As the transparent conductive film, indium tin oxide (ITO), tin oxide (TO), indium zinc oxide (IZO), SnO ₂ , amorphous-indium tin oxide (a-ITO) .

6E, the pixel electrode 122, the gate upper electrode 156, and the data upper electrode 166 are included by lifting off the first photoresist pattern 174a and the transparent conductive film thereon by a stripping process A transparent conductive pattern is formed. The lift off pass layer 172 exposed in the fourth wet process is then removed. The lift off pass layer 172 is made of a metal such as copper (Cu), molybdenum (Mo), or aluminum (Al), and the transparent conductive pattern is made of indium tin oxide (ITO) (TiO ₂ ), indium tin oxide (ITO), indium zinc oxide (IZO), SnO ₂ , amorphous-indium tin oxide Only the lift off pass layer 172 can be removed.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

1 is a plan view showing a thin film transistor substrate according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view of the thin film transistor substrate shown in FIG. 1 taken along line I-I ', II-II', III-III ', IV-IV', and V-V '.

3A and 3B are a plan view and a cross-sectional view for explaining a method of manufacturing a gate metal pattern in a method of manufacturing a thin film transistor substrate according to an embodiment of the present invention.

4A and 4B are a plan view and a cross-sectional view illustrating a method of fabricating a semiconductor pattern and a data metal pattern in a method of fabricating a thin film transistor substrate according to an embodiment of the present invention.

5A and 5B are a plan view and a cross-sectional view for explaining a protective film and a method of manufacturing a transparent conductive pattern in the method of manufacturing a thin film transistor substrate according to an embodiment of the present invention.

FIGS. 6A and 6F are cross-sectional views illustrating the protective film and the transparent conductive pattern shown in FIGS. 5A and 5B, respectively.

Description of the Related Art

101: lower substrate 102: gate line

104: Data line 106: Gate electrode

108: source electrode 110: drain electrode

112: gate insulating film 114: active layer

116: ohmic contact layer 120, 154, 164: contact hole

122: pixel electrode 130: thin film transistor

150: gate pad 152: gate pad lower electrode

156: gate pad upper electrode 160: data pad

162: Data pad lower electrode 166: Data pad upper electrode

170: Protective layer 172: Lift off pass layer

180: lift off path

Claims (5)

Forming a gate electrode pattern including a gate line, a gate electrode, a storage electrode, and a gate lower electrode on a lower substrate; A gate insulating film is formed on a lower substrate on which the gate electrode pattern is formed, and a data metal pattern including a data line, a source and a drain electrode, and a data lower electrode is formed thereon, and a semiconductor pattern ; ≪ / RTI > Forming a protective film and a lift off pass layer on the gate insulating film on which the data metal pattern and the semiconductor pattern are formed, first and second photoresist patterns having different thicknesses from each other; Forming a gate contact hole, a data contact hole, and a pixel contact hole using the first and second photoresist patterns; ashing the first and second photoresist patterns; Forming a lift-off path in an etching process using the first photoresist pattern thinned by the ashing process; Forming a transparent conductive film on the substrate including the first photoresist pattern and then lifting off the first photoresist pattern and the transparent conductive film on the first photoresist pattern by a strip process to form a pixel electrode, And forming a transparent conductive pattern including the transparent conductive pattern. The method according to claim 1, Wherein the lift-off pass layer is formed of a metal material such as copper, chromium, aluminum, or the like. The method according to claim 1, Wherein the lift-off path is an over-lay structure formed by the lift-off pass layer having a length shorter than the length of the first photoresist pattern. The method according to claim 1, Wherein the etching process is a wet etching process in the step of forming the lift-off path. The method according to claim 1, Further comprising the step of removing the exposed lift off pass layer by a wet etching process after forming the transparent conductive pattern.

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