KR101424919B1 - Transistor with copper diffusion barrier layer, method for manufacturing the same and electronic device comprising transistor - Google Patents

Transistor with copper diffusion barrier layer, method for manufacturing the same and electronic device comprising transistor Download PDF

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KR101424919B1
KR101424919B1 KR1020130022383A KR20130022383A KR101424919B1 KR 101424919 B1 KR101424919 B1 KR 101424919B1 KR 1020130022383 A KR1020130022383 A KR 1020130022383A KR 20130022383 A KR20130022383 A KR 20130022383A KR 101424919 B1 KR101424919 B1 KR 101424919B1
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electrode
copper
layer
channel layer
transistor
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KR1020130022383A
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Korean (ko)
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정재경
이철규
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인하대학교 산학협력단
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

A transistor including a copper diffusion preventing layer, a manufacturing method thereof, and an electronic device including a transistor are disclosed. The transistor includes a gate electrode formed on a substrate; A gate insulating layer formed on the gate electrode; A channel layer formed on the gate insulating layer; A source electrode electrically connected to a source region of the channel layer and including copper (Cu); A drain electrode electrically connected to a drain region of the channel layer, the drain electrode including copper; And a copper diffusion barrier layer for preventing diffusion of copper (Cu) between each of the source and drain electrodes and the channel layer.

Description

TECHNICAL FIELD [0001] The present invention relates to a transistor including a copper diffusion prevention layer, a method of manufacturing the same, and an electronic device including a transistor. [0002]

The following description relates to transistors, their fabrication methods and electronic devices including transistors.

Description of the Related Art [0002] Thin film transistors (TFTs) are one type of field effect transistors (FETs), and are used as switching devices and driving devices. . The liquid crystal display to which the TFT technology is applied is called a TFT-Liquid Crystal Display (TFT-LCD).

Currently, the proportion of material costs is becoming larger as the size of flat panel displays and flexible displays increases. Therefore, it is important to reduce cost by simplifying the manufacturing process and reducing the material cost, rather than enlarging the glass substrate size.

Copper (Cu) has about one-hundredth the price of silver (Ag), but the conductivity is equivalent to that of Ag. In addition, Cu can prevent signal deterioration due to the resistance of aluminum wiring, and is an indispensable element in a high-resolution and large-sized display panel of 50 inches or more.

In recent years, as a high-speed wiring technology becomes more important in display devices, some attempts have been made to use Cu wiring as a gate and source / drain electrodes, but Cu diffusion may cause a problem in TFT performance. For example, the SS (subthreshold swing) value increases with the Cu diffusion, and the threshold voltage moves excessively in the positive direction, so that the device performance may deteriorate. Accordingly, there is a demand for a technique capable of preventing diffusion of Cu to improve the performance of the TFT.

A copper diffusion preventing layer is provided.

A method of manufacturing the transistor is provided.

And an electronic device including the transistor.

According to one embodiment, a transistor includes: a gate electrode formed on a substrate; A gate insulating layer formed on the gate electrode; A channel layer formed on the gate insulating layer; A source electrode electrically connected to a source region of the channel layer and including copper (Cu); A drain electrode electrically connected to a drain region of the channel layer and including copper (Cu); And a copper diffusion barrier layer for preventing diffusion of copper (Cu) between each of the source and drain electrodes and the channel layer.

A method of manufacturing a transistor according to an embodiment includes: forming a gate electrode on a substrate; Forming a gate insulating layer on the gate electrode; Forming a channel layer on the gate insulating layer, the channel layer including a source region and a drain region; Forming a copper diffusion preventing layer on the channel layer to prevent diffusion of copper (Cu); And forming a source electrode including copper (Cu) and a drain electrode including copper (Cu) on the copper diffusion preventing layer.

A transistor according to an embodiment includes: a gate electrode formed on a substrate; A gate insulating layer formed on the gate electrode; A channel layer formed on the gate insulating layer; A source electrode electrically connected to a source region of the channel layer and including copper (Cu); A drain electrode electrically connected to a drain region of the channel layer and including copper (Cu); And a copper diffusion barrier layer for preventing copper (Cu) diffusion between each of the source and drain electrodes and the channel layer.

According to one embodiment, the performance of the transistor can be improved by preventing copper from diffusing from the copper electrode into the channel layer.

1 is a cross-sectional view illustrating a structure of a transistor according to an embodiment.
FIG. 2 is a graph showing simulation results of transistor performance according to an embodiment with and without a copper diffusion preventing layer. Referring to FIG.
3 is a graph showing SIMS analysis results according to the presence or absence of a copper diffusion preventing layer according to an embodiment.
4 is a graph showing the results of TLM analysis according to the presence or absence of a copper diffusion preventing layer according to an embodiment.
5 is a flowchart illustrating a method of manufacturing a transistor according to an embodiment.

Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. The specific structural or functional descriptions below are merely illustrative for purposes of illustrating embodiments of the invention and are not to be construed as limiting the scope of the invention to the embodiments described in the text. Like reference symbols in the drawings denote like elements.

1 is a cross-sectional view illustrating a structure of a transistor according to an embodiment.

1, the transistor 100 includes a gate electrode 110, a gate insulating layer 120, a channel layer 130, a source electrode, a drain electrode, and a copper diffusion barrier layer 140, . ≪ / RTI > The transistor 100 may be used as an electronic device constituting a TFT-LCD, an AMOLED (Active Matrix Organic Light Emitting Diode), a transparent display, or the like.

The gate electrode 110 may be formed on a substrate. The substrate may be a glass substrate, but may be any other substrate, for example, a plastic substrate, a silicon substrate, or various substrates used in a general semiconductor device process. The gate electrode 110 may be formed of a metal, a conductive oxide, or the like.

A gate insulating layer 120 may be formed on the gate electrode 110 to cover the gate electrode 110. The gate insulating layer 120 may include a silicon oxide layer or a silicon nitride layer, but may also include a layer of another material, for example, a layer of high dielectric constant material having a dielectric constant higher than that of the silicon nitride layer. The gate insulating layer 120 may have a single-layer structure or a multi-layer structure.

A channel layer 130 may be formed on the gate insulating layer 120. The channel layer 130 may include a channel region, a source region, and a drain region. The channel layer 130 may be formed of an oxide semiconductor. For example, the channel layer 130 may be formed by stacking an oxide semiconductor such as ZFT (Zinc Tin Oxide). However, the ZTO is merely an example, and various other oxide semiconductors can be used. For example, oxide semiconductors may be formed of indium gallium zinc oxide (InGaZnO), zinc tin oxide (ZnSnO), indium tin oxide (InSnO), indium zinc oxide (InZnO), hafnium indium zinc oxide (HfInZnO), zirconium zinc tin oxide (ZrZnSnO ), And hafnium zinc tin oxide (HfZnSnO). Alternatively, the oxide semiconductor may be a binary, ternary or quaternary semiconductor material containing at least two or more metal materials selected from indium (In), zinc (Zn), tin (Sn), zirconium (Zr), hafnium (Hf) Quaternary metal oxide semiconductor material.

A source electrode electrically connected to the source region of the channel layer 130 on the gate insulating layer 120 and including copper (Cu) may be provided. Also, a drain electrode electrically connected to the drain region of the channel layer 130 and containing copper (Cu) may be provided on the gate insulating layer 120. The source electrode and the drain electrode may have a multi-layer structure. The source electrode may include a copper electrode 145, a tantilium electrode 150, and an aluminum (Al) electrode 155. The drain electrode may also include a copper electrode 165, a tantalum electrode 170, and an aluminum electrode 175. Each of the tantilium electrodes 150 and 170 at the source electrode and the drain electrode may be positioned between the copper electrodes 145 and 165 and the aluminum electrodes 155 and 175.

Diffusion barrier layers 140 and 160 for preventing diffusion of copper between the source and drain electrodes and the channel layer 130 may be provided. The copper diffusion barrier layers 140 and 160 may include tantalum (Ta). The copper diffusion barrier layers 140 and 160 may have a structure extended to the gate insulating layer 120 adjacent thereto while being in contact with one end of the channel layer 130. [ The copper diffusion preventing layers 140 and 160 can prevent copper from diffusing into the channel layer 130 from the copper electrode included in the source electrode and the drain electrode. Accordingly, it is possible to reduce the occurrence of defects in the channel layer 130 and to reduce the deterioration of the performance of the transistor 100 caused by diffusion of copper into the channel layer 130. For example, by preventing the copper diffusion barrier layers 140 and 160 from diffusing copper into the channel layer 130, the SS (Subthreshold Swing) increases and the threshold voltage shifts in the positive direction .

FIG. 2 is a graph showing simulation results of transistor performance according to an embodiment with and without a copper diffusion preventing layer. Referring to FIG.

The graph 210 shows the transfer characteristics of the W / O diffusion barrier without the copper diffusion barrier and the graph 220 shows the transistor diffusion characteristics with the diffusion barrier with the copper diffusion barrier . In general, the performance of a TFT can be evaluated as mobility, subthreshold swing (SS), and threshold voltage. It is considered to be a high-performance TFT when the mobility is high or the SS is an appropriate value. If the SS value is too low, the current control of the device may be difficult, and if the SS value is too high, the power consumption of the device may increase as the driving voltage of the device increases. When the threshold voltage of the TFT is away from 0 (V), the power consumption may increase due to the increase of the driving voltage. Therefore, it is considered that the closer the threshold voltage is to 0 (V), the higher the performance. When comparing the graph 210 and the graph 220, it can be seen that the threshold voltage is closer to 0 (V) when the copper diffusion preventing layer is present than when there is no copper diffusion preventing layer. Therefore, it can be seen that the transistor including the copper diffusion preventing layer exhibits a further improved performance.

Table 1 below shows the simulation results showing the performance difference of the transistor with or without the copper diffusion preventing layer.

Sat mobility
(cm 2 / Vs) Lin mobility
(cm 2 / Vs) V th (V) S-factor
(V / dec) W / O barrier layer 10.4 13.2 9.1 1.1 With barrier layer 10.7 18.7 3.0 0.48

According to Table 1, in the case of the transistor without the copper diffusion preventing layer, the SS is 1.1 V / dec, the threshold voltage (Vth) is 9.1 V, the SS is 0.481 V / dec and the Vth is 3.0 V It can be confirmed that the copper diffusion preventing layer exhibits improved performance in the presence of the copper diffusion preventing layer.

3 is a graph showing SIMS analysis results according to the presence or absence of a copper diffusion preventing layer according to an embodiment.

The graph 300 shows the depth profile of the channel according to the presence or absence of the copper diffusion preventing layer through a secondary ion mass spectroscopy (SIMS) analysis. From SIMS analysis, it can be seen that the W / O diffusion barrier diffuses more copper into the channel layer than the diffusion barrier without the copper diffusion barrier.

4 is a graph showing the results of TLM analysis according to the presence or absence of a copper diffusion preventing layer according to an embodiment.

The graph 410 shows the TLM (transfer length method) analysis result when there is no copper diffusion preventing layer, and the graph 420 shows the TLM analysis result when the copper diffusion preventing layer is present.

Detailed analysis results are shown in Table 2 below.

V W / O diffusion barrier (Ω) With diffusion barrier (Ω) 20V 13904 8567 25V 5727 4210 30V 2721 2507 35V 2100 1692 40V - 1244

Table 2 shows the contact resistance between the source electrode and the drain electrode and the channel with or without the copper diffusion barrier layer using TLM analysis. If the contact resistance is high, the time for turning on the device becomes longer, and the power consumption may increase. From the results shown in Table 2, it can be seen that the presence of the copper diffusion preventing layer has lower contact resistance than the case without the copper diffusion preventing layer.

5 is a flowchart illustrating a method of manufacturing a transistor according to an embodiment.

Referring to FIG. 5, a gate electrode may be formed 510 on a substrate. The substrate may be a glass substrate, but may be any other substrate, for example, a plastic substrate, a silicon substrate, or various substrates used in a general semiconductor device process. The gate electrode may be formed of a metal, a conductive oxide, or the like.

Next, a gate insulating layer covering the gate electrode may be formed (520) on the gate electrode of the gate electrode. The gate insulating layer may comprise a silicon oxide layer or a silicon nitride layer, but may also include other material layers, for example, a layer of high dielectric constant material having a dielectric constant greater than that of the silicon nitride layer. The gate insulating layer may have a single-layer structure or a multi-layer structure.

Thereafter, a channel layer including a channel region, a source region, and a drain region may be formed (530) on the gate insulating layer. The channel layer may be formed of an oxide semiconductor. For example, the channel layer may be formed by stacking an oxide semiconductor such as ZTO (Zinc Tin Oxide). However, ZTO is merely an example, and various other oxide semiconductors can be used. For example, in the case of indium gallium zinc oxide (InGaZnO), zinc tin oxide (ZnSnO), indium zinc oxide (InZnO), hafnium indium zinc oxide (HfInZnO), zirconium zinc tin oxide (ZrZnSnO), hafnium zinc tin oxide (HfZnSnO) By depositing a material containing either one, a channel layer can be formed. Or at least one or more metal targets of indium (In), zinc (Zn), tin (Sn), zirconium (Zr), hafnium (Hf), and gallium (Ga) are simultaneously sputtered on the gate insulating layer A channel layer may be formed by depositing a binary oxide, a ternary or quartz metal oxide semiconductor material. According to an example, a channel layer may be formed under the conditions of a working pressure of 5 mTorr, an O 2 ratio of 10%, a DC power of 100 W, a sputtering time of 15 minutes, and an annealing temperature of 500 degrees Celsius .

When a channel layer is formed, a copper diffusion preventing layer 540 for preventing diffusion of copper (Cu) may be formed on the channel layer. The copper diffusion barrier layer may include tantalum (Ta). The copper diffusion preventing layer may have a structure extended to the gate insulating layer adjacent thereto while being in contact with one end of the channel layer. The copper diffusion preventing layer can prevent copper from diffusing into the channel layer from the copper electrode included in the source electrode and the drain electrode. Accordingly, it is possible to reduce the occurrence of defects in the channel layer and reduce the performance deterioration due to copper diffusion into the channel layer. For example, by preventing the copper diffusion barrier from diffusing copper into the channel layer, the SS increases and the threshold voltage can be prevented from moving in the positive direction.

A source electrode including copper (Cu) and a drain electrode including copper (Cu) may be formed (550) on the copper diffusion preventing layer. The source electrode and the drain electrode may have a multi-layer structure. The source electrode and the drain electrode are formed by forming a copper (Cu) electrode on a copper anti-reflective layer, forming a tantalum (Ta) electrode on the copper electrode, and forming an aluminum (Al) electrode on the tantilium electrode Lt; / RTI >

According to an example, the copper diffusion preventing layer, the source electrode and the drain electrode can be produced under the conditions of a working pressure of 4 mTorr (Ar only), a DC power of 50 W, and an annealing temperature of 250 degrees Celsius (° C). Through the sputtering process, the copper diffusion preventing layer can be formed with a thickness of 10 nm, a copper electrode with a thickness of 150 nm, a tantalum electrode with a thickness of 50 nm, and an aluminum electrode with a thickness of 200 nm. However, this is for the purpose of describing the manufacturing process of the transistor in detail and should not be construed as limiting the scope of the embodiments.

The method according to an embodiment may be implemented in the form of a program command that can be executed through various computer means and recorded in a computer-readable medium. The computer-readable medium may include program instructions, data files, data structures, and the like, alone or in combination. The program instructions to be recorded on the medium may be those specially designed and configured for the embodiments or may be available to those skilled in the art of computer software. Examples of computer-readable media include magnetic media such as hard disks, floppy disks and magnetic tape; optical media such as CD-ROMs and DVDs; magnetic media such as floppy disks; Magneto-optical media, and hardware devices specifically configured to store and execute program instructions such as ROM, RAM, flash memory, and the like. Examples of program instructions include machine language code such as those produced by a compiler, as well as high-level language code that can be executed by a computer using an interpreter or the like. The hardware devices described above may be configured to operate as one or more software modules to perform the operations of the embodiments, and vice versa.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. For example, it is to be understood that the techniques described may be performed in a different order than the described methods, and / or that components of the described systems, structures, devices, circuits, Lt; / RTI > or equivalents, even if it is replaced or replaced.

Therefore, other implementations, other embodiments, and equivalents to the claims are also within the scope of the following claims.

Claims (13)

A gate electrode formed on the substrate;
A gate insulating layer formed on the gate electrode;
A channel layer formed on the gate insulating layer;
A source electrode electrically connected to a source region of the channel layer and including copper (Cu);
A drain electrode electrically connected to a drain region of the channel layer and including copper (Cu); And
And a copper diffusion preventing layer for preventing diffusion of copper (Cu) between each of the source electrode and the drain electrode and the channel layer,
/ RTI >
Each of the source electrode and the drain electrode
A copper (Cu) electrode;
An aluminum (Al) electrode formed on the copper electrode; And
A tantalum (Ta) electrode located between the copper electrode and the aluminum electrode
/ RTI >
The copper diffusion barrier layer
Tantalum (Ta). delete The method according to claim 1,
The copper diffusion barrier layer
And a gate insulation layer adjacent to the one end of the channel layer. delete delete The method according to claim 1,
Wherein the channel layer comprises:
(InGaZnO), zinc tin oxide (ZnSnO), indium tin oxide (InSnO), indium zinc oxide (InZnO), hafnium indium zinc oxide (HfInZnO), zirconium zinc tin oxide (ZrZnSnO), hafnium zinc tin oxide HfZnSnO). ≪ / RTI > delete An electronic device comprising the transistor according to claim 1. Forming a gate electrode on the substrate;
Forming a gate insulating layer on the gate electrode;
Forming a channel layer on the gate insulating layer, the channel layer including a source region and a drain region;
Forming a copper diffusion preventing layer on the channel layer to prevent diffusion of copper (Cu); And
Forming a source electrode including copper (Cu) and a drain electrode including copper (Cu) on the copper diffusion preventing layer
Lt; / RTI >
Each of the source electrode and the drain electrode
A copper (Cu) electrode;
An aluminum (Al) electrode formed on the copper electrode; And
A tantalum (Ta) electrode located between the copper electrode and the aluminum electrode
/ RTI >
The copper diffusion barrier layer
Tantalum (Ta). delete delete 10. The method of claim 9,
Wherein forming the channel layer comprises:
(InGaZnO), zinc tin oxide (ZnSnO), indium tin oxide (InSnO), indium zinc oxide (InZnO), hafnium indium zinc oxide (HfInZnO), zirconium zinc tin oxide (ZrZnSnO), hafnium zinc tin oxide HfZnSnO). ≪ / RTI > 10. The method of claim 9,
Wherein forming the channel layer comprises:
Sputtering at least two or more metal targets of indium (In), zinc (Zn), tin (Sn), zirconium (Zr), hafnium (Hf) and gallium (Ga) Wherein the metal oxide semiconductor material is a metal oxide semiconductor material.
KR1020130022383A 2013-02-28 2013-02-28 Transistor with copper diffusion barrier layer, method for manufacturing the same and electronic device comprising transistor KR101424919B1 (en)

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CN109449214A (en) * 2018-12-05 2019-03-08 山东大学 A kind of gallium oxide semiconductor Schottky diode and preparation method thereof
CN109449214B (en) * 2018-12-05 2023-05-30 山东大学 Gallium oxide semiconductor Schottky diode and manufacturing method thereof

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