KR101383924B1 - Thin Film Transistor Array and Fabricating method thereof - Google Patents

Abstract

The present invention relates to a thin film transistor array having improved ductility of a metal pattern and a method of manufacturing the same.

Method of manufacturing a thin film transistor array according to an embodiment of the present invention comprises the steps of providing a coating liquid comprising a metal nanoparticles, activating oxygen is coupled to the end group, a conductive polymer matrix and a solvent bonded to the activation oxygen; Coating the coating solution on a flexible substrate; Curing the coating solution to form a coating film on the flexible substrate; And patterning the coating film to form a thin film transistor.

Description

Thin Film Transistor Array and Fabrication Method

1 is a view showing a conventional thin film transistor array.

2 illustrates a thin film transistor array according to an exemplary embodiment of the present invention.

3A through 3D are diagrams each showing an example of a method of manufacturing the thin film transistor array shown in FIG.

<Explanation of symbols for the main parts of the drawings>

21: flexible substrate 22, 22a: gate metal pattern

24: semiconductor pattern 25, 25a, 25b: source / drain metal pattern

26 thin film transistor 29 pixel electrode

The present invention relates to a thin film transistor array and a method of manufacturing the same in a display device. In particular, the present invention relates to a thin film transistor array having improved ductility of a metal pattern and a method of manufacturing the same.

Thin film transistors (hereinafter, referred to as "TFTs") are mainly used in active matrix flat panel displays. A flat panel display includes a plurality of pixel arrays defined by the intersection of gate lines and data lines on a substrate. Each pixel receives an electrical signal by a TFT connected to the gate line and the data line. A flat panel display including a TFT includes a liquid crystal display (LCD), an organic light emitting diode (OLED), an electrophoretic display, and the like.

1 is a cross-sectional view schematically showing a TFT array of a conventional flat panel display.

Referring to FIG. 1, the TFT array 10 includes a plurality of pixel arrays formed on the substrate 1. Each pixel is defined by the intersection of the gate line 2 and the data line 5 and includes a TFT 6 and a pixel electrode 9. The TFT causes the data voltage of the data line 5 to be charged and held in the pixel electrode 9 in response to the gate voltage of the gate line 2. Hereinafter, the cross-sectional structure shown by enlarging the TFT 6 will be described.

The TFT 6 includes a gate electrode 2a connected to the gate line 2, a source electrode 5a connected to the data line 5, a drain electrode 5b facing the source electrode 5a, and a source electrode 5a. ) And a semiconductor pattern 4 in ohmic contact with the drain electrode 5b.

The gate electrode 2a is connected to the gate line 2 to apply a scan signal to the TFT 6.

The semiconductor pattern 4 is activated when a scan signal of more than the threshold voltage Vth is applied to the gate electrode 2a to conduct the source electrode 5a and the drain electrode 5b. To this end, the semiconductor pattern 4 is composed of an active layer 4a and an ohmic contact layer 4b. The active layer 4a overlaps the gate electrode 2a with the gate insulating film 3 interposed therebetween, and is exposed between the source electrode 4a and the drain electrode 4b to form a semiconductor channel. The ohmic contact layer 4b is formed between the source electrode 5a and the active layer 4a and the drain electrode 5b and the active layer 4a such that the source electrode 5a and the drain electrode 5b are in ohmic contact with the active layer 4a. It is formed between.

The above-described TFT 6 is protected by the protective film 7. The protective film 7 includes a contact hole 8 exposing the drain electrode 5b. The pixel electrode 9 is connected to the drain electrode 5b through this contact hole 8.

Such pixel arrays are formed through a plurality of mask processes including a plurality of cleaning processes, thin film deposition processes, photolithography processes, and etching processes. The thin film deposition process included in each mask process requires a high temperature. The high temperature generated during the thin film deposition process causes deformation of the flexible substrate 1. The deformation | transformation of the flexible board | substrate 1 is shrinkage | contraction other than a high temperature process after expansion by high temperature. Since the ductility of the metal patterns formed on the flexible substrate 1 is significantly smaller than the strain of the flexible substrate 1, a crack C occurs in the metal patterns. The crack C generated in the metal patterns becomes a problem because it causes a defect of the TFT array substrate such as malfunction or inoperability of the TFT 6.

SUMMARY OF THE INVENTION An object of the present invention is to provide a thin film transistor array having improved ductility of a metal pattern and a method of manufacturing the same.

In order to achieve the above object, a thin film transistor array according to an embodiment of the present invention is a flexible substrate; And a thin film transistor formed on the flexible substrate and including metal nanoparticles having activated oxygen bonded to an end group, and a conductive polymer matrix bonded to the activated oxygen.

Method of manufacturing a thin film transistor array according to an embodiment of the present invention comprises the steps of providing a coating liquid comprising a metal nanoparticles, activating oxygen is coupled to the end group, a conductive polymer matrix and a solvent bonded to the activation oxygen; Coating the coating solution on a flexible substrate; Curing the coating solution to form a coating film on the flexible substrate; And patterning the coating film to form a thin film transistor.

The forming of the thin film transistor may include forming a plurality of gate lines to which a scan signal is supplied on the flexible substrate; And forming a plurality of data lines on the flexible substrate to cross the gate lines and to which a data signal is supplied; The data lines and the gate lines include metal nanoparticles in which activation oxygen is bonded to an end group, and a conductive polymer matrix bonded to the activation oxygen.

The gate line is formed simultaneously with the gate electrode of the thin film transistor connected to the gate line, and the data line is simultaneously with the source electrode of the thin film transistor connected to the data line and the drain electrode of the thin film transistor separated from the source electrode. Is formed.

Forming a pixel electrode connected to the drain electrode; The pixel electrode includes metal nanoparticles in which activation oxygen is bonded to an end group, and a conductive polymer matrix bonded to the activation oxygen.

The gate line, the gate electrode, the data line, the source electrode and the drain electrode may be one of Mo, Ti, Cu, AlNd, Al, Cr, Ni, Ag, Au, Pt, Mo alloy, Cu alloy, and Al alloy. It includes at least a species of metal nanoparticles.

The pixel electrode may be formed of indium tin oxide (ITO), tin oxide (TO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), Al, At least one metal nanoparticle of AlNd and Mo.

The conductive polymer matrix may include poly acetylene, poly thiophene, poly (3-acryl thiophene), poly pyrrole, poly (para-phenyl). Poly (para-penylene vinylene), poly (ethylene vinylene), poly (para-phenylene), poly (3,4- Ethylene dioxythiophene) (poly (3,4-ethylene dioxythiopene)).

The size of the metal nanoparticles in which the activation oxygen is bonded to the terminal group is 50 nm or less.

The metal nanoparticles in which the activation oxygen is bonded to the terminal group include particles of 50 nm size and 20 nm size.

The mixing ratio of the 50 nm particles and the 20 nm particles is 7: 3 or 8: 2.

The preparing of the coating solution further includes forming metal nanoparticles having activated oxygen in the terminal group, and forming metal nanoparticles having activated oxygen in the terminal group includes oxidizing the metal nanoparticles. Making a step; And dehydrogenating the metal nanoparticles.

The step of oxidizing the metal nanoparticles is made through alkyl acid (C _n H _{2n + 1} COOH).

The alkyl acid includes oleic acid (C ₁₇ H ₃₃ COOH).

The content ratio of the metal nanoparticles having activated oxygen in the terminal group in the coating solution is 20% by weight or more and 50% by weight or less.

Other objects and advantages of the present invention will become apparent from the following description of preferred embodiments of the present invention with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 2 to 3D.

2 is a view schematically showing a TFT array according to an embodiment of the present invention. Referring to FIG. 2, the TFT array according to the embodiment of the present invention includes a plurality of pixel arrays formed on the flexible substrate 21. Each pixel is defined by the intersection of the gate line 22 and the data line 25 and includes a TFT 26 and a pixel electrode 29. The TFT causes the data voltage of the data line 25 to be charged and held in the pixel electrode 29 in response to the scan signal of the gate line 22.

The TFT 26 includes a gate electrode 22a connected to the gate line 22, a source electrode 25a connected to the data line 25, a drain electrode 25b facing the source electrode 25a, and a source electrode 25a. ) And the semiconductor pattern 24 in ohmic contact with the drain electrode 25b.

The gate electrode 22a is connected to the gate line 22 to apply a scan signal to the TFT 26.

The semiconductor pattern 24 is activated when a scan signal of more than the threshold voltage Vth is applied to the gate electrode 22a to conduct the source electrode 25a and the drain electrode 25b. To this end, the semiconductor pattern 24 is composed of an active layer 24a and an ohmic contact layer 24b. The active layer 24a overlaps the gate electrode 22a with the gate insulating film 23 interposed therebetween, and is exposed between the source electrode 24a and the drain electrode 24b to form a semiconductor channel. The ohmic contact layer 24b is formed between the source electrode 25a and the active layer 24a and the drain electrode 25b and the active layer 24a such that the source electrode 25a and the drain electrode 25b are in ohmic contact with the active layer 24a. It is formed between.

The TFT 26 is protected by the protective film 27. The passivation layer 27 includes a contact hole 28 exposing the drain electrode 25b. The pixel electrode 29 is connected to the drain electrode 25b through this contact hole 28.

The TFT array includes a gate metal pattern including a gate line 22 and a gate electrode 22a, a source / drain metal pattern including a data line 25, a source electrode 25a, and a drain electrode 25b, and a pixel. The pixel metal pattern including the electrode 29 is included.

The metal pattern according to the embodiment of the present invention includes metal nanoparticles in which activating oxygen is bonded to an end group as in Chemical Formula 1, and a conductive polymer matrix bonded to the activating oxygen.

MO ^- (M: metal nanoparticles, O ^-: active oxygen)

The conductive polymer matrix is elastic and has a stable chemical bond with activated oxygen. Accordingly, the metal pattern according to the embodiment of the present invention is improved in flexibility by the conductive polymer stably bonded to the metal nanoparticles.

The gate metal pattern and the source / drain metal pattern include metal nanoparticles, the metal nanoparticles being Mo, Ti, Cu, AlNd, Al, Cr, Ni, Ag, Au, Pt, Mo alloys, Cu alloys, Al alloys And one or more metals among these metals.

In addition, the pixel metal pattern includes metal nanoparticles, the metal nanoparticles of which are indium tin oxide (ITO), tin oxide (TO), indium zinc oxide (IZO), and indium tin. It includes at least one metal from metals such as indium tin zinc oxide (ITZO).

The metal patterns described above are formed through a plurality of mask processes, including a plurality of cleaning processes, thin film coating processes, photolithography processes, and etching processes. According to an exemplary embodiment of the present invention, a method of manufacturing a thin film transistor array includes a coating liquid including metal nanoparticles having activated oxygen bonded to an end group, a conductive polymer matrix bonded to the activated oxygen, and a solvent prior to the thin film coating process. Prepare.

The metal nanoparticles in which the activation oxygen is bonded to the terminal group are formed before preparing the coating liquid. Hereinafter, a process of forming the metal nanoparticles in which the activation oxygen is bonded to the terminal group will be described in detail.

Metal nanoparticles can be formed in a variety of ways. For example, the metal nanoparticles may be formed by a bottom-up method of increasing the size of the formed particles by nano units by causing a precipitation reaction through a solution including metal ions. In the bottom-up method, the size of the particles may be adjusted according to the composition of the solution. As another example, the metal nanoparticles are pulverized until the desired size is achieved by ion milling or ball milling the metal powder in millimeters or micrometers. It can be formed by a top-down method. Herein, the size of the metal nanoparticles is preferably formed to be 50 nm or less to improve conductivity.

Subsequently, in the manufacturing method according to the embodiment of the present invention, after the formation of the metal nanoparticles, the activated oxygen is formed on the metal nanoparticle end groups. To this end, the metal nanoparticles are oxidized through alkyl acid (C _n H _{2n + 1} COOH) and then hydrogen is removed through a dehydrogenation reaction. After the dehydrogenation reaction, activated oxygen is formed in the terminal group of the metal atom as shown in the formula (2).

MOH-> MO ^-

The alkyl group (C _n H _{2n + 1} ) included in the alkyl acid basically has a structure in which a carbon single bond (SP3) is long connected, and a double bond may be included. Alkyl acid containing a double bond is oleic acid (0leic acid: C ₁₇ H ₃₃ COOH) represented by the formula (3).

Since the above-described alkyl acid is a fast activating oxygen generation reaction, it is advantageous to form the activating oxygen in the metal nanoparticle end group.

As such, the metal nanoparticles in which the activated oxygen is bound are mixed with the conductive polymer matrix in the solvent. The conductive polymer matrix is stably bound to the activated oxygen of the metal nanoparticles. Conductive polymer matrices include poly acetylene, poly thiophene, poly (3-acryl thiophene), poly pyrrole, poly (para-phenyl) Poly (para-penylene vinylene), poly (ethylene vinylene), poly (para-penylene), poly (3,4- Ethylene dioxythiophene) (poly (3,4-ethylene dioxythiopene)) and the like.

Metal nanoparticles that are stably bonded to the conductive polymer matrix through activated oxygen are mixed through a solvent to have fluidity, and thus may be coated by spin coating, slit coating, roll printing, inkjet, or the like during thin film coating. The above-described coating method can be made through a cheaper equipment than the vacuum deposition can reduce the manufacturing cost of the TFT array.

The manufacturing method according to the embodiment of the present invention forms a metal pattern by including the process of coating the coating solution described above, a process of forming a coating film by curing the coating solution, and patterning the coating film through a mask process.

The metal nanoparticles included in the coating solution are preferably mixed with particles of 50 nm size and 10 nm size in a ratio of 7: 3 or 8: 2. This is because when the metal nanoparticles are mixed at the above-mentioned ratio, the metal nanoparticles having the size of 10 nm are filled in the pores between the metal nanoparticles having the size of 50 nm, thereby reducing the overall porosity of the metal nanoparticles, thereby improving the conductivity of the metal pattern. Moreover, it is preferable that content of the metal nanoparticle in a coating liquid is 20 weight% or more and 50 weight% or less. When the content of the metal nanoparticles is less than 20% by weight, it is not preferable because the thickness of the coated thin film after curing increases the resistance of the finally completed metal pattern. In addition, when the content of the metal nanoparticles exceeds 50% by weight, it is not preferable because the coating liquid may not have a viscosity enough to be coated on the substrate.

3A to 3D, a method of manufacturing a TFT array substrate according to an exemplary embodiment of the present invention will be described step by step using a four mask process as an example.

Referring to FIG. 3A, after the coating liquid including the gate metal nanoparticles is coated and cured on the flexible substrate 21, the gate metal pattern including the gate line and the gate electrode 22a connected to the gate line is formed by a first mask process. Is formed.

Referring to FIG. 3B, after the gate insulating layer 23 covering the gate metal pattern is formed, an amorphous silicon layer and an amorphous silicon layer doped with impurities (n + or p +) are formed on the gate insulating layer 23. Thereafter, the coating solution including the source / drain metal nanoparticles is coated and cured on the amorphous silicon layer doped with impurities, and then the semiconductor pattern 24 including the active layer 24a and the ohmic contact layer 24b by a second mask process. ) And a source / drain metal pattern including a data line, a source electrode 25a connected to the data line, and a drain electrode 25b facing the source electrode 25a. As the gate insulating film 23, an inorganic insulating material such as SiOx, SiNx, or the like is mainly used. Amorphous silicon is used as the active layer 24a, and amorphous silicon doped with impurities is used as the ohmic contact layer 24b.

The third mask process may form the semiconductor pattern 24 and the source / drain metal pattern in one mask process by using a halftone mask or a diffraction exposure mask.

Referring to FIG. 3C, a third mask process includes a contact hole 28 formed on the gate insulating layer 23 to cover the semiconductor pattern 24 and the source / drain metal pattern and exposing the drain electrode 25b. The protective film 27 is formed. As the protective layer 27, inorganic insulating materials such as SiOx and SiNx may be used, or organic insulating materials such as acrylic organic compounds, benzocyclobutene (BCB), perfluorocyclobutane (PFBC), teflon, and cytop may be used. do.

Referring to FIG. 3D, the coating solution including the pixel metal nanoparticles is coated and then cured to form a pixel electrode 29 connected to the drain electrode 25b through the contact hole 28 in a fourth mask process.

When the pixel electrode 29 is used as a reflective electrode, the metal included in the pixel metal nanoparticles may include at least one of metals such as Al, AlNd, and Mo.

As described above, the thin film transistor array and the method of manufacturing the same according to the embodiment of the present invention may improve the flexibility of the metal pattern by including the conductive polymer matrix in the metal pattern. Accordingly, even if the substrate is deformed during the manufacturing process of the thin film transistor array according to the embodiment of the present invention, a phenomenon in which a crack occurs in the metal pattern may be improved.

In addition, the thin film transistor array substrate and the method of manufacturing the same according to an embodiment of the present invention allows the conductive polymer matrix to be stably bonded by forming activated oxygen in the terminal groups of the metal nanoparticles included in the metal pattern.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

Claims (24)

A flexible substrate; And A thin film transistor including a plurality of gate lines formed on the flexible substrate and supplied with a scan signal, and a plurality of data lines intersecting the gate lines on the flexible substrate and supplied with a data signal, And the data lines and the gate lines include metal nanoparticles in which activation oxygen is bonded to an end group, and a conductive polymer matrix bonded to the activation oxygen. delete The method of claim 1, The thin film transistor A gate electrode connected to the gate line; A source electrode connected to the data line; And And a drain electrode separated from the source electrode. The method of claim 3, A pixel electrode connected to the drain electrode; The pixel electrode includes a metal nanoparticle in which activation oxygen is bonded to an end group, and a conductive polymer matrix bonded to the activation oxygen. The method of claim 3, The gate line, the gate electrode, the data line, the source electrode and the drain electrode A thin film transistor array comprising Mo, Ti, Cu, AlNd, Al, Cr, Ni, Ag, Au, Pt, Mo alloys, Cu alloys and Al alloys. 5. The method of claim 4, The pixel electrode Indium Tin Oxide (ITO), Tin Oxide (TO), Indium Zinc Oxide (IZO), Indium Tin Zinc Oxide (ITZO), Al, AlNd and Mo A thin film transistor array comprising at least one metal nanoparticle. The method of claim 1, The conductive polymer matrix Poly acetylene, poly thiophene, poly (3-acryl thiophene), poly pyrrole, poly (para-phenylene vinylene) ( poly (para-penylene vinylene)), poly (ethylene vinylene), poly (para-penylene), poly (3,4-ethylene dioxythiophene) A thin film transistor array comprising any one of (poly (3,4-ethylene dioxythiopene)). The method of claim 1, The thin film transistor array, characterized in that the size of the metal nanoparticles in which the activation oxygen is bonded to the terminal group is 50nm or less. The method of claim 1, The metal nanoparticles in which the activating oxygen is bonded to the terminal group includes 50nm size and 20nm size particles. 10. The method of claim 9, The thin film transistor array, characterized in that the mixing ratio of the 50nm size particles and the 20nm size particles is 7: 3 or 8: 2. Preparing a coating solution including metal nanoparticles having activated oxygen bonded to an end group, a conductive polymer matrix bonded to the activated oxygen, and a solvent; And Forming a thin film transistor on the flexible substrate, Forming the thin film transistor, Forming a plurality of gate lines to which a scan signal is supplied on the flexible substrate with the coating liquid; And Forming a plurality of data lines on the flexible substrate with the coating liquid and crossing the gate lines and supplied with a data signal, And the data lines and the gate lines include metal nanoparticles having activated oxygen bonded to terminal groups and a conductive polymer matrix bonded to the activated oxygen. The method of claim 11, Forming the gate lines and the data lines, Coating the coating solution on a flexible substrate; Curing the coating solution to form a coating film on the flexible substrate; And And patterning the coating layer to form the coating layer. The method of claim 11, The gate line Is formed simultaneously with the gate electrode of the thin film transistor connected to the gate line, The data line is And a source electrode of the thin film transistor connected to the data line and a drain electrode of the thin film transistor separated from the source electrode. 14. The method of claim 13, Forming a pixel electrode connected to the drain electrode; The pixel electrode includes a metal nanoparticle in which activation oxygen is bonded to an end group, and a conductive polymer matrix bonded to the activation oxygen. 14. The method of claim 13, The gate line, the gate electrode, the data line, the source electrode and the drain electrode A method of manufacturing a thin film transistor array comprising at least one metal nanoparticle of Mo, Ti, Cu, AlNd, Al, Cr, Ni, Ag, Au, Pt, Mo alloy, Cu alloy, and Al alloy. 15. The method of claim 14, The pixel electrode Indium Tin Oxide (ITO), Tin Oxide (TO), Indium Zinc Oxide (IZO), Indium Tin Zinc Oxide (ITZO), Al, AlNd and Mo A method of manufacturing a thin film transistor array comprising at least one metal nanoparticle. The method of claim 11, The conductive polymer matrix Poly acetylene, poly thiophene, poly (3-acryl thiophene), poly pyrrole, poly (para-phenylene vinylene) ( poly (para-penylene vinylene)), poly (ethylene vinylene), poly (para-penylene), poly (3,4-ethylene dioxythiophene) (poly (3,4-ethylene dioxythiopene)) comprising any one of a thin film transistor array. The method of claim 11, The method of manufacturing a thin film transistor array, wherein the size of the metal nanoparticles in which the activation oxygen is bonded to the terminal group is 50 nm or less. The method of claim 11, The metal nanoparticles in which the activating oxygen is bonded to the terminal group includes a 50 nm size and 20 nm size particles. 20. The method of claim 19, Method for manufacturing a thin film transistor array, characterized in that the mixing ratio of the particles of 50nm size and particles of 20nm size is 7: 3 or 8: 2. The method of claim 11, Preparing the coating solution Forming a metal nanoparticle having activated oxygen in the terminal group; Forming a metal nanoparticle having activated oxygen in the terminal group Oxidizing the metal nanoparticles; And Dehydrogenating the metal nanoparticles comprising the step of manufacturing a thin film transistor array. 22. The method of claim 21, Oxidizing the metal nanoparticles Method of manufacturing a thin film transistor array, characterized in that it is made of alkyl acid (C _n H _{2n + 1} COOH). 23. The method of claim 22, The alkyl acid is a method of manufacturing a thin film transistor array, characterized in that it comprises oleic acid (C ₁₇ H ₃₃ COOH). The method of claim 11, Method of manufacturing a thin film transistor array, characterized in that the content ratio of the metal nanoparticles having activated oxygen in the terminal group in the coating solution is 20% by weight or more and 50% by weight or less.

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