KR101376884B1 - Apparatus for controlling program command prefetch and method thereof - Google Patents

Abstract

An apparatus and method for prefetching and executing a program into a cache memory are disclosed. The program command prefetch control apparatus according to the present invention includes a MAP file storage unit for generating and recording program setting information when a program is compiled; And a prefetch unit for prefetching the next necessary instructions and data from the memory according to the order recorded in the MAP file storage unit when the instructions and data required for the program execution requested by the processor are not in the cache memory. The prefetch unit checks the source file and the binary code index information from the map file generated when the program is compiled, and prefetches the next command to be executed. The present invention uses the MAP file information generated when compiling a program to obtain the next instruction and data address to be executed and prefetches this portion to reduce the time to access the memory, thereby significantly reducing the time required to execute the program. There is.

Prefetch, Memory, SDRAM, DRAM, Cache Memory, Processor

Description

Apparatus for controlling program command prefetch and method

1 is a schematic diagram of an instruction prefetch form of a general processor;

2 is a schematic diagram of an apparatus for prefetching program instructions into a cache memory according to a first embodiment of the present invention;

3 is a schematic diagram of an apparatus for prefetching program instructions into a cache memory according to a second embodiment of the present invention;

4 is a detailed block diagram of a prefetch unit illustrated in FIGS. 2 and 3;

5 is a flow diagram of a method of prefetching program instructions into a cache memory in accordance with the present invention.

* Brief description of symbols for the main parts of the drawings *

100, 400: processor 200, 500: cache memory

210, 510: cache control unit 300, 600: memory

310 and 610: Memory control unit 320 and 520: Prefetch unit

330, 530: MAP file storage unit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for prefetching instructions from a memory, and more particularly, to a program instruction prefetch control apparatus for quickly processing a program by prefetching instructions from a memory and providing the same to a cache memory. It is about a method.

In a System On Chip platform architecture with a processor that includes a cache, the processor must fetch the associated instructions and data for program execution, and typically sequence the instructions from volatile or flash memory, such as synchronous DRAM. Will be withdrawn accordingly.

The main purpose of the processor is to execute a program to perform a desired operation by the user. At this time, the program to be executed by the processor is stored in a DRAM having a large capacity and low cost. The processor sends out an address and a control signal to retrieve the instruction, and the cache controller checks whether the instruction located at the address sent by the processor exists in the cache memory. The cache is used to reduce access latency inside the storage hierarchy.

The program to be executed by the processor is stored in a memory, such as a DRAM, and is drawn out to the processor according to an execution sequence to execute the program.

1 is a schematic diagram of an instruction prefetch form of a general processor. Referring to FIG. 1, the processor 10 sends out an address and a control signal to obtain an instruction. First, the processor 10 checks whether an instruction located at the exported address exists in the cache memory 20. If an instruction of the corresponding address exists in the cache memory 20, the cache controller 21 transmits the instruction to the processor 10. If the corresponding instruction is not in the cache memory 20, a predetermined instruction among the instruction to be executed through the memory controller 31 and the instruction at an address adjacent to the instruction is withdrawn from the memory 30 and stored in the cache memory 20, Prepare the processor for the next instruction request.

If a program is executed according to the conventional method as described above, it does not matter if there is an instruction necessary to execute the program in the cache memory, but if there is no corresponding program execution instruction in the cache memory because it has not been used recently, Some time is consumed.

In particular, DRAM takes the most time when it fetches the first one command, and it takes less time when it gets the first one or more commands when fetching several commands continuously. However, the cache always takes a constant amount of time, so using a cache can reduce the time to fetch instructions. Therefore, in a system including a cache, the processor fetches instructions from the slow memory and stores the instructions in the cache, thereby saving time.

However, although the cache memory is excellent in performing instruction execution quickly, the cost is expensive, and therefore, the inexpensive DRAM is used.

Therefore, it is an important issue to efficiently design cheap but slow DRAM and expensive but fast cache memory (SRAM).

In general, instructions at the adjacent address of an instruction to be executed are stored in the cache. If the flow of a program is not sequential and has divergent characteristics, that is, instructions at the adjacent address of the instruction to execute are not executed, they are stored in cache memory. You must continue to fetch new commands that are missing.

This leads to the inefficient use of expensive and fast caches.

Thus, there is a need to reconfigure the cache so that various programs can run at similar speeds.

In order to solve the above problems, the present invention applies a prefetch algorithm between a cache memory and a main memory to execute a program which is quickly executed by prefetching an instruction which is scheduled to be executed next to a cache memory even if the address is not adjacent. An object of the present invention is to provide an instruction prefetch control apparatus and a method thereof.

Program instruction prefetch control apparatus according to the present invention for achieving this object comprises a memory for storing program instructions and data; A memory controller which controls a read / write function of the memory; A cache memory for storing recently used instructions and data among the program instructions and data stored in the memory; A cache controller which controls a read / write function of the cache memory; A processor configured to overall control the system by retrieving instructions and data stored in the cache memory; A MAP file storage unit for generating and recording program setting information when the program is compiled; And a prefetch unit for pre-fetching the next necessary instructions and data from the memory according to the order recorded in the MAP file storage unit when the instructions and data required for the program execution requested by the processor are not in the cache memory.

The prefetch unit may identify a source file and binary code index information from a map file generated when the program is compiled, and prefetch the next command to be executed. The instruction pre-fetched by the prefetch unit is stored in a prefetch memory, and the memory is a dynamic random access memory (DRAM) or a flash memory.

When the prefetch unit is installed in the memory control unit, the command and data of an address adjacent to a command and data currently fetched by the memory control unit are fetched from the memory, regardless of an address not adjacent to the currently fetched command and data. The command and data may be fetched in the execution order according to the MAP file information.

When the prefetch unit is installed in the cache controller, the memory controller may request a command and data from the memory controller according to an execution order according to MAP file information.

Program instruction prefetch control method according to the present invention for achieving the object comprises the steps of determining whether the instruction is present in the cache memory when instructions and data required for program execution from the processor; If the requested instructions and data are present in a cache memory, providing the instructions and data to a processor; If the instruction and data requested from the processor do not exist in the cache memory, retrieving the instruction to be executed from the memory and the instruction at an address adjacent to the instruction to be stored in the cache memory; Receiving a command information to be executed next from a map file in a prefetch unit, and fetching (prefetching) the command to be executed in advance and storing the command in a prefetch unit; And when subsequent instructions and data required for executing the program are requested from the processor, immediately providing the instructions and data stored in the prefetch unit to the cache memory.

Retrieving the current command to be executed from the memory and an instruction of an address adjacent to the command to be executed and storing the same in a cache memory, and receiving a command information to be executed next from a map file in a prefetch unit, The steps of fetching (prefetching) an instruction in advance and storing the command in the prefetch unit may be independently performed.

When the prefetch unit is included in the cache controller, when it is determined that instructions and data necessary for program execution are not present in the cache memory, the prefetch unit stores the currently required instructions and instructions and data to be executed immediately after the instructions according to the MAP file information. Characterized in that the storage is withdrawn from the memory through the control unit.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention.

Computer-aided software development systems require a program to quickly edit, compile, link and perform all sequences from memory. The edit-compile-link cycle of developing source code in a computer's implementation generates many modules of source text accessed by the computer, compiles the modules from the computer to generate code tables for each module, and links. Linking the code table from a computer to provide a table and a list of links and to produce an object-code image that can be executed by it.

Hereinafter, exemplary embodiments will be described with reference to the accompanying drawings.

First Embodiment

2 is a schematic diagram of an apparatus for prefetching program instructions into a cache memory according to a first embodiment of the present invention.

Referring to FIG. 2, the memory management apparatus according to the first embodiment of the present invention includes a processor 100, a cache memory 200, and a memory 300, and the processor 100 and the cache memory 200. Exchanges commands and data through the cache controller 210. The memory 300 receives a control signal of the cache controller 210 through a bus and provides data corresponding to the control to the processor 100. The memory 300 operates by the read / write control signal of the memory controller 310, and the cache memory 200 operates by the read / write control signal of the cache controller 210.

Although the processor 100 illustrates that the control signal is transmitted and received only through the cache controller 210, the processor 100 may transmit and receive the control signal through the bus.

The memory 300 stores program instructions and data, and the memory controller 310 controls a read / write function of the memory 300. The cache memory 200 stores recently used instructions and data among program instructions and data stored in the memory 300, and the cache controller 210 controls a read / write function of the cache memory 200.

The processor 100 controls the overall system by drawing the instructions and data stored in the cache memory 200, and the program setting information is generated and recorded in the MAP file storage unit 330 when the program is compiled.

The prefetch unit 320 generates a command required for executing a program requested by the processor 100 and next data in the order recorded in the MAP file storage unit 330 in a situation that data is not stored in the cache memory 200. And data are prefetched from the memory 300 in advance.

Meanwhile, the cache memory 200 uses static random access memory (SRAM) because the recently used instructions and data must be continuously stored even when the power is turned off.

The memory 300 may use inexpensive DRAM or flash memory.

DRAM is a volatile memory device that cannot store program instructions and data at all times. Therefore, in the present specification, it is assumed that necessary program instructions and data are stored in DRAM after power is applied.

Since the flash memory does not change the data storage state even when the power is off, it can be seen that the program instructions and data are stored.

The MAP file storage unit 330 provides program setting information generated when the program is compiled as shown in Table 1.

command Address xxx 01010001 yyy 01010010 ... ... zzz 01110001

The program to be executed by the processor should be compiled in the language of the processor. The address information in which each instruction is stored in the compilation process is implemented in the form shown in Table 1, and includes the following information.

The MAP file acts like an index that maps the source file and binary at compile time. The location of the function, line, etc. of the corresponding source is displayed by mapping the location where the generated binary operates on the virtual address.

Thus, the map file provides information about the linked program in text form.

The information includes the base name of the file, the module name, the time stamp of the program file header, not the file system.

In addition, the group list of the program, the start address, length, group name and class of each group are displayed together. The list of common symbols, each address, symbolic name, flat address, and symbolic .obj file are displayed together with the entry point (section: offset).

The prefetch unit 320 receives program instructions and data from the cache controller 210 or the processor 100, and predicts an order of the next necessary instructions and data on the MAP file list in the form shown in Table 1, Accordingly, the command and data are fetched and stored from the corresponding address of the memory 300 in advance.

In the first exemplary embodiment, the prefetch unit 320 is provided in the memory controller 310.

When the prefetch unit 320 is provided in the memory controller 310, instructions and data necessary for executing a program may not be provided to the cache memory 200 in the order of execution.

This is because the basic function of the memory controller 310 fetches commands and data of adjacent addresses in order.

Therefore, in the first exemplary embodiment, the MAP file information is not included by the prefetch unit 310 while the instruction and data of the address adjacent to the currently fetched instruction and data are fetched according to the basic function of the memory controller 310. The command and data are fetched according to the execution order.

Since the prefetch unit 320 is a function for providing necessary instructions and data from the memory 300 to the cache memory 200, the location thereof is not limited to the memory control unit 310.

Therefore, the case where the positions of the prefetch units are different will be described with reference to the second embodiment.

Second Embodiment

3 is a schematic diagram of an apparatus for prefetching program instructions into a cache memory according to a second embodiment of the present invention. Referring to FIG. 3, the memory management apparatus according to the second embodiment of the present invention includes a memory 600 storing program instructions and data, a memory controller 610 controlling a read / write function of the memory 600, Cache memory 500 for storing recently used instructions and data among program instructions and data stored in the memory 600, a cache controller 510 for controlling a read / write function of the cache memory 500, and a cache memory ( A processor 400 for controlling overall control of the system by retrieving the instructions and data stored in 500; a MAP file storage unit 530 in which program setting information is generated and recorded when a program is compiled; and a program execution requested by the processor 400 In the situation that the instructions and data required for the data are not stored in the cache memory 500, the next necessary instructions and data in the order recorded in the MAP file storage unit 530. And a prefetch unit 520 for prefetching the data from the memory 600.

Since the cache memory 500, the memory 600, and the MAP file storage unit 530 in the second embodiment are the same as in the first embodiment, description thereof will be omitted.

However, in the second embodiment, the prefetch unit 510 is included in the cache control unit 510 in that it is significantly different from the configuration of the first embodiment.

When the prefetch unit 510 is included in the cache controller 510, the cache controller 510 is executed by the MAP file information regardless of the command and data of an adjacent address when a command and data request are made to the memory controller 610. In order to request commands and data.

The first and second embodiments may have different loading speeds depending on the characteristics of the program to be executed. That is, some programs may be loaded faster in the first embodiment and relatively slower in the second embodiment. In the first embodiment, even when loaded slowly, the loading may be faster when performed in the same manner as in the second embodiment.

4 is a detailed block diagram of the prefetch unit illustrated in FIGS. 2 and 3. Referring to FIG. 4, the prefetch units 320 and 520 may prefetch the instructions and data required for execution according to a request of the processor, and the instructions and data prefetched from the memory. It may include a PreFetch Memory (PFM) for storing the.

The prefetch controller PFC looks up the program file information list of the MAP file storage units 330 and 530 in order to know an execution order of instructions and data required for execution.

The MAP file storage units 330 and 530 may be included in the prefetch units 320 and 520.

Hereinafter, a cache memory management method of the memory management apparatus having the above configuration will be described. 5 is a flowchart of a method of prefetching program instructions into a cache memory in accordance with the present invention.

Fig. 5 shows a memory management method in the first embodiment.

First, suppose that power is applied and programs used by a user are stored in a memory. First, an instruction and data for executing a program are requested from a processor by a user's input (S10).

When the program execution command and data are requested, it is necessary to check whether there is the corresponding command and data in the cache memory (S12). It is determined whether the corresponding instruction and data exist in the cache memory (S14), and if determined to be in the cache memory, the instruction and data can be immediately provided to the processor (S16).

However, if it is determined in S14 that the instruction and data necessary for program execution are not present in the cache memory, the memory controller fetches the instruction and the data and instructions and data of the adjacent address from the memory and provides the cache to the cache memory (S18).

At a similar time, the prefetch controller prefetches instructions and data to be executed after the requested instruction according to the MAP file information and stores the prefetched instructions and data in the prefetch memory (S20).

S20 may be performed simultaneously because S18, the memory controller, and the prefetch controller may be driven independently.

Subsequently, when a subsequent instruction and data request is received from the processor, the instruction and data stored in the prefetch memory are immediately provided to the cache memory to be used by the processor (S22).

In the case where the prefetch unit is included in the cache control unit as in the second embodiment of the present invention, in step S18, if it is determined that the instruction and data necessary for program execution are not present in the cache memory, the prefetch control unit is currently required according to the MAP file information. The command, the command to be executed immediately after the command, and data are retrieved from the memory through the memory controller and stored in the prefetch memory.

As described above, the prefetching apparatus and method according to the present invention uses the MAP file information generated during program compilation to obtain a command and a data address to be executed next, thereby prefetching this portion to reduce the time to access the memory. This has the effect of significantly reducing the time taken to execute the program.

By implementing the program high speed execution through the prefetch unit, it is possible to reduce the cost used to increase the cache memory capacity for high speed program execution.

Claims (11)

A memory for storing program program instructions and data; A memory controller which controls a read / write function of the memory; A cache memory for storing recently used instructions and data among the program instructions and data stored in the memory; A cache controller which controls a read / write function of the cache memory; A processor configured to overall control the system by retrieving instructions and data stored in the cache memory; A MAP file storage unit for generating and recording program setting information when the program is compiled; And When the first instruction and the first data required for the program execution requested by the processor are not in the cache memory, the first instruction and the first data, the first instruction, and the second instruction adjacent to the first data and the first data are not present. A memory controller configured to retrieve 2 data from the memory and provide the data to the cache memory; And If the first command and the first data are not in the cache memory, the third command and the third data required after the first command and the first data according to the order recorded in the MAP file storage unit are stored in the memory. Including a prefetch unit to be pre-fetched from the cache memory, The MAP file storage unit stores a map (MAP) file, and the map file stores the execution order between the first command and the first data and the third command and the third data when the program is executed. Contains information to make predictions, The memory controller fetching the first command, the first data, the second command, and the second data from the memory and providing the first command and the first data, the second command, and the second data to the cache memory; Prefetching from the memory is performed independently of each other. The method of claim 1, wherein the prefetch unit And fetching the third command in advance by checking source file and binary code index information from the map file generated when the program is compiled. The method of claim 1, And the third command and the third data fetched by the prefetch unit are stored in a prefetch memory. The method of claim 1, wherein the memory is Program random data prefetch control device, characterized in that the DRAM (DRAM: Dynamic Random Access Memory). delete delete The method of claim 1, And the map file includes a timestamp and a section (offset) of a program file header. Determining whether the first instruction and the first data exist in a cache memory when a first instruction and first data necessary for executing a program are requested from a processor; If the first instruction and the first data exist in the cache memory, providing the first instruction and the first data to a processor; When the first instruction and the first data do not exist in the cache memory, the cache is fetched from the memory by drawing the first instruction and the first instruction and the second instruction and the second data of an address adjacent to the first instruction. Storing in memory; The prefetch unit receives information on the third command and the third data to be performed after the first command from the MAP file, and prefetches the third command and the third data in advance. Storing in a prefetch section; And If the third instruction and the third data are requested from the processor, providing the third instruction and the third data stored in the prefetch unit to the cache memory, Extracting the first instruction and the first data and the second instruction and the second data of the address adjacent to the first instruction and storing the first instruction and the second instruction in the cache memory; The fetching (prefetching) and storing the prefetching unit are performed independently. And the map file includes information about an execution order between the first command and the first data and the third command and the third data when the program is executed. delete delete 9. The method of claim 8, And the map file includes a timestamp and a section (offset) of a program file header.

Images