KR101375818B1 - Direct through via wafer level fanout package - Google Patents

Abstract

Methods, systems, and apparatuses for improved integrated circuit packages are disclosed. The integrated circuit package includes a semiconductor substrate and a semiconductor die. The semiconductor substrate has opposing first and second surfaces, a plurality of vias through the semiconductor substrate, and routing of one or both surfaces of the semiconductor substrate. The die is mounted on a first surface of the semiconductor substrate. An insulating material insulates the die on the first surface of the semiconductor substrate.

Description

Direct Through Via Wafer Level Fanout Package {DIRECT THROUGH VIA WAFER LEVEL FANOUT PACKAGE}

This application claims the benefit of US Provisional Patent Application No. 61 / 435,648, filed Jan. 24, 2011, which is hereby incorporated by reference in its entirety.

The present invention relates to integrated circuit packages.

Integrated circuit (IC) chips or dies are typically interfaced with other circuits using a package that can be attached to a circuit board. One such type of IC die package is a ball grid array (BGA) package. BGA packages offer smaller footprints than many other package solutions available today. One type of BGA package has one or more IC dies attached to the first surface of the package substrate and has an array of solder ball pads located on the second surface of the package substrate. Solder balls are attached to the solder ball pads. The solder balls are reflowed to attach the package to the circuit board.

An advanced type of BGA package is a wafer-level BGA package. Wafer-level BGA packages have several names in the industry, including wafer level chip scale packages (WLCSP), among others. In a wafer-level BGA package, the solar balls are mounted directly to the IC die when the IC die has not yet been singulated from the process wafer. As such, wafer-level BGA packages do not include a package substrate. Wafer-level BGA packages can therefore be made very small, with high pin out, compared to other IC package types including traditional BGA packages.

For IC dies used in wafer-level BGA packages, routing is typically formed directly on the die. The routing is formed on the surface of the dies to route the signals of the die pads to locations where the solder balls are attached to the die. Fan-in routing and fanout routing are two different types of routing that can be formed in the dies. Fan-in routing is a type of routing that is formed only within the area of each semiconductor die. Fanout routing is a type of routing that extends out of areas of a semiconductor die (above the material provided around the dies).

As such, fanout routing provides additional space for interconnects (eg, solder balls) for the resulting integrated circuit packages, so that the signals of the IC dies are larger than the area of the dies. It is spread over the area. However, typical techniques for forming wafer-level packages using fanout routing are expensive and use a relatively large number of assembly steps. As such, integrated circuit package assembly techniques that enable chip scale packages to be manufactured are less expensive and use fewer process steps as desired.

It is an object of the present invention to provide a direct through via wafer level fanout package that includes a multilayer circuit routing area that provides fanout routing and interconnects with active semiconductor devices in an interposer substrate.

Substantially, an integrated circuit in a semiconductor substrate having multi-layer routing and vias formed through the semiconductor substrate, as described and / or described herein in connection with at least one of the figures, as described more fully in the claims. Methods, systems, and apparatuses for forming integrated circuit packages by mounting a die are disclosed.

According to one aspect, the method

Forming a plurality of vias through the first semiconductor wafer in a plurality of semiconductor substrate regions of a first semiconductor wafer;

Attaching a plurality of dies singulated from a second semiconductor wafer to a surface of the first semiconductor wafer;

Insulating the dies at the surface of the first semiconductor wafer; And

Singulating the first semiconductor wafer to separate the plurality of substrate regions to form a plurality of integrated circuit packages, each integrated circuit package including at least one of the dies and the substrate according to a substrate region, Each substrate includes singulating, including fanout routing.

Advantageously, said first semiconductor wafer is a silicon wafer and said vias are through-silicon vias.

Preferably, the method further comprises:

Testing the substrate regions in the first semiconductor wafer to determine a set of substrate regions that operate prior to the singulating step.

Preferably, the method further comprises:

Forming routing at the surface of the first semiconductor wafer in each of the semiconductor regions.

Preferably, the attaching step,

Mounting each die in a substrate region using an array of solder bumps.

Preferably, the method further comprises:

Forming a plurality of interconnecting balls on a second surface of the first semiconductor wafer prior to singulating;

Each integrated circuit package includes interconnect balls of the plurality of interconnect balls for use by the integrated circuit package to interface with a circuit board.

Preferably, an array of electrically conductive pads on the surface of each integrated circuit package is used to interface the integrated circuit package with the circuit board as a land grid array package.

According to one aspect, the method

Forming a plurality of vias through the first semiconductor wafer in a plurality of semiconductor substrate regions of a first semiconductor wafer;

Singulating the first semiconductor wafer to form a plurality of substrates in accordance with the plurality of substrate regions;

Attaching the substrates to a surface of a carrier;

Attaching a plurality of dies singulated from the second semiconductor wafer to the substrates;

Encapsulating dies on the substrates with an encapsulating material in the carrier;

Detaching the carrier from the insulated dies and substrates to form a molded assembly comprising the insulating material insulating the dies and substrates; And

Singulating the molded assembly to form a plurality of integrated circuit packages, each integrated circuit package including at least one of the dies and at least one of the substrates, each substrate including fanout routing To, singulating.

Advantageously, said first semiconductor wafer is a silicon wafer and said vias are through-silicon vias.

Preferably, the method further comprises:

Testing the substrate regions in the first semiconductor wafer to determine a set of substrate regions that operate prior to the singulating the first semiconductor wafer.

Preferably, the method further comprises:

Forming routing on the surface of the first semiconductor wafer in each of the semiconductor regions.

Preferably, the attaching step,

Mounting each die on a substrate using an array of solder bumps.

The method comprises:

Forming a plurality of interconnecting balls on a second surface of said first semiconductor wafer prior to said singulating said first semiconductor wafer,

Each integrated circuit package includes interconnect balls of the plurality of interconnect balls used to interface the integrated circuit package to a circuit board.

Preferably, an array of electrically conductive pads on the surface of each integrated circuit package is used to interface the integrated circuit package as a land grid array package with a circuit board.

According to one aspect, an integrated circuit package,

A silicon substrate having opposing first and second surfaces, a plurality of vias through the silicon substrate, and routing at least at the first surface of the silicon substrate;

A die mounted on the first surface of the silicon substrate; And

An insulating material that insulates the die on the first surface of the silicon substrate.

Preferably, the package further comprises:

And a plurality of solder bumps attaching the die to the first surface of the silicon substrate.

Preferably, the package further comprises:

And a plurality of interconnecting balls attached to the second surface of the silicon substrate.

Preferably, the package further comprises:

The integrated circuit package further includes an array of electrically conductive pads on the second surface of the silicon substrate that are used to interface with the circuit board as a land grid array package.

Preferably, the vias are through-silicon vias.

Advantageously, said silicon substrate comprises active integrated circuit logic.

As noted above, in accordance with the present invention, interleaving substrates using through vias, such as through silicon vias (TSV), are provided to overcome the limitations of conventional fanout routing packaging. There is an advantage of having multiple routing layers in the poser substrates.

The accompanying drawings, which are incorporated herein and form a part of this specification, illustrate the invention, and together with the above description, illustrate the principles of the invention and further enable those skilled in the art to make and use the invention. to provide.
1 and 2 illustrate cross-sectional views of exemplary exemplary wafer level integrated circuit packages.
3 illustrates a cross-sectional side view of an integrated circuit package, in accordance with an example embodiment.
4 illustrates a flow diagram that provides an exemplary process for assembling integrated circuit packages, in accordance with an embodiment.
5 illustrates a top view of a first semiconductor wafer, in accordance with an example embodiment.
6 illustrates an additional procedure for testing substrate regions of a first semiconductor wafer, in accordance with an embodiment.
7 is a plan view of a second semiconductor wafer according to an example embodiment.
8 illustrates a view of the semiconductor wafer of FIG. 5 with a die attached to each substrate region of the wafer, in accordance with an example embodiment.
9 illustrates a cross-sectional side view of a portion of the semiconductor wafer of FIG. 5 with first and second dies mounted in respective substrate regions, according to an example embodiment.
10 illustrates a cross-sectional side view of a portion of the wafer shown in FIG. 9 with insulated dies, in accordance with an example embodiment.
FIG. 11 illustrates IC packages singulated from the insulated wafer of FIG. 10 in accordance with an example embodiment.
12 illustrates a flow diagram providing an exemplary process of using a carrier to assemble integrated circuit packages according to one embodiment.
13 shows a view of the surface of a carrier with attached semiconductor interposer substrates, according to an example embodiment.
14 illustrates the view of FIG. 13 with a die attached to the semiconductor substrates, in accordance with an example embodiment.
15 illustrates a cross-sectional side view of dies attached to a semiconductor substrate on a carrier, in accordance with example embodiments.
FIG. 16 illustrates a cross-sectional view of the carrier of FIG. 15 mounting semiconductor substrates and dies having an insulating material applied to the carrier to insulate the semiconductor substrates and dies, according to an example embodiment.
FIG. 17 illustrates a cross-sectional view of FIG. 16 separated from the insulating material, semiconductor substrates and dies to form the carrier-molded assembly in accordance with an example embodiment.
18 illustrates first and second IC packages singulated from the molded assembly of FIG. 17 in accordance with an example embodiment.
19 illustrates a cross-sectional side view of a portion of an IC package having a semiconductor substrate with multiple routing layers, according to an example embodiment.
20-22 illustrate examples of IC packages including a semiconductor interposer substrate, in accordance with embodiments.
The invention will now be described with reference to the accompanying drawings. In the drawings, like reference numerals refer to the same or functionally similar components. Additionally, the leftmost digit (s) of a reference sign refers to the figure in which the reference first appears.

Ⅰ. Introduction

The present specification discloses one or more embodiments that incorporate the features of the present invention. The embodiment (s) disclosed above are merely illustrative of the invention. The scope of the invention is not limited to the embodiment (s) disclosed above. The invention is defined by the claims appended hereto.

References in the detailed description to “one embodiment”, “one embodiment”, “an example embodiment”, and the like, indicate that the disclosed embodiment may include particular features, structures, or characteristics, but all embodiments Examples may not necessarily include specific features, structures, or characteristics. Moreover, such phrases are not necessary with respect to the same embodiment. In addition, when a particular feature, structure, or characteristic is described in connection with one embodiment, it is within the knowledge of a person skilled in the art to bring such feature, structure, or characteristic in connection with other embodiments, whether or not explicitly described. Is said.

Moreover, the spatial expressions used herein (eg, "over", "less than", "up", "left", "right", "down", "top", "bottom", "vertical") It is to be understood that the " horizontal " is for illustrative purposes only and that practical implementations of the structures described herein can be spatially arranged in any orientation or manner.

Ⅱ. Example Embodiments

Integrated circuit (IC) chips or dies typically interface with other circuitry using a package that can be attached to a circuit board. One such type of IC die package is a ball grid array (BGA) package. BGA packages offer smaller footprints than many other package solutions available today. One type of BGA package has one or more IC dies attached to the first surface of the package substrate and has an array of solder ball pads located on the second surface of the package substrate. Solder balls are attached to the solder ball pads. The solder balls are reflowed to attach the package to a circuit board.

An advanced type of BGA package is a wafer-level BGA package. Wafer-level BGA packages have various names in the industry, including wafer level chip scale packages (WLCSP), among others. In a wafer-level BGA package, solder balls are mounted directly to the IC die when the IC die has not yet been singulated from its process wafer. As such, wafer-level BGA packages do not include a package substrate. Wafer-level BGA packages can therefore be made very small with high pin out, compared to other IC package types including typical BGA packages.

For example, FIG. 1 shows a cross-section of an example typical wafer level integrated circuit package 100. As shown in FIG. 1, package 100 includes a die 106, first and second dielectric layers 102a and 102b, and an array of solder balls 104. Die 106 has a plurality of die terminals on the active surface of die 106 with I / O pads for signals of die 106. First dielectric layer 102a is formed on the surface of die 106 over the terminals, and second dielectric layer 102b is formed on the surface of first dielectric layer 102a. Solder balls 104 are formed on the second surface of the second dielectric layer 102b. Routing in the routing layer between the first and second dielectric layers 102a and 102b and vias through the first and second dielectric layers 102a and 102b connect the terminals of the die 106 to the solder balls 104. Connect For example, terminal 112 of die 106 may be connected to solder ball 108 by vias 114 passing through trace 110 and second routing layer 102b in the routing layer. 1 is shown.

The package 100 of FIG. 1 uses fan-in routing because the routing of the routing layer (eg, trace 110) is formed only within the area of the bottom surface of the die 106 in FIG. 1. 2 shows a cross-sectional view of an exemplary wafer level integrated circuit package 200 using fanout routing. Fanout routing is a type of routing that extends out of areas of the semiconductor die (above the material provided around the die). For example, as shown in FIG. 2, the package 200 includes a die 106, first and second dielectric layers 102a and 102b, an array of solder balls 104, and an insulating material 204. do. Insulating material 204 covers the four peripheral surfaces of the die and the top surface of the die in FIG. 2 and surrounds the die 106 without covering only the active surface of the die 106 where the die terminals are located. Like the package 100 of FIG. 1, the die 106 has a plurality of die terminals at the active surface of the die 106 with the I / O pads for the signals of the die 106, and the first dielectric layer 102a. Is formed on the surface of die 106 over the terminals, a second dielectric layer 102b is formed on the surface of the first dielectric layer 102a, and solder balls 104 are formed on the second of the second dielectric layer 102b. Is formed on the surface.

Routing formed in the routing layer between the first and second dielectric layers 102a and 102b and vias passing through the first and second dielectric layers 102a and 102b connect the terminals of the die 106 to the solder balls 104. Connect. For example, terminal 210 of die 106 may be connected to solder ball 206 by a trace 202 in the routing layer, and via 208 passing through second routing layer 102b. 2 is shown. Since the trace 202 extends out of the region of the semiconductor die (outside the region of the active surface of the die 106) over the insulating material 204 provided around the die 106, the trace 202 fans out. This is an example of routing. As such, the fanout routing provides a die 106 over an area larger than just that area of the die 106 that provides additional space for interconnects (eg, solder balls 104) to the package 200. Spreads the signals However, conventional techniques for forming wafer-level packages using fanout routing, such as package 200, are expensive and use a relatively large number of assembly steps.

In accordance with embodiments, an active semiconductor device (eg, a die) is attached to a semiconductor interposer substrate having through-vias, the semiconductor interposer substrate being used to interface the semiconductor device with a circuit board. The interposer substrate may include a multilayer circuit routing area that provides fanout routing and interconnections with the active semiconductor device. The active semiconductor device and the interposer substrate are encapsulated by an encapsulating material (eg, molding compound). Various types of integrated circuit packages include land grid array (LGA) packages, ball grid array (BGA) packages, flip chip LGA packages, flip chip BGA packages, and the like. And a poser substrate. For example, interconnects (eg, solder balls) may be attached to the surface of the interposer substrate to form a BGA package.

Embodiments of the present invention overcome the limitations of conventional fanout routing packaging. For example, embodiments having interposer substrates using through vias, such as through silicon vias (TSV), may have multiple routing layers in the interposer substrates, while typically 'S fanout packaging technologies are limited to single metal layer routing capacity.

For example, FIG. 3 illustrates a cross-sectional side view of an integrated circuit package 300, in accordance with an example embodiment. As shown in FIG. 3, the package 300 includes a die 106, a semiconductor substrate 306, and an insulating material 304. As shown in FIG. 3, the semiconductor substrate 306 has opposing first and second surfaces 312, 314. The semiconductor substrate 306 has a plurality of vias 310 that pass through the semiconductor substrate 306. Moreover, the semiconductor substrate 306 includes at least one routing layer. The routing layer may include fanout routing extending through the substrate 306 out of the area of the die 106. Die 106 is mounted to first surface 312 of semiconductor substrate 306. Insulating material 304 insulates die 106 on first surface 312 of semiconductor substrate 306.

The semiconductor substrate 306 may be made of a semiconductor material such as silicon or gallium arsenide. For example, semiconductor substrate 306 may be fabricated from a semiconductor wafer and singulated from the wafer. The semiconductor substrate 306 may be active (eg, including active integrated circuit logic) or passive (not including logic). As shown in FIG. 3, the semiconductor substrate 306 is covered at a first surface 312 having a first insulating layer 302a (eg, a passivation layer or a solder mask layer), and a second insulating layer 302c. And a core semiconductor layer 302b made of a semiconductor material covered at the second surface 314 having a passivation layer or solder mask layer, for example. The first routing layer may be covered by the first insulating layer 302a, or may be electrically conductive properties (eg, traces, via pads, which may be exposed through openings in the first insulating layer 302a). Etc.) on the first surface 312 of the core semiconductor layer 302b. In addition, the second routing layer may be covered by the second insulating layer 302c or electrically conductive properties (eg, traces, vias) that may be exposed through openings in the second insulating layer 302c. Pads, etc.) at the second surface 314 of the core semiconductor layer 302b. During the formation of a wafer according to standard semiconductor process / processing techniques (eg, using photolithography, etc.), the first and second insulating layers 302a, 302c and any number of routing layers may be formed of a core semiconductor layer ( 302b). The routing (eg, traces) and other electrically conductive properties (eg, via pads, solder ball pads, etc.) of the routing layers described herein include copper, aluminum, tin, nickel, gold, silver, It may be composed of an electrically conductive material, such as a metal such as solder or a combination of metals / alloys.

Vias 310 may be formed through semiconductor substrate 306 during in-wafer. For example, as shown in FIG. 3, vias 310 may be fully formed through core semiconductor layer 302b. When the semiconductor substrate 306 is a silicon substrate (eg, formed from a silicon wafer), the vias 310 may be referred to as through-silicon vias (TSVs).

Vias 310 may be filled or covered with an electrically conductive material (eg, a metal or combination of metals / alloys, including copper, aluminum, tin, gold, silver, solder, etc.). As shown in FIG. 3, vias 310 include via 316. Via 316 is formed in the first via pad 318 formed in the first routing layer at the first surface 312 of the semiconductor substrate 306, in the second routing layer at the second surface 314 of the semiconductor substrate 306. A second via pad 308 formed. Via 316 forms an electrical connection for terminal 320 of die 106 through substrate 306. Terminals 320 are connection points (eg, “die pads”) for electrical signals of die 106 (eg, input-output signals, power signals, ground signals, test signals, etc.). , "I / O pads", and the like. Any number of terminals 320 may be present on the surface of die 106, including ten, one hundred, and even larger numbers of terminals 320.

As shown in FIG. 3, terminal 320 is connected to via pad 308 (eg, by electrically conductive adhesive material). As such, terminal 320 is electrically connected via via pad 318 and via 316 to via pad 308 at second surface 314 of substrate 306. When the package 300 is mounted on a circuit board, the via pad 308 is directly or indirectly (eg, connected to the land pad of the circuit to electrically couple the signal of the terminal 320 to the land pad of the circuit board). Through solder balls). Additional terminals of die 106 may be electrically coupled to land pads of a circuit board in a similar manner.

The package 300 of FIG. 3, and additional package embodiments of the present invention, can be formed in a variety of ways. For example, the following subsection describes a process for forming integrated circuit packages with semiconductor substrates without the use of an intermediate carrier, and the process for forming integrated circuit packages with semiconductor substrates using an intermediate carrier. This is followed by a detailed description. Continued details are provided describing various examples of semiconductor interposer substrate routing and examples of IC packages having semiconductor interposer substrates. It is known from the teachings herein that the embodiments described herein can be combined in any manner as will be appreciated by those skilled in the relevant art.

A. Embodiments of Forming Packages Without Using a Carrier

Integrated circuit packages including semiconductor interposer substrates, such as package 300 of FIG. 3, may be formed in various ways. For example, FIG. 4 shows a flow diagram 400 that provides an exemplary process for assembling integrated circuit packages, in accordance with an embodiment. Flowchart 400 is described with respect to FIGS. 5-11 for purposes of illustration. Other structural and operational embodiments will be apparent to those skilled in the art based on the discussion provided herein. Flowchart 400 is described as follows.

Referring to flowchart 400, in step 402, a plurality of vias are formed through the first semiconductor wafer in the plurality of semiconductor substrate regions of the first semiconductor wafer. For example, FIG. 5 illustrates a top view of a first semiconductor wafer 500 in accordance with one embodiment of the present invention. Wafer 500 may be a silicon wafer, gallium arsenide wafer, or other wafer type. As shown in FIG. 5, wafer 500 has a surface 504 formed by a plurality of semiconductor substrate regions 502 (shown as dotted rectangles in FIG. 5). Each semiconductor substrate region 502 is configured to be divided into separate IC packages and packaged according to the process of the flowchart 400. Any number of substrate regions 502 can be included in the wafer 500, including ten, 100, 1000, and even larger numbers.

In accordance with step 402, a plurality of vias may be formed through the wafer 500 in each of the regions 502. For example, each region 502 may include a plurality of vias similar to the vias 310 shown in FIG. 3. Each via may be cylindrical in shape, narrow in width as shown in FIG. 3, or may have a different shape. In addition, each via may be filled and / or enclosed with an electrically conductive material, and may have formed via pads (eg, similar to via pads 318 and 308 shown in FIG. 3). Additionally, one or more routings to provide electrically conductive routing from the electrically conductive vias through wafer 500 to other electrically conductive properties (eg, conductive land pads for solder terminals, solder ball pads, etc.). Layers (and additional insulating layers) may be formed on the wafer 500.

In addition, FIG. 6 illustrates additional steps 602 that may be performed in the flowchart 400 of FIG. 4, in accordance with an embodiment. In step 602, the substrate regions can be tested on a first semiconductor wafer to determine a set of substrates to operate. In embodiments, substrate regions 502 may be used to determine operating substrates (eg, the substrates 306 of FIG. 3 that passed the test and non-operating substrates (substrates that failed the test). Can be tested on the wafer 500. As can be well known to those skilled in the art, any type and number of tests can be performed in the substrate regions 502. For example, functional tests can be performed ( For example, by applying probes to the conductive properties of the substrate regions 502 to provide test signals and measure test results, environmental tests, and the like can be performed.

In one embodiment, substrate regions 502 in the wafer 500 that are determined to not operate in accordance with step 602 may be displayed. For example, inks, laser markings or other forms of marking may be applied to substrates that do not work to indicate that they do not work. In this way, certain non-operating substrate areas can be distinguished so that they are not advanced / used further.

4, in step 404, a plurality of dies singulated from the second semiconductor wafer are attached to the surface of the first semiconductor wafer. For example, FIG. 7 shows a plan view of the second semiconductor wafer 700. Wafer 700 may be a silicon wafer, gallium arsenide wafer, or other wafer type. As shown in FIG. 7, wafer 700 has a surface 704 formed by a plurality of integrated circuit regions 702 (shown as small squares in FIG. 7). One or more integrated circuit regions 702 may be packaged into separate IC packages according to the process of flow diagram 400. Any number of integrated circuit regions 702 may be included in the wafer 700, including ten, 100, 1000, and even larger numbers.

Wafer 700 may be thinned by selective backgrinding. For example, the backgrinding process can be performed on the wafer 700 to reduce the thickness of the wafer 700 to the extent desired if desired and / or desired. However, thinning of the wafer 700 does not necessarily have to be performed in all embodiments. Wafer 700 may be thinned in any manner, as is well known to those skilled in the art. Wafer 700 will be made as thin as possible to help minimize the thickness of the resulting packages that will include integrated circuit regions 702. Moreover, each integrated circuit region 702 can be tested on the wafer 700. For example, test probes provide test input signals, receive test result signals, and test the terminals 320 (not shown in FIG. 7) on the wafer 700 to test each integrated circuit region 702. Can be applied to

Wafer 700 may be singulated / diced in any suitable way to physically separate the integrated circuit regions from one another, as is well known to those skilled in the art. For example, wafer 700 may be singulated by a saw, router, laser, or the like, in conventional or other ways. The singulation of the wafer 700 may vary from 10, 100, 1000, or even larger numbers of dies 106 (Figure 1), depending on the number of integrated circuit regions 702 of the wafer 700. Will effect 3).

In accordance with step 404 of FIG. 4, one or more dies singulated from a second semiconductor wafer (such as wafer 700 of FIG. 7) such that each substrate region 502 has at least one die attached thereto. May be mounted to the surface 504 of the first semiconductor wafer 500 (FIG. 5). For example, FIG. 8 illustrates a surface 504 of a wafer 500 with dies 106 attached thereto such that die 106 is attached to each substrate region 502, according to one exemplary embodiment. Indicate the time. 9 shows a cross-sectional side view of a portion of a wafer 500 in which the shown first and second dies 106a and 106b are mounted in first and second substrate regions 502a and 502b, respectively. Dies 106 may be placed on substrates regions 502 in any manner, including through the use of pick-and-place devices, self-aligning processes, or other techniques. And / or may be located. Terminals of the dies 106 may be aligned with conductive land pads on the substrate regions 502 to combine the signals of the dies 106 with the routing of the substrates regions 502. For example, solder or other electrically conductive material (eg, metal or a combination of metals / alloys) can be used to couple the terminals to the conductive pads. The adhesive material may be applied to the surfaces of the substrate regions 502 and / or the active surfaces of the dies 106 before placing the dies 106 on the substrate regions 502, and / or the After attachment, it may be inserted between the dies 106 and the substrate regions 502 (eg, an underfill material). The adhesive material may be used to help adhere the dies 106 to the substrate regions 502. Any suitable adhesive material can be used, including conventional die-adhesive materials, epoxies, adhesive films, and the like.

Additionally, the terminals of dies 106 may include signal / die pads of the dies and may include one or more metal layers formed on the die pads, referred to as under bump metallization (UBM) layers. . UBM layers are typically formed (eg metal deposition-plating) to provide a robust interface between the die pads and additional routing and / or a package interconnection mechanism such as studs or solder balls. (plating, sputtering, etc.) one or more metal layers.

Returning to FIG. 4, at step 406, the dies are insulated at the surface of the first semiconductor wafer. For example, FIG. 10 shows a cross-sectional side view of a portion of the wafer 500 shown in FIG. 9 with insulated dies, according to an example embodiment. The wafer 500 shown in FIG. 9 with insulated dies may be referred to as a “molded assembly” 1000. As shown in FIG. 10, the dies 106a and 106b attached to the substrates regions 502a and 502b are insulated by a molding compound 1002 applied to the surface 504 of the wafer 500. . Molding compound 1002 is an example of an insulating material that may be used to insulate dies 106 in wafer 500. The molding compound 1002 may be applied to the wafer 500 in any manner, including methods according to vacuum molding processes, and the like. For example, in one embodiment, a mold is formed so as to be positioned over the surface 504 of the wafer 500 (with attached dies 106), and the molding compound 1002 is formed from the mold (e.g., , In liquid form) and solidified to insulate the dies 106 on the wafer 500. Suitable insulating materials, such as molding compounds, are well known to those skilled in the art, including resins, epoxies, and the like.

Referring back to FIG. 4, at step 408, the first semiconductor wafer is singulated to distinguish a plurality of substrate regions to form a plurality of integrated circuit packages, each integrated circuit package having at least one of the dies. It includes one. For example, FIG. 11 shows a first IC package 1100a and a second IC package 1100b singulated from the molded assembly 1000 of FIG. 10. Several IC packages 1100 may be singulated from the molded assembly, including ten, 100 or even thousands IC packages 1100. As shown in FIG. 11, IC package 1100a includes a die 106a mounted on substrate 306a and a molding compound 1002 that insulates die 106a on substrate 306a. Moreover, IC package 1100b includes a die 106b mounted on a substrate 306b and a molding compound 1002 that insulates the die 106b on the substrate 306b. The substrate 306a is formed by singulating the substrate region 502a from the wafer 500, and the substrate 306b is formed by singulating the substrate region 502b from the wafer 500.

IC packages 1100 may be singulated from molded assembly 1000 in any suitable way to physically separate them from each other as is well known to those skilled in the art. For example, IC packages 1100 may be singulated by means of a saw, router, laser, or the like, in conventional or other ways. The IC packages 1100a and 1100b of FIG. 11 pass through the molding compound 1002 to separate the IC packages 1100a and 1100b from each other and from other IC packages 1100 (not shown in FIG. 10). It can be cut and singulated from the molded assembly 1000.

B. Embodiments of Forming Packages Using a Carrier

Integrated circuit packages including semiconductor interposer substrates, such as package 300 of FIG. 3, may be formed in various ways using carriers. For example, FIG. 12 shows a flow chart 1200 that provides an example process for assembling integrated circuit packages, according to one embodiment. Flowchart 1200 is described with reference to FIGS. 13-18 for purposes of explanation. Other structural and operational embodiments will be apparent to those skilled in the art based on the discussion provided herein. Flowchart 1200 is described as follows.

Referring to flowchart 1200, in step 1202, a plurality of vias are formed through the first semiconductor wafer in a plurality of semiconductor substrate regions of the first semiconductor wafer. For example, as described above with reference to FIG. 5, a plurality of vias may be formed through the wafer 500 in each region 502, similar to the vias 310 of FIG. 3. Moreover, similar to the description provided above, the additional step 602 shown in FIG. 6 is performed in flowchart 1200 to test substrate regions 502 on wafer 500 to determine a set of substrates to operate. Can be.

In step 1204, the first semiconductor wafer is singulated to form a plurality of substrates in accordance with the plurality of substrate regions. For example, referring to FIG. 5, wafer 500 may be in any suitable manner to physically separate substrate regions 502 from each other to form a plurality of separate substrates, as is well known to those skilled in the art. It can be singulated / diced. For example, wafer 500 may be singulated by means of a saw, router, laser, or the like, in conventional or other ways. The singulation of the wafer 500 may cause ten, 100, 1000, or even larger numbers of substrates 306 (in FIG. 3), depending on the number of substrate regions 502 of the wafer 500. Can cause.

12, in step 1206, the substrate is attached to the surface of the carrier. In one embodiment, the substrates are attached to the surface of the carrier, such as the substrate 306 singulated from the wafer 500 as described above. In one embodiment, a subset of singulated substrates (eg, substrates operating as described above) from the tested wafer 500 are attached to the carrier. Substrates that do not pass the test (eg, inoperable substrates) are not attached to the carrier.

For example, FIG. 13 shows a view of a carrier 1302 having a flat surface 1304 with a plurality of substrates 306 attached thereto, according to an example embodiment. Substrates 306 may be placed and / or positioned on surface 1304 of carrier 1302 in any manner, including through a pick-and-place apparatus, a self-aligning process, or other techniques. The adhesive material may be applied to the surface 1304 and / or the surfaces of the substrates 306 prior to placing the substrates 306 on the surface 1304 to adhere the substrates 306 to the surface 1304. . Any suitable adhesive material can be used, including epoxy, adhesive film, and the like.

In the example of FIG. 13, twenty five substrates 306 are shown attached to the surface 1304 of the carrier 1302. However, in embodiments, any number of substrates 306 may be attached to the surface of the carrier, including 10, 100, or even thousands of substrates 306. In one embodiment, the substrates 306 may be positioned adjacent to each other (eg, in contact with each other) on the surface 1304 of the carrier 1302. In another embodiment, the substrates 306 may be positioned with spaces spaced apart from the surface 1304 of the carrier 1302, as shown in FIG. 13. Substrates 306 may be spaced apart by a predetermined distance, as determined for a particular application.

Any suitable type of carrier may be used to accept the distinguished substrates, including carriers made of ceramic, glass, plastic, semiconductor materials (eg, silicon, gallium arsenide, etc.), metals, or other materials. The carrier may have a flat surface to receive substrates 306. Such carriers may have any contour shape, including round, rectangular, or other shapes. For example, FIG. 13 shows a carrier 1302 having a square (eg, square) shape. In one embodiment, the carrier 1302 may be a semiconductor wafer (eg, silicon or gallium arsenide), or may be made of other materials, such as plastic, ceramic, glass, metal, and the like.

Referring back to FIG. 12, at step 1208, a plurality of dies singulated from a second semiconductor wafer are attached to the substrates. For example, as described above, FIG. 7 shows a plan view of the second semiconductor wafer 700. Wafer 700 may be selectively thinned by backgrinding, and each integrated circuit region 702 of wafer 700 may optionally be tested on wafer 700. As described above, the wafer 700 may be singulated / diced in any suitable way to physically separate the integrated circuit areas from each other, to form discrete dies.

14 shows a view of a surface 1304 of a carrier 1302 having substrates 306 attached thereto and an IC die 106 attached to each substrate 306, in accordance with an example embodiment. Dies 106 may be placed and / or positioned on substrates 306 in any manner, including through pick-and-place devices, self-aligning processes, or other techniques. Terminals of the dies 106 may be aligned with conductive land pads on the substrates 306 to combine the signals of the dies 106 with the routing of the substrates 306. For example, solder or other electrically conductive material (eg, metal or a combination of metals / alloys) may be used to couple the terminals to the conductive pads. The adhesive material may be applied to the surfaces of the substrates 306 and / or the inoperative surfaces of the dies 106 prior to placing the dies 106 on the substrates 306, and / or attach It may then be inserted between the dies 106 and the substrates 306 (eg, underfill material). The adhesive material may be used to help adhere the dies 106 to the substrates 306. Any suitable adhesive material can be used, including conventional die-attach materials, epoxies, adhesive films, and the like.

For example, FIG. 15 shows a cross-sectional view of a portion of carrier 1302, according to one embodiment. As shown in FIG. 15, substrates 306a and 306b are attached to surface 1304 of carrier 1302. As shown in FIG. 3, the substrates 306a, 306b have opposing first and second surfaces 312, respectively, having second surfaces 314 attached to the substrate 1304 of the carrier 1302. , 314). Die 106a is attached to first surface 312 of substrate 306a and die 106b is attached to first surface 312 of substrate 306b. As described herein, dies 106 are attached to substrates 306 using electrically conductive plating, studs, or bumps as signal interconnections between each die 106 and substrate 306. Can be. Moreover, as described above, the terminals of dies 106 include signal pads of dies 106 and may include one or more metal layers formed on the die pads, referred to as UBM layers.

Additionally, the terminals of dies 106 may include signal / die pads of the dies and may include one or more metal layers formed on the die pads, referred to as under bump metallization (UBM) layers. UBM layers are typically formed (eg metal deposition-plating) to provide a robust interface between the die pads and additional routing and / or a package interconnection mechanism such as studs or solder balls. (plating, sputtering, etc.) one or more metal layers.

Referring back to FIG. 12, in step 1210, the dies are insulated on the carrier with an insulating material. For example, FIG. 16 shows a cross-sectional side view of a carrier 1302 having insulated dies and substrates, according to an example embodiment. As shown in FIG. 16, substrates 306a and 306b are attached to surface 1304 of carrier 1302 and dies 106a and 106b are attached to substrates 306a and 306b. Moreover, molding compound 1602 insulates substrates 306a and 306b and dies 106a and 106b on carrier 1302. Molding composite 1602 is an example of an insulating material that can be used to insulate substrates 306a and 306b and dies 106a and 106b on carrier 1302. The molding compound 1602 may be applied to the carrier 1302 in any manner, including methods according to vacuum molding processes, and the like. For example, in one embodiment, a mold is formed to be positioned over the surface 1304 of the carrier 1302 (with attached substrates and dies), and the molding compound 1602 is formed from the mold (eg, In liquid form) and solidified to insulate the substrates 306 and the dies 106 on the carrier 1302. Suitable insulating materials, including molding compounds, are well known to those skilled in the art, including resins, epoxies, and the like.

In step 1212, the carrier is detached from the insulated dies and substrates to form a molded assembly comprising the insulating material that insulates the dies and the substrates. For example, FIG. 17 illustrates a cross-sectional side view of a carrier 1302 removed or detached from the insulated dies and substrates, according to an example embodiment. In FIG. 17, the substrates 306a and 306b, the dies 106a and 106b, and the molding compound 1602 form a molded assembly 1702 detached from the carrier 1302. Bottom surfaces of the substrates 306a and 306b are coplanar with the surface of the molded assembly 1702 (bottom surface of FIG. 17) and exposed. Otherwise, the dies 106a and 106b and the substrates 306a and 306b are insulated by the molding compound 1602 in the molded assembly 1702. The carrier 1302 may be detached from the molded assembly 1702 in any manner. For example, molded assembly 1702 can be stripped from carrier 1302, and molded assembly 1702 and / or carrier 1302 cause carrier 1302 to be detached from molded assembly 1702. May be heated or cooled to enable or enable, or the like. In one embodiment, molding compound 1602 does not remain on carrier 1302 after substrates 306a and 306b are desorbed, but rather substrates 306a and 306b are along carrier 1602 along molding compound 1602. To the substrates 306a and 306b more strongly than that to the carrier 1302 (eg, stronger than the adhesive material that attaches the substrates 306a and 306b to the carrier 1302) to allow detachment from the carrier 1302. can do.

12, in step 1212, the molded assembly is singulated to form a plurality of integrated circuit packages, each integrated circuit package having at least one of the dies and at least one of the substrates. It includes. For example, FIG. 18 shows a first IC package 1800a and a second IC package 1800b singulated from the molded assembly 1700 of FIG. 17. Several IC packages 1800 can be singulated from the molded assembly, including ten, 100 or even thousands IC packages 1800. As shown in FIG. 18, IC package 1800a includes a die 106a mounted on a substrate 306a and a molding compound 1702 that insulates the die 106a on the substrate 306a. Additionally, IC package 1800b includes die 106b mounted on substrate 306b and molding compound 1702 for encapsulating die 106b on substrate 306b.

IC packages 1800 may be singulated from molded assembly 1700 in any suitable way to physically separate them from each other as is well known to those skilled in the art. For example, IC packages 1800 may be singulated by means of a saw, router, laser, or the like, in conventional or other ways. The IC packages 1800a and 1800b of FIG. 18 pass through the molding composite 1602 to separate the IC packages 1800a and 1800b from each other and from other IC packages 1800 (not shown in FIG. 17). It can be cut and singulated from the molded assembly 1700. In one embodiment, the sawing of the substrates 306 to ensure that the molding compound 1702 is not present at the peripheral edges of the substrates 306a, 306b in the IC packages 1800a, 1800b. It may be performed directly adjacent to the peripheral edges (ie, peripheral substrate edges are exposed as shown in FIG. 18). Alternatively, the sawing allows the substrates 306a and 306b to remain some molding compound 1702 present to cover the peripheral edges of the substrates 306a and 306b in the IC packages 1800a and 1800b. Can be done at a distance from the peripheral edges of the edge (the surrounding substrate edges are not exposed).

C. Example Package Embodiments

As described above, such as package 300 (FIG. 3), packages 1100a and 1100b (FIG. 11), and packages 1800a and 1800b (FIG. 18), IC packages are described in embodiments. Can be formed in various ways. Such packages include semiconductor substrates, such as substrate 306 including through vias and routing to couple signals of mounted dies to package interconnects. Such vias and routing may be configured in any manner, including any number of vias and any number of routing layers.

For example, FIG. 19 illustrates a cross-sectional side view of a portion of an IC package 1900, in accordance with an example embodiment. Package 1900 is shown here to illustrate examples of routing that may be varied in various ways, as is well known to those skilled in the art from the teachings. As shown in FIG. 19, the package 1900 includes a die 106, a semiconductor substrate 1902, solder bumps 1904, and a ball interconnect 1906. Solder bump 1904 is present for mounting terminal 1940 of die 106 to substrate 1902. Ball interconnect 1906 is present for attaching substrate 1902 to a circuit board (not shown in FIG. 19). A certain number of solder bumps 1904 and / or ball interconnects 1904 may be present in embodiments. Package 1900 is further described as follows.

As shown in FIG. 19, routing is formed in the first surface 1938 of the substrate 1902 to route the signal from the solder bumps 1904 to the vias 1918 passing through the substrate 1902. For example, as shown in FIG. 19, the substrate 1902 may include a core insulating layer 1922, a first insulating layer 1924 formed on a core semiconductor layer 1922 on a first surface 1938, and a first insulating layer 1924 formed of a first insulating layer 1924. A first routing layer 1934 formed on the first insulating layer 1924, and a second insulating layer 1926 formed on the routing layer 1934. Via 1918 is a through via that passes completely through core semiconductor layer 1922. Via 1918 has a first via pad 1916 on a first surface of core semiconductor layer 1922 and a second via pad 1920 on a second surface of core semiconductor layer 1922. Trace 1912 is formed in routing layer 1934 that is connected to via pad 1916 through an opening in first insulating layer 1924 at the first end of trace 1912. Trace 1912 may also be referred to as a redistribution layer or redistribution interconnect. Land pads 1908 are formed on the traces 1912 through openings 1910 at a second insulating layer 1926 near or at the second end of the traces 1912. Solder bumps 1904 are attached to land pads 1908. Land pad 1908 may include multiple layers of electrically conductive material. For example, the land pad 1908 may be formed to provide a robust interface between the terminals 1940 and additional routing and / or a package interconnection mechanism such as studs or solder balls (eg, metal deposition (eg, metal deposition). metal deposition—plating, sputtering, etc.) may be a UBM layer comprising one or more metal layers. The metal layers may be of different metals and / or alloys to allow solder bumps 1904, which may include a first metal / alloy, to adhere to a trace 1912, which may be made of a second, different metal / alloy. Can be formed.

As shown in FIG. 19, trace 1912 is fanout routing provided by substrate 1902 for die 106. This is because trace 1912 extends above substrate 1902 out of the area of the active surface (surface 1942 of die 106) of die 106 facing substrate 1902. In other words, the trace 1912 extends out of the area between the die 106 and the substrate 1902 over the first surface 1938 of the substrate 1902. As such, trace 1912 fan-out from die 106 and substrate 1902 corresponds to the trace so that package 1900 can be more easily mounted on the circuit board (with as much land pad space as possible). Provide a larger surface area than the area of the die 106 for signals at terminals of the die 106 to be routed over. As shown in FIG. 19, the solder balls 1906 under the die 106 partially extend out of the area of the die 106 (to the right in FIG. 19). In yet another embodiment, solder balls 1906 may be fully positioned out of the area of die 106 (eg, further to the right of FIG. 19).

As shown in FIG. 19, routing is formed in the second surface 1940 of the substrate 1902 to route the signal from the vias 1918 to the solder balls 1906. For example, as shown in FIG. 19, the substrate 1902 is formed in the second routing layer 1936 formed on the core semiconductor layer 1922 at the second surface 1940, and in the routing layer 1936. And a third insulating layer 1928. Routing layer 1936 includes via pads 1920, traces 1932, and solder ball pads 1930 of vias 1918. Trace 1932 connects via pads 1920 and solder ball pads 1930. Via pad 1920, trace 1932, and solder ball pads 1930 are exposed through openings in third insulating layer 1928. Interconnect balls 1906 are formed in solder ball pads 1930. As such, electrical connections are made from the solder bumps 1904 through the semiconductor substrate 1902 to the land pads 1908, traces 1912, via pads 1916, vias 1918, via pads 1920, and traces. 1932, through solder ball pads 1930, is formed of interconnect balls 1906. The electrical connection electrically couples the signal at terminal 1940 of die 106 to a land pad on a circuit board on which package 1900 is mounted. In a similar manner, any number of electrical connections may be formed through the substrate 1902.

Although a single routing layer 1934 is shown as being on the first surface 1938 of the substrate 1902, a single routing layer 1936 is shown as being on the second surface 1940 of the substrate 1902. There may be any number of additional routing layers on either or both of the surfaces 1938, 1940 to route signals through 1902 to solder bumps 1904 and / or solder balls 1906. Moreover, in embodiments, interconnect balls 1906 may be formed directly on via pads 1920 and / or solder bumps 1904 may be formed directly on via pads 1916. In embodiments, solder bumps 1904 and / or interconnect balls 1906 may or may not be present to form various package types.

For example, FIGS. 3 and 20-22 show examples of IC packages that include a semiconductor interpose substrate in accordance with embodiments. The package 300 of FIG. 3 described above is an example of a land grid array (LGA) package. An LGA package such as package 300 is a type of surface mount package for integrated circuits (ICs) with an array of pads used to mount the package to a circuit board. The LGA package can be electrically connected to a printed circuit board (PCB) by the use of a socket (with pins) or by soldering the pads directly to the board.

20 shows a side cross-sectional view of a ball grid array (BGA) package 2000. The BGA package 2000 is similar to the package 300 of FIG. 3, adding an array of solder balls 2002 attached to the solder ball pads at the second surface 314 of the substrate 306. The solder balls 2002 may be reflowed to attach the BGA package 2000 to the circuit board. The solder balls 2002 may be attached to the substrate 306 when in-wafer (eg, to the wafer 500 in the further process of the flowchart 400), or after the substrate 306 is separated from the wafer. .

21 shows a side cross-sectional view of another LGA package 2100. LGA package 2100 is an array of solder bumps 2104 attached to terminals of die 106 to mount die 106 to land pads on first surface 312 of substrate 306. Is a type of LGA package similar to LGA package 300 of FIG. The LGA package 2100 of FIG. 21 may be referred to as a flip chip LGA package.

22 shows a side cross-sectional view of a ball grid array (BGA) package 2200. The BGA package 2200 adds an array of solder bumps 2104 attached to the terminals of the die 106 to mount the die 106 with land pads on the first surface 312 of the substrate 306. Which is a type of BGA package similar to the BGA package 2000 of FIG. 20. The BGA package 2200 of FIG. 22 may be referred to as a flip chip BGA package.

In embodiments, various forms of interconnects may be formed on the second surface 314 of the substrate 306 to attach the packages to the circuit boards. Examples of such interconnections include BGA packages, pins (eg, pin grid array packages (PGAs)), posts, or other types of interconnects. Such interconnections may be applied to the substrates in any manner, including methods in accordance with conventional and appropriate techniques.

In embodiments, the semiconductor substrates included in the IC packages (eg, package 300, packages 1100a, 1100b, packages 1800a, 1800b, etc.) may be active (active) or passive (passive). For example, Figure 19 shows a substrate 1902 that optionally includes active integrated circuit logic 1950. When present, active integrated circuit logic 1950 causes the substrate 1902 to become an active semiconductor substrate. When not present, the substrate 1902 is a passive semiconductor substrate.Logic 1950 is a type of logic (eg, transistors, logic gates, etc.), such as processing logic, configured to perform certain logic functions. Logic 1950 may be coupled to routing in the substrate 1902 and / or vias that are electrically coupled to the signals of the die 106.

conclusion

While various embodiments of the invention have been described above, it should be understood that they have been presented by way of example only, and not limitation. It will be apparent to those skilled in the art that various changes in form and detail may be made herein without departing from the spirit and scope of the invention. Therefore, the breadth and scope of the present invention should not be limited by any of the above-described exemplary embodiments, but rather should be defined only in accordance with the following claims and their equivalents.

Claims (15)

A method of creating an integrated circuit package,
Forming a plurality of vias through the first semiconductor wafer in a plurality of semiconductor substrate regions of a first semiconductor wafer;
Attaching a plurality of dies singulated from a second semiconductor wafer to a surface of the first semiconductor wafer;
Encapsulating the dies at the surface of the first semiconductor wafer; And
Singulating the first semiconductor wafer to separate the plurality of semiconductor substrate regions to form a plurality of integrated circuit packages,
Each of the plurality of integrated circuit packages includes at least one of the dies, a substrate corresponding to one of the plurality of semiconductor substrate regions, and an interconnect connecting each of the plurality of integrated circuit packages with a circuit board. Including,
The substrate comprises at least one routing layer, each of the at least one routing layer including fanout routing extending out of the dies,
At least a portion of the interconnection is located outside the area of the dies. The method of claim 1, wherein the first semiconductor wafer is a silicon wafer and the vias are through-silicon vias.
The method according to claim 1,
Testing the plurality of semiconductor substrate regions of the first semiconductor wafer to determine a set of substrate regions that operate prior to the singulating step. The method according to claim 1,
Forming the routing layer on a surface of the first semiconductor wafer in each of the plurality of semiconductor substrate regions. The method of claim 1, wherein the attaching step,
Mounting at least one of the dies to each of the plurality of semiconductor substrate regions using an array of solder bumps. The method according to claim 1,
Forming a plurality of interconnect balls on a second surface of said first semiconductor wafer prior to said singulating;
Wherein each of the plurality of integrated circuit packages comprises interconnect balls of the plurality of interconnect balls used to interface each of the plurality of integrated circuit packages with a circuit board. The system of claim 1, wherein an array of electrically conductive pads on a surface of each of the plurality of integrated circuit packages includes a land grid array package for each of the plurality of integrated circuit packages. As used to interface with a circuit board. A method of creating an integrated circuit package,
Forming a plurality of vias through the first semiconductor wafer in a plurality of semiconductor substrate regions of a first semiconductor wafer;
Singulating the first semiconductor wafer to form a plurality of substrates corresponding to the plurality of semiconductor substrate regions;
Attaching the substrates to a surface of a carrier;
Attaching a plurality of dies singulated from a second semiconductor wafer to the substrates;
Encapsulating dies on the substrates with the encapsulating material in the carrier;
Detaching the carrier from the insulated dies and substrates to form a molded assembly comprising the insulating material insulating the dies and substrates; And
Singulating the molded assembly to form a plurality of integrated circuit packages,
Each of the plurality of integrated circuit packages includes an interconnect connecting at least one of the plurality of dies, at least one of the substrates, and each of the plurality of integrated circuit packages with a circuit board,
Each of the substrates comprises at least one routing layer, each of the at least one routing layer including fanout routing extending out of the dies,
At least a portion of the interconnection is located outside the area of the dies. The method of claim 8, wherein the first semiconductor wafer is a silicon wafer and the vias are through-silicon vias.
The method according to claim 8,
Testing the plurality of semiconductor substrate regions of the first semiconductor wafer to determine a set of substrate regions that operate prior to the singulating the first semiconductor wafer. As an integrated circuit package,
A silicon substrate having opposing first and second surfaces, a plurality of vias through the silicon substrate, and a routing layer on at least the first surface of the silicon substrate;
A die mounted on the first surface of the silicon substrate; And
An insulating material insulating the die on the first surface of the silicon substrate; And
An interconnect connecting said integrated circuit package with a circuit board,
The routing layer includes fanout routing extending out of the die,
At least a portion of the interconnection is located outside an area of the die. The method of claim 11,
And a plurality of solder bumps attaching the die to the first surface of the silicon substrate. The method of claim 11,
And a plurality of interconnect balls attached to the second surface of the silicon substrate. The method of claim 11,
And further comprising an array of electrically conductive pads on said second surface of said silicon substrate used to interface said integrated circuit package as a land grid array package. . The package of claim 11, wherein the vias are through-silicon vias.

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