KR101371512B1 - Apparatus and method for high speed basedband data storage - Google Patents

Abstract

The present invention relates to an apparatus and a method for verifying an error by storing high-speed baseband data, the present invention relates to a device for storing high-speed baseband data, in which a plurality of high-speed baseband data is connected in parallel with the memory, the high-speed baseband data A memory controller which provides an interface with the memory for input / output, a main controller which is connected in parallel with the memory controller when there are a plurality, and accesses the memory for high speed baseband data input / output through the memory controller; It is connected to the main control unit and includes an external interface for high speed baseband data input / output, and it is possible to implement a data storage and transmission, reception, and data error verification system through memory expansion during high speed baseband data verification. Modulation Demodulation, Scheduling, LMAC The baseband data write and read functions can be implemented without processing, or with the implementation of IP packets, the main function of the processor board, to verify the speed of the air interface and the presence of data errors.

Broadband wireless access communication system, high speed baseband, DDR memory, FPGA.

Description

High speed baseband data storage device and method {APPARATUS AND METHOD FOR HIGH SPEED BASEDBAND DATA STORAGE}

1 is a view showing the structure of a general wireless communication system,

2 is a diagram showing the structure of a storage device of a wireless communication system according to an embodiment of the present invention;

3 is a diagram illustrating a structure of a wireless communication system transmitter according to an exemplary embodiment of the present invention;

4 is a diagram illustrating an interface for memory control of an FPGA according to an embodiment of the present invention;

5 is a diagram illustrating memory driving timing according to an embodiment of the present invention;

6 is a view showing the structure of a wireless communication system receiver according to an embodiment of the present invention;

7 is a diagram illustrating the structure of a wireless communication system in an embodiment of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to baseband data error verification, and in particular, to verify the presence or absence of transmission data on a high-speed RF data path that can efficiently store or transmit high-speed baseband data and verify the stored data at a necessary time. It relates to a system structure for.

1 is a diagram illustrating a structure of a general wireless communication system.

Referring to FIG. 1, the received data is converted into a baseband signal from the IF (Intermediate Frequency) board 120 after the air interface 110 and then the modem board 130. 132, 134).

Data transmitted from the modem boards 130, 132, and 134 is transmitted to the process board 140 through a demodulation process, and the data processed by the process board 140 is passed through a relay line board or the process. Passed directly from the board 140 to the host system.

In the wireless communication system, in order to verify the air interface 110, that is, to verify the presence or absence of the error of the baseband data, the baseband data cannot be verified, and the process board 140 and the modem board 130, 132, 134) has a difficulty in verifying after the data is processed.

That is, there is a problem in that all of the functions of the process board 140 and the modem boards 130, 132, and 134 must be verified.

It is an object of the present invention to provide a fast baseband data storage device and method.

It is another object of the present invention to implement a baseband data write and read function without implementing functions such as modulation and demodulation, scheduling, LMAC processing, which are the main functions of the modem mode, and IP packet processing, which are the main functions of the processor board, in the wireless communication system. An object of the present invention is to provide an apparatus and a method for verifying speed and error of data.

According to a first aspect of the present invention for achieving the above object, in the device for storing the high-speed baseband data, in the case of a plurality of devices is connected in parallel with the memory, the high-speed baseband data input and output A memory controller providing an interface with a memory, a plurality of memory controllers connected in parallel with the memory controller and accessing the memory for high speed baseband data input / output through the memory controller, and a connection with the main controller And an external interface for high speed baseband data input / output.

According to a second aspect of the present invention for achieving the above object, in a system for verifying high-speed baseband data, when present in a plurality, it is connected in parallel with the memory and interfaces with the memory for high-speed baseband data input and output A memory control unit providing a memory controller, a main control unit connected to the memory control unit in parallel when the plurality of memory controllers are present, and accessing the memory for high-speed baseband data input / output through the memory control unit; A storage device including an external interface for baseband data input and output, and a terminal for monitoring and verifying high-speed baseband data connected through the external interface of the storage device and input / output to the storage device. .

According to a third aspect of the present invention for achieving the above object, a method of accessing a high-speed baseband data, the method comprising: connecting the memory in parallel to the memory control unit for high-speed baseband data input and output, and a high-speed base Connecting the memory controller to the main controller in parallel for band data input / output, connecting the main controller and an external interface for high speed baseband data input / output, and high-speed baseband data using the external interface. It characterized in that it comprises a process of accessing.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. In the following description, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

The present invention will now be described with respect to a fast baseband data storage device and method.

In a wireless communication system using 8x8 Multi Input Multi Output (MIMO) and Quadrature Amplitude Modulation (64QAM), a baseband data rate of approximately 10n Gbps is required for speed verification of an n Gbps air interface.

2 is a diagram illustrating a structure of a storage device of a wireless communication system according to an exemplary embodiment of the present invention.

Referring to FIG. 2, approximately 32 Gbps baseband data rate is required for verification of a 3 Gbps 8x8 MIMO air interface in a test system for broadband wireless access communication.

In the 8x8 MIMO air interface, the digitalized analog signal transmitted from the IF board is captured by each memory board, and the actual digital data is extracted from the captured data and verified.

As a conventional device, there is no device capable of storing data having a bandwidth of 32 Gbps, and a structure devised for this purpose is shown in FIG. 2. The apparatus of FIG. 2 is largely based on field-programmable gate arrays (FPGAs) 253 and 254 capable of controlling Double Data Rate Synchronous Dynamic RAM (DDR SDRAM) and data of DDR SDRAMs 255, 256, 257 and 258. It is composed of a main processor (Main Processor) 251 that can be loaded as needed

In the first FPGA 253, 254 can control one or two DDR SDRAM according to the DDR controller IP, the data of the DDR SDRAM (255, 256, 257, 258) and the FPGA (253, 254) The data is transmitted to the main processor 251 through a parallel address / parallel data bus between the main processors 251, and the transmitted data may be confirmed at the terminal 210 through the “Gigabit Ethernet” interface 252. The manner of operation between the boards (or units) will be described in detail below.

3 is a diagram illustrating a structure of a wireless communication system transmitter according to an exemplary embodiment of the present invention.

Referring to FIG. 3, a data transmission interface between each board 310, 330, and 350 uses a GXB7 interface, and an interface between the FPGAs 331, 335, 351, and 355 within the board is a DPA (Dynamic Phase Aligner). Use the interface.

The GXB interface is connected to the input / output ports of the FPGAs 331, 335, 351, and 355, and the input / output ports provide 2.5 Gbps of bandwidth per port, so that using multiple ports provides the necessary data rate of n Gbps. I can receive it.

The DPA interface is an interface between the FPGAs 331, 335, 351, and 355 in the board, and provides 1 Gbps of bandwidth per port so that more than n ports can be used to provide the speed of n Gbps.

The interface between the FPGA (331, 335, 351, 355) and the DDR SDRAM (332, 333, 336, 337, 352, 353, 356, 357) has a built-in DDR controller IP in the FPGA so that the DDR SDRAM ( 332, 333, 336, 337, 352, 353, 356, and 357 and the FPGAs 331, 335, 351, and 355 may be connected. In the embodiment of the present invention, the reason why the DDR SDRAM is selected as the storage device is that both the capacity and the data transfer rate are satisfied, and the storage method is as follows.

4 is a diagram illustrating an interface for memory control of an FPGA according to an embodiment of the present invention.

Referring to FIG. 4, the interface between the DDR SDRAM and the FPGA follows a standard 64-bit DDR control scheme, and the data transmission bandwidth between the DDR SDRAM and the FPGA is determined according to the DDR clock speed of FIG. 5 to be described below. DDR clocks can be up to 200 Mhz, but using them the same as the FPGA's GXB clock has a simple advantage in logic implementation.

Because, in order to increase the bandwidth of DDR SDRAM, when using a clock different from the GXB clock, a phase locked loop (PLL), an electronic circuit that matches the input signal with the reference frequency and the output signal, must be separately implemented. FPGA internal logic becomes complicated, such as the need to add buffering-related logic.

5 is a diagram illustrating memory driving timing according to an embodiment of the present invention.

Referring to FIG. 5, when the DDR controller performs a read operation on the DDR SDRAM, the read efficiency of the clock is only about 25% to 30% even when operating in the burst mode. The same is true for write operations. This is because an idle cycle, a command cycle, and a refresh cycle such as idle cycles when accessing the DDR SDRAM take up a large part of the actual access time. When the GXB clock is operated at 125 MHz, the active bandwidth is calculated as in Equation 1 below.

 125 MHz (clock source) × 2 (double data rate) × 64 bits (data bus size) × 0.25 (efficiency) = 4 Gbps

 In other words, using 125 MHz clock, it provides 4Gbps of bandwidth per DDR memory.

For example, to store data at 32 Gbps, eight DDR SDRAMs can be placed in parallel. In other words, if more DDR SDRAMs are placed in parallel, more data can be stored at higher speeds.

The transmitter of FIG. 2 stores data in advance in non-real time in DDR SDRAM of each memory board. At system startup, each SDRAM transfers data to the FPGA at 4 Gbps, and the FPGA collects the data and transmits them sequentially to the higher stages.

The data transfer bandwidth when transferring from the memory board to the IF board is "Number of DDR SDRAM × DDR SDRAM Data Bandwidth (4Gbps)". DDR controllers, DDR SDRAM separate data collection logic, and higher transport structure logic can be implemented inside the FPGA.

The wireless communication system can increase the data bandwidth according to the number of parallel arrangement of DDR SDRAM, which indicates that the desired transmission rate can be achieved through memory expansion during high-speed baseband data verification.

6 is a diagram illustrating a structure of a wireless communication system receiver according to an exemplary embodiment of the present invention.

Referring to FIG. 6, high-speed baseband data transmitted from the IF board 610 is transferred to each of the DDR SDRAMs 632, 633, 636, 637, 652, 653, 655, and 657 of the memory boards 630 and 650. Stored. Since the data transmitted from the IF board 610 is high speed, one bandwidth of the data cannot be accommodated in one DDR SDRAM.

For example, if 32 Gbps of data is transmitted from the IF board 610, and only 4 Gbps of bandwidth can be accommodated in the DDR SDRAM, if 8 parallel DDR SDRAMs are used to accommodate 32 Gbps of data, the data is accommodated. This is possible. In other words, the receiver can obtain the desired speed through memory expansion.

7 is a diagram showing the structure of a wireless communication system according to an embodiment of the present invention.

Referring to FIG. 7, in the wireless communication system of the present invention, the received data is converted through the air interface 710 and then converted into baseband data by the IF board 720, and then the modem boards 730, 732, and 734. Is sent to.

Data transmitted from the modem boards 730, 732, and 734 is transferred to the process board 740 through a demodulation process, and the packet data processed by the process board 740 is passed through the relay line board or the Data directly from the process board 740 is transferred to the host system.

The present invention can install memory boards (730, 732, 734) arranged in parallel to load all the data, and can monitor the presence of data errors in the terminal through a gigabit Ethernet interface, which is the main function of the modem mode The baseband data write and read function can be implemented without verification of modulation, demodulation, scheduling, LMAC processing, and IP packet processing, which are the main functions of the processor board. .

While the present invention has been described in connection with what is presently considered to be the most practical and preferred embodiment, it is to be understood that the invention is not limited to the disclosed embodiments, but is capable of various modifications within the scope of the invention. Therefore, the scope of the present invention should not be limited to the described embodiments, but should be determined not only by the scope of the following claims, but also by the equivalents of the claims.

  The present invention can implement data storage, transmission, reception, and data error verification system through memory expansion during high-speed baseband data verification, and it is processing and demodulation, scheduling, LMAC processing, which is the main function of modem mode, and IP packet processing, which is the main function of processor board. The baseband data write and read functions can be implemented to verify the speed of the air interface and the presence of data errors.

Claims (15)

In a device for storing high-speed BaseBand data, A memory controller which is connected in parallel with the memory when there are a plurality, and provides an interface with the memory for high speed baseband data input / output; A main control unit connected in parallel with the memory control unit when there are a plurality, and accessing the memory for high speed baseband data input / output through the memory control unit; And an external interface connected to the main controller and configured for high speed baseband data input / output. The method according to claim 1, And the memory controller is implemented using a field-programmable gate array (FPGA). The method according to claim 1, And the memory controller is connected to another memory controller using a dynamic phase aligner (DPA) interface when the memory controller is connected to the same board according to an implementation situation. The method according to claim 1, When the memory controller is connected to another board according to an implementation situation, the memory controller is connected to the other memory controller using a GXB (Gigabit Transceiver Block) interface. The method according to claim 1, And the data input / output speed of the main controller is increased by expansion of a memory. In a system for verifying fast baseband data, A memory controller which is connected in parallel with the memory if there are a plurality and provides an interface with the memory for high-speed baseband data input / output, and a memory controller which is connected in parallel with the memory controller when the number is present and the memory is controlled through the memory controller. A storage device including a main controller for accessing high speed baseband data input / output, an external interface connected to the main control portion, and an external interface for high speed baseband data input / output; And a terminal for monitoring and verifying high speed baseband data connected through the external interface of the storage device and input / output to the storage device. The method according to claim 6, The memory controller is implemented using an FPGA. The method according to claim 6, The memory controller is connected to another memory controller using a DPA interface when connected to the same board according to an implementation situation. The method according to claim 6, When the memory controller is connected to another board according to an implementation situation, the memory controller is connected to another memory controller using a GXB interface. The method according to claim 6, And a data input / output speed of the main controller is increased by expansion of the memory controller and memory. In a method of accessing fast baseband data, Connecting the memory to the memory controller in parallel for high speed baseband data input and output; Connecting the memory controller in parallel with the main controller for high speed baseband data input / output; Connecting the main controller and an external interface for high speed baseband data input / output; Accessing high speed baseband data using the external interface. 12. The method of claim 11, The memory control unit is implemented using an FPGA. 12. The method of claim 11, The memory controller is connected to another memory controller using a DPA interface when the memory controller is connected to the same board according to an implementation situation. 12. The method of claim 11, When the memory controller is connected to another board according to an implementation situation, the memory controller is connected to another memory controller using a GXB interface. 12. The method of claim 11, And the data input / output speed of the main controller is increased by expansion of a memory.

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