KR101369443B1 - 파워 복원 후 리로드 기능을 갖는 캐시 - Google Patents

파워 복원 후 리로드 기능을 갖는 캐시 Download PDF

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KR101369443B1
KR101369443B1 KR1020127025911A KR20127025911A KR101369443B1 KR 101369443 B1 KR101369443 B1 KR 101369443B1 KR 1020127025911 A KR1020127025911 A KR 1020127025911A KR 20127025911 A KR20127025911 A KR 20127025911A KR 101369443 B1 KR101369443 B1 KR 101369443B1
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KR20130036221A (ko
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필립 엔쥐
짐셰드 비. 미르자
안토니 아사로
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에이티아이 테크놀로지스 유엘씨
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    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/24Resetting means
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0862Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0866Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
    • G06F12/0868Data transfer between cache memory and other subsystems, e.g. storage devices or host systems
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10Providing a specific technical effect
    • G06F2212/1028Power efficiency
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/60Details of cache memory
    • G06F2212/6024History based prefetching
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02DCLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
KR1020127025911A 2010-03-03 2011-02-28 파워 복원 후 리로드 기능을 갖는 캐시 Active KR101369443B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US12/716,391 US8495300B2 (en) 2010-03-03 2010-03-03 Cache with reload capability after power restoration
US12/716,391 2010-03-03
PCT/IB2011/000597 WO2011107882A2 (en) 2010-03-03 2011-02-28 Cache with reload capability after power restoration

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KR20130036221A KR20130036221A (ko) 2013-04-11
KR101369443B1 true KR101369443B1 (ko) 2014-03-04

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US (1) US8495300B2 (enExample)
EP (1) EP2542975B1 (enExample)
JP (1) JP5570621B2 (enExample)
KR (1) KR101369443B1 (enExample)
CN (1) CN102971716B (enExample)
WO (1) WO2011107882A2 (enExample)

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US10135776B1 (en) 2011-03-31 2018-11-20 Zynga Inc. Cross platform social networking messaging system
US8522137B1 (en) 2011-06-30 2013-08-27 Zynga Inc. Systems, methods, and machine readable media for social network application development using a custom markup language
JP5803614B2 (ja) * 2011-11-29 2015-11-04 ソニー株式会社 不揮発性キャッシュメモリ、不揮発性キャッシュメモリの処理方法、コンピュータシステム
US9507534B2 (en) * 2011-12-30 2016-11-29 Intel Corporation Home agent multi-level NVM memory architecture
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WO2014030249A1 (ja) * 2012-08-24 2014-02-27 株式会社日立製作所 ボリュームのi/o性能の検証システム及び検証方法
US9183144B2 (en) * 2012-12-14 2015-11-10 Intel Corporation Power gating a portion of a cache memory
JP6092019B2 (ja) * 2013-06-25 2017-03-08 株式会社東芝 プロセッサ
KR101864831B1 (ko) * 2013-06-28 2018-06-05 세종대학교산학협력단 가상 캐시를 포함하는 메모리 및 그 관리 방법
US9772782B2 (en) 2014-05-21 2017-09-26 Seagate Technology Llc Non-volatile complement data cache
US20150363319A1 (en) * 2014-06-12 2015-12-17 Netapp, Inc. Fast warm-up of host flash cache after node failover
US10339023B2 (en) 2014-09-25 2019-07-02 Intel Corporation Cache-aware adaptive thread scheduling and migration
JP5974133B1 (ja) 2015-03-20 2016-08-23 株式会社東芝 メモリシステム
US10139891B2 (en) * 2015-06-23 2018-11-27 Honeywell International Inc. Systems and methods of power-safe control panel installation
US10423418B2 (en) 2015-11-30 2019-09-24 International Business Machines Corporation Method for maintaining a branch prediction history table
US10318428B2 (en) 2016-09-12 2019-06-11 Microsoft Technology Licensing, Llc Power aware hash function for cache memory mapping
US10489296B2 (en) 2016-09-22 2019-11-26 International Business Machines Corporation Quality of cache management in a computer
US10338855B2 (en) * 2016-12-08 2019-07-02 International Business Machines Corporation Optimized reading of multiple objects from tape
US10591978B2 (en) 2017-05-30 2020-03-17 Microsoft Technology Licensing, Llc Cache memory with reduced power consumption mode
US10241561B2 (en) 2017-06-13 2019-03-26 Microsoft Technology Licensing, Llc Adaptive power down of intra-chip interconnect
US10229061B2 (en) 2017-07-14 2019-03-12 International Business Machines Corporation Method and arrangement for saving cache power
JP7142289B2 (ja) * 2018-08-23 2022-09-27 日本電信電話株式会社 プロセッサ、多階層キャッシュメモリの制御方法、及び多階層キャッシュメモリの制御プログラム
US11507174B2 (en) * 2020-02-25 2022-11-22 Qualcomm Incorporated System physical address size aware cache memory
US11307634B1 (en) 2021-01-28 2022-04-19 Red Hat, Inc. Maintaining historical power level metadata for dynamic voltage and frequency scaling of processor instructions
US12164431B2 (en) * 2021-11-30 2024-12-10 Red Hat, Inc. Managing prefetching operations for drives in distributed storage systems
US12013784B2 (en) * 2022-01-07 2024-06-18 Centaur Technology, Inc. Prefetch state cache (PSC)
KR20240133288A (ko) 2023-02-28 2024-09-04 삼성전자주식회사 스토리지 시스템의 메모리를 관리하는 방법 및 장치

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Publication number Publication date
JP2013521559A (ja) 2013-06-10
JP5570621B2 (ja) 2014-08-13
EP2542975A4 (en) 2013-12-11
CN102971716A (zh) 2013-03-13
US8495300B2 (en) 2013-07-23
US20110219190A1 (en) 2011-09-08
WO2011107882A2 (en) 2011-09-09
CN102971716B (zh) 2015-06-17
KR20130036221A (ko) 2013-04-11
EP2542975B1 (en) 2018-02-21
WO2011107882A3 (en) 2011-11-17
EP2542975A2 (en) 2013-01-09

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