KR101346958B1 - Liquid crystal display device and method for fabricating of the same - Google Patents

Abstract

The present invention relates to a liquid crystal display device, comprising: a substrate having an uneven portion; A gate wiring formed in the recess; A gate insulating film formed on an entire surface of the substrate including the gate wirings; A data line formed on the gate insulating layer to intersect the gate line; A thin film transistor formed at an intersection of the gate line and the data line; By including a pixel electrode electrically connected to the thin film transistor, the area of the gate wiring on the substrate can be maintained or reduced as compared with the conventional one, and the surface area of the gate wiring can be increased to provide a liquid crystal display device having a high opening ratio. have.

Aperture ratio, signal delay, liquid crystal display, irregularities

Description

Liquid crystal display device and method for manufacturing the same {Liquid crystal display device and method for fabricating of the same}

1 is a plan view of one pixel of a liquid crystal display according to a first exemplary embodiment of the present invention.

FIG. 2 is a cross-sectional view of the liquid crystal display according to the first exemplary embodiment of the present invention, taken as II ′ of FIG. 1.

3A to 3C are flowcharts illustrating a method of manufacturing a liquid crystal display device according to a first embodiment of the present invention.

4 is a cross-sectional view illustrating a liquid crystal display device according to a second embodiment of the present invention.

5 is a cross-sectional view illustrating a liquid crystal display device according to a third embodiment of the present invention.

 DESCRIPTION OF THE REFERENCE NUMERALS (S)

 100, 200, 300: substrate 110, 210, 310: gate wiring

 120, 220, 320: Data wiring 130. 230. 330: Gate insulating film

 170, 270, 370: passivation layer 180, 280, 380: pixel electrode

 Tr: thin film transistor

The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device having a high opening ratio and a manufacturing method thereof.

Among flat panel displays, liquid crystal displays have excellent characteristics such as high brightness, high contrast, and low power consumption, and thus are used in a wide range of fields such as desktop computer monitors, notebook computer monitors, TV receivers, in-vehicle TV receivers, and navigation systems.

In recent years, the liquid crystal display device has become a large area and high quality. In this case, since the liquid crystal display device has a large area and a problem such as signal delay occurs, the problem is solved by increasing the width of the wiring or the thickness of the wiring provided in the liquid crystal display.

However, if the width of the wiring is increased, the aperture ratio of the liquid crystal display device is lowered. On the other hand, if the thickness of the wiring is increased, a step difference caused by the wiring is generated and the orientation characteristic is deteriorated. do.

SUMMARY OF THE INVENTION An object of the present invention is to provide a liquid crystal display device having a high opening ratio and excellent image quality characteristics and a manufacturing method thereof.

In order to achieve the above technical problem, an aspect of the present invention provides a liquid crystal display device. The liquid crystal display device includes a substrate having an uneven portion; A gate wiring formed in the recess; A gate insulating film formed on an entire surface of the substrate including the gate wirings; A data line formed on the gate insulating layer to intersect the gate line; A thin film transistor formed at an intersection of the gate line and the data line; And a pixel electrode electrically connected to the thin film transistor.

According to another aspect of the present invention, there is provided a method of manufacturing a liquid crystal display device. The manufacturing method includes the steps of forming an uneven portion on the substrate; Forming a gate wiring and a gate electrode in the recess; Forming a gate insulating film on an entire surface of the substrate including the gate wiring; Forming a semiconductor layer, a source / drain electrode, and a data line on the gate insulating film; And forming a pixel electrode electrically connected to the thin film transistor.

Hereinafter, embodiments of the present invention will be described in more detail with reference to the drawings of the liquid crystal display according to the present invention. The following embodiments are provided by way of example so that those skilled in the art can fully understand the spirit of the present invention. Therefore, the present invention is not limited to the embodiments described below, but may be embodied in other forms. In the drawings, the size and thickness of an apparatus may be exaggerated for convenience. Like numbers refer to like elements throughout.

1 and 2 are views illustrating a liquid crystal display device according to a first embodiment of the present invention. FIG. 1 is a plan view of one pixel of the liquid crystal display, and FIG. 2 is a cross-sectional view of FIG. 1 taken as II ′.

1 and 2, the substrate 100 on which the uneven portion is formed is located. A plurality of gate lines 110 and data lines 120 intersect each other on the substrate 100. The gate wiring 110 is formed to be filled in a recess formed in the substrate 100. In this case, when the liquid crystal display is enlarged, a signal delay through the gate line 110 is generated by increasing the thickness of the gate line 110 without increasing the width of the gate line 110. Not only that but also the opening ratio can be prevented from being lowered. Since the gate wiring 100 is formed to be filled in the recess, even if the thickness of the gate wiring 110 is formed thick, no step occurs. At this time, the yaw portion is formed to have a depth of 0.5 to 5 ㎛. When the depth of the recess is formed to be less than 0.5 μm, the thickness of the gate wiring 110 is reduced, and the width of the gate wiring 110 is increased, so that the aperture ratio is lowered. On the other hand, when the depth of the recess exceeds 5 μm, the gate line 110 is visible toward the side of the substrate 100 when the liquid crystal display is viewed from the side, so that the image quality at the side may be deteriorated. have.

The gate wiring 110 may be formed of at least one of a metal, a conductive polymer, and a conductive paste. For example, the metal may be at least one selected from the group consisting of Pt, Au, Ir, Cr, Mg, Ag, Ni, Al, Ti, Nd, Cu, and Mo. The conductive polymer may be any one of polythiophene, polyaniline, and polyacetylene. The conductive paste may be formed by containing any one of Ag, Cu, Al, and Ni in the polymer.

A gate insulating layer 130 is formed between the gate line 110 and the data line 120.

The gate insulating layer 130 may be an inorganic layer, an organic layer, or a stacked layer thereof. For example, the inorganic film may be a silicon oxide film, a silicon nitride film, or a laminated film thereof. In addition, the organic layer may be formed of at least one selected from the group consisting of benzocyclobutene, polyimide, polyethylene, polymethyl methacrylate, polyethylene, polypropylene, polyacrylonitrile, and parylene.

The thin film transistor Tr is formed at the intersection of the gate line 110 and the data line 120.

The thin film transistor Tr may include a gate electrode 112 branched from the gate line 110, the gate insulating layer 130 formed on the gate electrode 112, and the gate corresponding to the gate electrode 112. The semiconductor layer 150 may be disposed on the insulating layer 130, and the source / drain electrodes 122a and 122b may be positioned at both ends of the semiconductor layer 150, respectively. Here, the gate electrode 112 is formed by branching the gate wiring 112, and may be formed in the recessed portion. In addition, the semiconductor layer 150 may include an active layer 150a made of amorphous silicon and an ohmic contact layer 150b made of amorphous silicon doped with impurities.

A passivation layer 170 is further formed on the gate insulating layer 130 including the thin film transistor Tr. The protective film 170 may be formed of an inorganic film, an organic film, or a laminated film thereof. For example, the inorganic film may be a silicon nitride film, a silicon oxide film, or a laminated film thereof. The organic layer may be formed of any one selected from the group consisting of benzocyclobutene, polyacrylic resin, and polyimide resin.

The pixel electrode 180 is electrically connected to the thin film transistor Tr on the passivation layer 170. The pixel electrode 180 is a transparent electrode and may be formed of either ITO or IZO.

Although not shown, the liquid crystal display may further include an upper substrate disposed at a predetermined distance from the substrate on which the thin film transistor Tr is formed.

A color filter pattern and a black matrix pattern are formed on one surface of the upper substrate, and a common electrode may be further formed on the color filter.

As a result, when the liquid crystal display device becomes large in area, in order to prevent signal delay from occurring, recesses are formed in the substrate, and wirings are buried in the recesses, so that the wirings can be formed thick. The fall can be prevented. In addition, since the step difference caused by the gate wiring is reduced, the orientation characteristic can be prevented from being lowered.

3A to 3C are flowcharts illustrating a method of manufacturing a liquid crystal display device according to a first embodiment of the present invention.

Referring to FIG. 3A, a substrate 100 is provided. A first photosensitive film pattern 105 is formed on the substrate 100. The first photosensitive film pattern 105 may be formed by applying a photosensitive resin onto the substrate 100 and then exposing and developing the mask M1. In this case, the first photosensitive film pattern 105 may be formed of a negative photosensitive resin formed by removing the photosensitive film in a region corresponding to the blocking region of the mask M1. Alternatively, unlike the drawing, the photosensitive layer may be formed of a positive photosensitive resin formed by removing the photosensitive layer corresponding to the transmission region of the mask M1. In this case, in order to form the first photosensitive film pattern 105, a mask in which the transmission region and the blocking region of the mask M1 are designed to be opposite to each other is used.

According to the first photosensitive film pattern 105, the substrate 100 is etched, and the first photosensitive film pattern 105 is removed to form recesses in the substrate 100.

At this time, the depth of the recess is formed to have a depth of 0.5 to 5 ㎛. This is considered as the thickness and width of the gate wiring are determined according to the depth of the recess, as described above. That is, according to the depth of the recessed portion, the depth of the recessed portion is formed to have a depth of 0.5 to 5 μm in consideration of the aperture ratio and the image quality characteristic at the side surface.

Referring to FIG. 3B, after the first conductive layer 205 is formed on the entire surface of the substrate 100 on which the recess is formed, a second photosensitive layer pattern 125 is formed on the first conductive layer 115. .

The first conductive layer 115 may be formed of at least one of a metal, a conductive polymer, and a conductive paste.

When the first conductive film 115 is made of metal, the first conductive film 115 is deposited to be filled in the recess by sputtering or vacuum deposition. In addition, when the first conductive film 115 is a conductive polymer or a conductive paste, the first conductive film 115 is coated to be filled in the recess through a dip coating method, a spray method, a bar coating method, a screen printing method, a doctor blade method, or the like. In this case, the metal may be at least one selected from the group consisting of Pt, Au, Ir, Cr, Mg, Ag, Ni, Al, Ti, Nd, Cu, and Mo. The conductive polymer may be any one of polythiophene, polyaniline, and polyacetylene. The conductive paste may be formed by containing any one of Ag, Cu, Al, and Ni in the polymer.

The second photosensitive layer pattern 125 may be formed of a material having properties opposite to that of the first photosensitive layer pattern 105 in FIG. 3A. That is, when the first photosensitive film pattern 105 is formed of a negative photosensitive resin, the second photosensitive film pattern 125 may be formed of a positive photosensitive resin. In contrast, when the first photosensitive film pattern 105 is formed of a positive photosensitive resin, the second photosensitive film pattern 125 may be formed of a negative photosensitive resin. This is because the first photosensitive film pattern 105 and the second photosensitive film pattern 125 are formed such that regions opposite to each other are removed, so that the first photosensitive film pattern 105 and the second photosensitive film pattern ( This is because it is possible to form 125 through the same mask by forming the materials having the opposite characteristics. That is, the main portion formed on the substrate and the gate wiring to be described later may be formed using the same mask.

After the first conductive layer 115 is etched according to the second photosensitive layer pattern 125, the second photosensitive layer pattern 125 is removed, and the gate wirings positioned in the recesses as shown in FIG. 3C. 110 and the gate electrode 112 are formed.

A gate insulating layer 130 is formed on the entire surface of the substrate 100 including the gate wiring 110 and the gate electrode 112. The gate insulating layer 130 may be an inorganic layer, an organic layer, or a stacked layer thereof. For example, the inorganic film may be a silicon oxide film, a silicon nitride film, or a laminated film thereof. In this case, the gate insulating layer 130 may be formed through chemical vapor deposition or sputtering. In addition, the organic layer may be formed of at least one selected from the group consisting of benzocyclobutene, polyimide, polyethylene, polymethyl methacrylate, polyethylene, polypropylene, polyacrylonitrile, and parylene. In this case, the gate insulating layer 130 may be formed by any one method selected from the group consisting of spray coating method, bar coating method, doctor blade method, dip coating method, roll printing method, screen printing method.

A data line 120 intersecting the gate line 110 and a thin film transistor Tr positioned at an intersection area of the gate line 110 and the data line 120 are formed on the gate insulating layer 130. do. Here, the gate electrode 112 of the thin film transistor Tr is simultaneously formed when the gate line 110 is formed. The semiconductor layer 150 of the thin film transistor Tr sequentially forms an active layer 150a made of amorphous silicon and an ohmic contact layer 150b made of amorphous silicon doped with impurities. The source / drain electrodes 122a and 122b of the thin film transistor Tr are simultaneously formed when the data line 120 is formed. Furthermore, in order to simplify the process, the semiconductor layer 150 and the source / drain electrodes 122a and 122b may be formed using the same mask. That is, after sequentially stacking amorphous silicon, amorphous silicon containing impurities, and a conductive material on the gate insulating layer 130, the photoresist layer is sequentially etched according to the photosensitive film pattern formed through an exposure and development process using a mask. The semiconductor layer 150 and the source / drain electrodes 122a and 122b may be formed.

After the passivation layer 170 is formed on the gate insulating layer 130 including the thin film transistor Tr, a contact hole exposing a portion of the thin film transistor Tr is formed in the passivation layer 170.

The pixel electrode 180 is formed on the passivation layer 170 and is electrically connected to the thin film transistor exposed through the contact hole. The pixel electrode 180 is a transparent electrode, and may form ITO or IZO through a sputtering method.

Subsequently, although not shown in the drawings, the liquid crystal display may be manufactured by further bonding the upper substrate on which the color filter is formed onto the substrate 100 and forming the liquid crystal layer.

4 is a cross-sectional view illustrating a liquid crystal display device according to a second embodiment of the present invention. Here, except that the gate wiring and the gate electrode are formed according to the step of the uneven portion formed on the substrate, the liquid crystal display according to the first embodiment and the method of manufacturing the same are the same, and the repeated description is omitted.

Referring to FIG. 4, the substrate 200 on which the uneven portion is formed is located.

The gate line 210 and the data line 220 are formed to cross each other on the substrate 200.

The surface area of the gate line 210 may be increased by forming the stepped portion of the gate line 210 according to the stepped portion. As a result, even when the liquid crystal display device becomes large, a signal delay can be prevented from occurring without increasing the width or thickness of the gate wiring 210, and the aperture ratio can be prevented from decreasing.

At this time, the depth of the recess is formed to have a depth of 0.5 to 5 ㎛. When the depth of the recess is formed to be less than 0.5 μm, the thickness of the gate wiring 210 is reduced, and the width of the gate wiring 210 is increased, so that the aperture ratio is lowered. On the other hand, when the depth of the recess exceeds 5 μm, the gate wiring 210 is visible toward the side of the substrate 200 when the liquid crystal display is viewed from the side, so that the image quality at the side may be deteriorated. have. The gate line 210 may be formed of at least one selected from the group consisting of Pt, Au, Ir, Cr, Mg, Ag, Ni, Al, Ti, Nd, Cu, and Mo. In this case, the gate wiring 210 may be formed through a sputtering method in order to form according to the step of the uneven portion.

A gate insulating film 230 is interposed between the gate wiring 210 and the data wiring 220. Here, the gate insulating film 230 may be formed of an inorganic film, an organic film, or a stacked film thereof. In this case, the step formed by the uneven portion formed on the substrate 200 may be overcome by forming the gate insulating film 230 as an organic film or an organic / inorganic stacked film.

A thin film transistor Tr is formed at an intersection area of the gate line 210 and the data line 220, and the gate electrode 212 of the thin film transistor is formed by branching the gate line 210. That is, the gate electrode 212 may be formed according to the step difference of the uneven portion formed in the substrate 200. Alternatively, the gate electrode 212 may be formed in a region where the uneven portion is not formed.

A passivation layer 270 is formed on the entire surface of the substrate including the thin film transistor Tr, and a pixel electrode 280 electrically connected to the thin film transistor Tr is formed on the passivation layer 270.

In this case, although not shown in the drawing, an uneven portion may be formed in the gate insulating layer 230, and a data line 220 may be formed along the uneven portion.

After forming the uneven portion on the substrate 200 or the gate insulating layer 230, a wire may be formed according to the step of the uneven portion to increase the surface area of the wire. As a result, when manufacturing a large-area liquid crystal display device, it is not necessary to increase the thickness of the wiring or the area in which the substrate is located in order to prevent signal delay from occurring, so that the aperture ratio is lowered or the step difference caused by the wiring is increased. It can increase and it can prevent that an orientation characteristic falls.

5 is a cross-sectional view illustrating a liquid crystal display device according to a third embodiment of the present invention. Here, the liquid crystal display according to the second embodiment and the method of manufacturing the same are repeated except that a plurality of uneven parts are formed on the substrate, and gate wirings and gate electrodes are formed according to the steps of the plurality of uneven parts. The description will be omitted.

Referring to FIG. 5, a substrate 300 having a plurality of irregularities in which irregularities are formed is positioned. The uneven portion is formed in a region where a gate wiring to be described later will be formed and a region where a gate electrode branched from the gate wiring will be formed. At this time, the depth of the recess is formed to have a depth of 0.5 to 5 ㎛. As described above, the aperture ratio and the image quality characteristics of the side surface of the liquid crystal display are considered.

The gate wiring 310 and the gate electrode 312 where the gate wiring 310 is branched are formed along the step of the unevenness. The gate wiring 310 may be formed of at least one selected from the group consisting of Pt, Au, Ir, Cr, Mg, Ag, Ni, Al, Ti, Nd, Cu, and Mo. In this case, the gate wiring 310 may be formed through a sputtering method.

As the gate wiring 310 is formed along a plurality of stepped irregularities, the gate wiring 310 is formed in a corrugated shape, and thus has a larger surface area than the area occupied by the substrate 300. Thus, when the liquid crystal display device becomes large, it is not necessary to increase the width or thickness of the gate wiring 310 in order to prevent signal delay from occurring.

In addition, in the embodiment of the present invention, the gate electrode 312 is formed in the uneven portion formed on the substrate 300, but not limited to this, the gate electrode 312 may be formed in the region where the uneven portion is not formed. .

Thereafter, a gate insulating film 330 is formed on the entire surface of the substrate 300 including the gate wiring 310. As described above, the gate insulating layer 330 may be formed of any one of an inorganic layer, an organic layer, or a stacked layer thereof, and the step formed by the uneven portion formed on the substrate 300 may be formed by the gate insulating layer ( 330 can be overcome by forming an organic film or an organic / inorganic laminated film.

A thin film transistor is formed on the gate insulating layer 330 in the data line 320 intersecting the gate line 310 and in the cross region of the gate line 310 and the data line 320.

A passivation layer 370 is formed on the entire surface of the substrate including the thin film transistor Tr, and a pixel electrode 380 electrically connected to the thin film transistor Tr is formed on the passivation layer 370. In this case, although not shown in the drawing, the uneven portion may be formed in the gate insulating layer 330, and the data line 320 may be formed along the step of the uneven portion. Thus, when the liquid crystal display is enlarged, by maintaining or reducing the area in which wiring is located with respect to the substrate 300 and increasing the surface area of the wiring, signal delay occurs and opening ratio is reduced, It can prevent that an orientation characteristic falls by a level | step difference.

After forming the uneven portion on the substrate 300 or the gate insulating layer 330, a wire may be formed according to the step of the uneven portion to increase the surface area of the wire. As a result, when manufacturing a large-area liquid crystal display device, it is not necessary to increase the thickness of the wiring or the area in which the substrate is located in order to prevent signal delay from occurring, so that the aperture ratio is lowered or the step difference caused by the wiring is increased. It can increase and it can prevent that an orientation characteristic falls.

As described above, according to the present invention, the area occupied by the wiring is the same or decreased as in the related art, and as the surface area of the wiring is increased, a signal delay is prevented from occurring and the liquid crystal display device having excellent aperture ratio and its manufacture Provide a method.

In addition, after the uneven portion is formed in the substrate, the wiring is buried in the uneven portion or the wire is formed in accordance with the uneven portion, so that the step with respect to the thickness of the unevenness can be overcome, resulting in a decrease in the orientation characteristic. Can be prevented.

Although described above with reference to embodiments of the present invention, those skilled in the art can variously modify and change the present invention without departing from the spirit and scope of the invention described in the claims below. You will understand.

Claims (17)

A substrate having an uneven portion including a plurality of uneven portions and convex portions; A gate wiring formed in the uneven portion; A gate insulating film formed on an entire surface of the substrate including the gate wirings; A data line formed on the gate insulating layer to intersect the gate line; A thin film transistor formed at an intersection of the gate line and the data line; And And a pixel electrode electrically connected to the thin film transistor. And the gate wiring is formed in a corrugated form along a step of the uneven portion. The method of claim 1, And the recess has a depth of 0.5 to 5 [mu] m. delete delete delete delete delete The method of claim 1, And the gate wiring is formed of at least one of a metal, a conductive polymer, and a conductive paste. The method of claim 1, And the gate insulating film is formed of any one of an inorganic film, an organic film, and a stacked film thereof. Forming a concave-convex portion including a plurality of concave portions and concave portions on the substrate; Forming a gate wiring and a gate electrode on the uneven portion; Forming a gate insulating film on an entire surface of the substrate including the gate wiring; Forming a semiconductor layer, a source electrode, a drain electrode, and a data wiring on the gate insulating film; Forming a pixel electrode electrically connected to the drain electrode; The gate wiring and the gate electrode are formed in a corrugated form along the step of the uneven portion manufacturing method of the liquid crystal display device. 11. The method of claim 10, The recess is formed in a depth of 0.5 to 5 ㎛ manufacturing method of the liquid crystal display device. 11. The method of claim 10, And wherein the uneven portion and the gate wiring are formed using the same mask. 11. The method of claim 10, And the concave-convex portion is formed using a negative photosensitive film, and the gate wiring is formed using a positive photosensitive film. 11. The method of claim 10, And the concave-convex portion is formed using a positive photosensitive film, and the gate wiring is formed using a negative photosensitive film. delete delete delete

Images