KR101339082B1 - Wet plasma annealing apparatus and fabrication method of oxide semiconductor thin film transistor using the same - Google Patents

Wet plasma annealing apparatus and fabrication method of oxide semiconductor thin film transistor using the same Download PDF

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KR101339082B1
KR101339082B1 KR1020130019785A KR20130019785A KR101339082B1 KR 101339082 B1 KR101339082 B1 KR 101339082B1 KR 1020130019785 A KR1020130019785 A KR 1020130019785A KR 20130019785 A KR20130019785 A KR 20130019785A KR 101339082 B1 KR101339082 B1 KR 101339082B1
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South Korea
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supply pipe
plasma
substrate
gas
oxide semiconductor
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KR1020130019785A
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Korean (ko)
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김동철
최용원
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김동철
최용원
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67098—Apparatus for thermal treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

De-ionized water (DIW) is mixed with a direct-type atmospheric plasma to supply a large amount of O * radicals, thereby minimizing the void space existing in the oxide film. A method of manufacturing an oxide semiconductor thin film transistor of the present invention includes: forming a gate pattern on a substrate; Forming a gate insulating film on the gate pattern; Depositing and patterning an oxide semiconductor layer on the gate insulating layer; Performing an atmospheric pressure wet plasma heat treatment in which gaseous pure water (DIW) is supplied to the patterned oxide semiconductor layer; Forming an etch stop layer on the oxide semiconductor layer; Forming a source and a drain on the substrate on which the etch stopper film is formed; And forming a protective film on the substrate on which the source and the drain are formed.

Description

[0001] The present invention relates to a wet plasma heat treatment apparatus and a method of manufacturing an oxide semiconductor thin film transistor using the same,

The present invention relates to a wet plasma thermal processing apparatus and a method for manufacturing an oxide semiconductor thin film transistor using the same, and more particularly, to an atmospheric pressure wet plasma thermal processing apparatus capable of reducing the instability of a display oxide semiconductor and a manufacturing method of an oxide semiconductor thin film transistor ≪ / RTI >

In a conventional thin film transistor, the active layer is typically comprised of a semiconductor material such as amorphous silicon or polysilicon. However, when the active layer is made of amorphous silicon, it is difficult to realize a display device which operates at a high speed due to low charge mobility. Further, when the active layer is made of polycrystalline silicon, there is a problem that the mobility of the charge is high, but the threshold voltage is uneven and an additional compensation circuit is required.

On the other hand, when a thin film transistor is manufactured using a low temperature polysilicon (LTPS) process, a high cost process such as a laser heat treatment is required, so that the cost of equipment investment and management is high and it is applied to a substrate having a large area There is a difficult problem.

In particular, in order to realize a display panel such as an active matrix organic light emitting diode (AMOLED) and a unlimited definition (UD) thin film transistor-liquid crystal display (TFT-LCD) requiring high resolution and high driving speed The conventional amorphous silicon TFT has a problem of large area uniformity due to the low charge mobility, and thus it is not easy to apply the LTPS TFT to actual products.

Accordingly, research on a method for solving the above-described problems of a silicon semiconductor device using a thin film transistor based on an oxide semiconductor has attracted attention. Various materials such as ZnO, SnO2, IGZO (Indium Gallium Zinc Oxide), and IZO (Indium Zinc Oxide) have been extensively studied as oxide semiconductors.

These oxides exhibit higher mobility than amorphous silicon TFTs, have advantages over LTPS TFTs in terms of large area uniformity, and are relatively easy to process. In addition, unlike silicon semiconductors, there are many researches and product developments because ohmic contacts can be made without additional doping process when the source and drain electrodes are electrically connected to the semiconductor.

However, when an IGZO-based oxide semiconductor thin film is applied to a thin film transistor, it is difficult to ensure uniform quality of the oxide film due to irregular distribution of vacancy remaining after the oxide film forming process. As a result, a threshold voltage (Vth) shift occurs and the stability of the device deteriorates, which makes it difficult to mass-produce the device.

SUMMARY OF THE INVENTION It is an object of the present invention to provide an atmospheric pressure wet plasma thermal processing apparatus capable of reducing instability of a display oxide semiconductor and a method of manufacturing an oxide semiconductor thin film transistor using the same .

Another object of the present invention is to provide an atmospheric pressure wet plasma thermal processing apparatus which improves the efficiency of a TFT while lowering the manufacturing cost by performing the heat treatment process of the oxide semiconductor for display at a low temperature and an atmospheric pressure, and a manufacturing method of the oxide semiconductor thin film transistor using the same .

In order to solve such problems, in the present invention, a direct-type atmospheric plasma is mixed with deionized water (DIW) to supply a large amount of O * radicals, thereby minimizing the void space existing in the oxide film.

A method of manufacturing an oxide semiconductor thin film transistor according to an aspect of the present invention includes: forming a gate pattern on a substrate; Forming a gate insulating film on the gate pattern; Depositing and patterning an oxide semiconductor layer on the gate insulating layer; Performing an atmospheric pressure wet plasma heat treatment in which gaseous pure water (DIW) is supplied to the patterned oxide semiconductor layer; Forming an etch stop layer on the oxide semiconductor layer; Forming a source and a drain on the substrate on which the etch stopper film is formed; And forming a protective film on the substrate having the source and drain formed thereon.

The atmospheric pressure wet plasma heat treatment step can be performed with Ar and O 2 gas as a plasma source at a temperature of up to 400 ° C.

According to another aspect of the present invention, there is provided a wet plasma thermal processing apparatus comprising: a heating shelf capable of loading a substrate and capable of heating the substrate; A plasma head capable of reciprocating on a surface of the substrate to scan the substrate and including an electrode portion capable of applying a high frequency voltage; A plasma region in which a plasma is generated by a high frequency voltage applied to the electrode unit; A gas supply pipe for supplying a plasma source gas into the plasma region; A bubbler for making de-ionized water (DIW) into a gaseous pure water; A pure water supply pipe for connecting the gaseous pure water from the bubbler to the gas supply pipe; A first supply pipe for supplying a first gas contained in the plasma source gas to the gas supply pipe; And a second supply pipe for supplying a second gas contained in the plasma source gas to the gas supply pipe, wherein the second supply pipe is branched to a third supply pipe and a fourth supply pipe, and the third supply pipe is branched from the first supply pipe And the fourth supply pipe is connected to the bubbler.

The heating shelf may heat the substrate to a maximum of 400 ° C, and it is preferable to heat the substrate so that the temperature of the substrate has a uniformity within ± 2%.

Preferably, the wet plasma heat treatment apparatus is an atmospheric pressure wet-type plasma heat treatment apparatus, wherein the first gas is oxygen, and the second gas is Ar.

The wet plasma heat treatment apparatus may further include a mass flow controller for respectively regulating a gas supplied through the first, third, and fourth supply pipes, and the pipe for heating the gaseous pure water in the pure supply pipe And may further include a heating unit.

The temperature of the pure water in the liquid state in the bubbler is preferably 70 ° C to 100 ° C.

According to the present invention as described above, the void space in the oxide film used for the oxide semiconductor for display can be effectively reduced. Thin film transistors with minimized void space have improved stability and lifetime, and the threshold voltage is constant and quality is improved. Accordingly, the mass productivity of the final product, that is, the large area display, can be increased.

FIGS. 1A to 1E are cross-sectional views illustrating a method of manufacturing an oxide semiconductor according to an embodiment of the present invention.
2 is a schematic diagram of an apparatus for atmospheric pressure wet plasma heat treatment according to an embodiment of the present invention.
FIG. 3 illustrates a process of filling an empty space in an oxide film by an atmospheric pressure wet plasma heat treatment according to an embodiment of the present invention.

Advantages and features of the present invention and methods for achieving them will be apparent with reference to the embodiments described below in detail with the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Is provided to fully convey the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims. It is to be understood that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. In the present specification, the singular form includes plural forms unless otherwise specified in the specification. It is noted that the terms "comprises" and / or "comprising" used in the specification are intended to be inclusive in a manner similar to the components, steps, operations, and / Or additions.

Hereinafter, an atmospheric pressure wet-process plasma annealing apparatus according to an embodiment of the present invention and a method for manufacturing an oxide semiconductor using the same will be described in detail with reference to the accompanying drawings.

FIGS. 1A to 1E are cross-sectional views illustrating a method of manufacturing an oxide semiconductor according to an embodiment of the present invention.

First, as shown in FIG. 1A, a gate pattern 120 is formed on a substrate 110.

A silicon, glass, or plastic substrate is generally used as the substrate 110, and an ITO (Indium Tin Oxide) layer is sputtered as a gate material and the pattern 120 is formed by wet etching.

As a gate material, a metal electrode such as Al, Cr, Au, or Ni other than ITO or a metal electrode such as AZO (Al-Zn-Oxide), GZO (Ga-Zn-Oxide), ZTO -Zn-Oxide) or the like may be used. The thickness of the gate pattern 120 may be 100-200 nm.

Next, as shown in FIG. 1B, a gate insulating layer (SiO 2) 130 is formed and a channel layer (active layer) 140 is deposited.

The gate insulating layer 130 is formed by depositing SiO 2, Al 2 O 3, Si 3 N 4, or the like as a dielectric layer to a thickness of about 20 to 200 nm by using PECVD (Plasma Enhanced Chemical Vapor Deposition) or ALD (Atomic Layer Deposition).

In order to form a channel layer, an oxide semiconductor material such as IGZO or GZO is sputtered, and a heat treatment is performed. Then, a channel layer pattern 140 is formed through patterning.

Next, the formed channel layer pattern 140 is annealed using an atmospheric pressure wet plasma. The atmospheric pressure wet plasma heat treatment according to the embodiment of the present invention is intended to eliminate the vacancy present in the formed IGZO film and to prevent quality deterioration of the oxide film due to irregular distribution of the vacant space.

The atmospheric-pressure plasma heat treatment according to an embodiment of the present invention can be performed by supplying de-ionized water (DIW) in a gaseous state to a commonly used atmospheric plasma source while maintaining a plasma ignition state, So that additional radicals can be supplied. At this time, the heating temperature is maximized to 400 ° C so that the radicals generated in the plasma can be easily diffused in the oxide film.

In the embodiment of the present invention, the channel layer pattern is formed and then the atmospheric pressure wet plasma heat treatment is performed. However, before the step of sputtering the oxide semiconductor material, which is a material of the channel layer, and then patterning the channel layer, The atmospheric pressure wet plasma heat treatment according to an embodiment of the present invention may be performed and the atmospheric pressure wet plasma heat treatment may be applied to both the heat treatment before and after the channel layer patterning.

2 is a schematic diagram of an apparatus for atmospheric pressure wet plasma heat treatment according to an embodiment of the present invention.

2, the atmospheric pressure wet plasma heat processing apparatus according to an embodiment of the present invention comprises a processing module 210 and a control module 220. The processing module 210 includes a heater 211 The control module 220 includes a RF generator 225, gas feed pipes 221, 222, 242 and 243, an MFC (not shown) Mass Flow Controllers) 231, 232, and 233.

When the substrate 100 on which the channel layer made of an oxide semiconductor is formed is placed on the heating shelf 211, the substrate 100 is heated to 100 ° C to 400 ° C using a heater to form a primary Create an environment.

The heating shelf 211 can be heated so that the temperature of the substrate has a uniformity within ± 2%. An indirect heating method using a lift pin can be used to prevent glass warpage of the substrate.

The plasma head 212 is configured to scan the substrate 100 through a reciprocating motion on the surface of the substrate 100, and forms a direct type CCP (Cathode Coupled Plasma). As such, the plasma head 212 scans the substrate through the reciprocating motion on the substrate surface, so that uniform processing can be performed on the large-area substrate.

The plasma is formed by the radio frequency generated by the RF generator 225 of the control module 220 and the RF generator 225 may generate radio frequency of 13.56 MHz. The radio frequency thus generated is matched by the RF matching network 215 of the processing module to be transmitted to the plasma head 212 and forms a plasma of the gas delivered through the gas supply pipe 250.

As the plasma source, Ar and O2 gas are used, Ar is for plasma ignition, and O2 is for O * radical formation. To this end, the control module 220 is provided with an O2 tube 221 and an Ar tube 222 for supplying O2 and Ar, respectively. The Ar gas is used as a plasma source and the DIW bubbler 213 is used to convert pure water into a gaseous state so that the Ar pipe 222 is divided into two pipes 242 and 243, 221 and the other pipe 243 is connected to the DIW bubbler 213 of the processing module 210. Three mass flow controllers (MFCs) 231, 232 and 233 are provided to control the gas supplied through each gas pipe.

The DIW bubbler 213 supplies Ar gas to the DIW in a liquid state to make it into a gaseous state. The temperature of the pure water in the bubbler 213 is about 70 ° C and can be 100 ° C at the maximum.

The gaseous DIW is connected to a gas supply pipe 250 for supplying Ar gas and O2 gas, which are plasma source gases, through the DIW tube 214 and is supplied to the plasma head 212 together with Ar gas and O2 gas. The DIW gas thus generates additional O * radicals during plasma formation. The DIW tube 214 is preferably heated to maintain the DIW in a gaseous state, and may further include a tube heating unit.

Now, when O * radicals are supplied to the heated oxide film by mixing the CCP type atmospheric plasma and the gaseous DIW, the O * radicals are absorbed into the vacant space in the oxide film, thereby eliminating the vacant space. At this time, the plasma ignition state is maintained so that a large amount of O * radicals can be supplied by the gas mixture of vaporized H2O and Ar and O2.

FIG. 3 illustrates a process of filling an empty space in an oxide film by an atmospheric pressure wet plasma heat treatment according to an embodiment of the present invention.

As shown in FIG. 3, the radicals in the electrons e, ions I and radicals R generated by the plasma penetrate into the oxide film to fill the vacant space V.

The bottom of the substrate is heated so that the radical can diffuse smoothly in the oxide film, and the H2O is supplied to the plasma in the gaseous state so that the plasma abundantly contains radicals.

Because the radicals rather than the ions facilitate the chemical reaction to the vacant space, the empty space is easily filled and the atmospheric plasma method is used instead of the vacuum plasma to make the radical rich state. In order to enrich the oxygen radical, O 2 gas is used as the main process gas in the atmospheric plasma, and steam can be added to generate more radicals.

As described above, the oxide semiconductor formed by removing the voids has improved stability and can prevent a shift in the threshold voltage, so that a uniform quality can be obtained.

1C, the etch stop layer 150 is patterned with SiO2 or the like on the channel pattern 140. Then, as shown in FIG. 1D, Source and drain regions 161 and 162 are formed. The source / drain regions 161 and 162 may be formed using a transparent electrode material such as ITO.

Finally, as shown in FIG. 1E, an oxide semiconductor TFT is completed by depositing a passivation layer 170 with SiO 2 or the like and forming a contact pattern.

While the invention has been described in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the invention. Accordingly, the appended claims are intended to embrace all such modifications and variations as fall within the true spirit of the invention.

100, 110: substrate 120: gate
130: gate insulating film 140: channel
150: etching prevention film 161, 162: source and drain
170: Protection film 210: Processing module
220: Control module 211: Heating chuck
212: plasma head 213: bubbler
214: vasoconstrictor 221: oxygen tube
222, 242, 243: Ar pipe 250: gas supply pipe
225: RF generator 215: RF matching network
231, 232, 233: Mass Flow Controller (MFC)

Claims (10)

delete delete A heating shelf capable of loading a substrate and capable of heating the substrate;
A plasma head capable of reciprocating on a surface of the substrate to scan the substrate and including an electrode portion capable of applying a high frequency voltage;
A plasma region in which plasma is generated by a high frequency voltage applied to the electrode unit;
A gas supply pipe supplying a plasma source gas to the plasma region;
A bubbler for making de-ionized water (DIW) in liquid state into pure water in gaseous state;
A pure water supply pipe connecting the gaseous pure water from the bubbler to the gas supply pipe;
A first supply pipe supplying a first gas included in the plasma source gas to the gas supply pipe; And
A second supply pipe configured to supply a second gas included in the plasma source gas to the gas supply pipe,
And the second supply pipe is branched into a third supply pipe and a fourth supply pipe, the third supply pipe is connected to the first supply pipe, and the fourth supply pipe is connected to the bubbler. The method of claim 3,
The heating shelf is a wet plasma heat treatment apparatus for heating the substrate up to 400 ° C. 5. The method of claim 4,
And the heating shelf heats the substrate such that the temperature of the substrate has a uniformity within ± 2%. The method of claim 3, wherein the wet plasma heat treatment apparatus,
A wet plasma heat treatment apparatus, which is a normal pressure wet plasma heat treatment apparatus. The method of claim 3,
The first gas is oxygen,
And the second gas is Ar. The method of claim 3,
And a mass flow controller for respectively regulating the gas supplied through said first, third, and fourth supply lines. The method of claim 3,
And a tube heating unit for heating the gaseous pure water in the pure water supply pipe. The method of claim 3,
The temperature of the liquid pure water in the bubbler is 70 ℃ to 100 ℃ wet plasma heat treatment apparatus.
KR1020130019785A 2013-02-25 2013-02-25 Wet plasma annealing apparatus and fabrication method of oxide semiconductor thin film transistor using the same KR101339082B1 (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011077514A (en) 2009-09-04 2011-04-14 Semiconductor Energy Lab Co Ltd Method of manufacturing semiconductor device
JP4982619B1 (en) 2011-07-29 2012-07-25 富士フイルム株式会社 Manufacturing method of semiconductor element and manufacturing method of field effect transistor
KR20120084107A (en) * 2011-01-19 2012-07-27 전자부품연구원 Method of manufacturing oxide semiconductor thin film transistor and semiconductor equipment
KR20120096879A (en) * 2008-07-31 2012-08-31 가부시키가이샤 한도오따이 에네루기 켄큐쇼 A method for manufacturing a semiconductor device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20120096879A (en) * 2008-07-31 2012-08-31 가부시키가이샤 한도오따이 에네루기 켄큐쇼 A method for manufacturing a semiconductor device
JP2011077514A (en) 2009-09-04 2011-04-14 Semiconductor Energy Lab Co Ltd Method of manufacturing semiconductor device
KR20120084107A (en) * 2011-01-19 2012-07-27 전자부품연구원 Method of manufacturing oxide semiconductor thin film transistor and semiconductor equipment
JP4982619B1 (en) 2011-07-29 2012-07-25 富士フイルム株式会社 Manufacturing method of semiconductor element and manufacturing method of field effect transistor

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