KR101330250B1 - Luminescence device - Google Patents

Luminescence device Download PDF

Info

Publication number
KR101330250B1
KR101330250B1 KR1020100045658A KR20100045658A KR101330250B1 KR 101330250 B1 KR101330250 B1 KR 101330250B1 KR 1020100045658 A KR1020100045658 A KR 1020100045658A KR 20100045658 A KR20100045658 A KR 20100045658A KR 101330250 B1 KR101330250 B1 KR 101330250B1
Authority
KR
South Korea
Prior art keywords
layer
semiconductor layer
formed
metal
host substrate
Prior art date
Application number
KR1020100045658A
Other languages
Korean (ko)
Other versions
KR20100057004A (en
Inventor
윤형수
이정훈
Original Assignee
서울바이오시스 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 서울바이오시스 주식회사 filed Critical 서울바이오시스 주식회사
Priority to KR1020100045658A priority Critical patent/KR101330250B1/en
Publication of KR20100057004A publication Critical patent/KR20100057004A/en
Application granted granted Critical
Publication of KR101330250B1 publication Critical patent/KR101330250B1/en

Links

Images

Abstract

The light emitting device according to the present invention comprises a semiconductor layer comprising a host substrate, a p-type nitride semiconductor layer, an active layer and an n-type nitride semiconductor layer formed on the host substrate, and at least one metal layer formed between the host substrate and the semiconductor layer. The host substrate may include at least two metal plates.

Description

Light emitting device

The present invention relates to a light emitting device, and provides a light emitting device including a host substrate that is easily separated between chips.

Since the first GaN-based materials have been developed, various researches have been conducted to improve their characteristics as optical devices. There is a lot of research on how to improve the characteristics. In addition, GaN-based materials are expected to play a significant role in the fabrication of devices for use in the lighting market.

However, in order to use a semiconductor device using a GaN-based material for lighting, there are many improvements to the GaN-based semiconductor device, and many studies have been made to improve these problems. Among the problems of GaN-based devices, the most important issue is to use insulating sapphire as a substrate for growing a GaN-based semiconductor layer. After forming the semiconductor layer on the sapphire, the P and N two electrodes must be formed on the last layer to drive the device. That is, the problem that the emission area of the light is reduced by forming two electrodes in the direction in which the light is emitted.

In addition, in order to use GaN-based semiconductor devices for illumination, there is a limit in increasing internal quantum efficiency that can be realized due to the characteristics of semiconductor materials, and therefore, luminous efficiency should be increased by applying a large current. However, when a large current is applied, a lot of heat is generated in the vicinity of the PN junction. In the semiconductor device having the above-described structure, since the heat is not sufficiently discharged, it is impossible to implement a large current device, and it is difficult to secure the reliability of the device by such heat. A problem occurred.

To solve this problem, a method of making and using a GaN substrate and a method of making a device using a SiC substrate, which is a conductive substrate, have been proposed. However, the price of these substrates is expensive, which is an obstacle in expanding the market in terms of price. In addition, in the related art, a method of increasing the light emitting efficiency of the device using a flip chip has been used, but there are problems of difficulty of the process and a decrease in yield.

Therefore, recently, the method of increasing the light efficiency by removing the substrate has been in the spotlight. This formed a GaN-based semiconductor layer on the sapphire growth substrate, and then bonded the GaN-based semiconductor layer to a host substrate capable of supporting the GaN-based semiconductor layer from which the growth substrate was removed before removing the growth substrate. In addition, when a conductive substrate, that is, a metal, is used as the host substrate, there is a problem that it is difficult to separate the light emitting chips by cutting the host substrate.

Therefore, the present invention can facilitate the separation between the light emitting cells through the host substrate of the structure that is easy to remove the lower growth substrate and the separation between the cells in order to solve the above problems, it is possible to improve the productivity in mass production Provided is a light emitting device.

The present invention provides a semiconductor layer comprising an n-type nitride semiconductor layer, an active layer and a p-type nitride semiconductor layer; A transparent electrode layer provided on the p-type nitride semiconductor layer of the semiconductor layer; A bonding metal layer provided on the transparent electrode layer and including at least one of nickel, zinc, silver, gallium, ruthenium, platinum, or iridium; And a host substrate provided on the bonding metal layer, wherein a layer including at least one of tungsten, nickel, molybdenum, indium, or tin is stacked in at least two layers.
At least two layers of the host substrate may include a first metal plating layer and a second metal plating layer.
The second metal plating layer may be provided on the first metal plating layer, and may have a small width.
The light emitting device may include the first metal plating layer on the gold metal layer.

delete

delete

delete

delete

delete

delete

delete

delete

delete

delete

delete

delete

delete

As described above, when the individual light emitting devices are manufactured by supporting the patterned semiconductor layer using the host substrate on which the cutting patterns are formed, it is possible to easily separate the devices, and in the case of mass production, it is important to improve productivity. Can act as a factor.

Moreover, the problem which arises by the difference in the thermal expansion coefficient between a metallic host substrate and a semiconductor layer can also be solved.

In addition, the host substrate may be manufactured externally and grown directly on the semiconductor layer without performing pressure bonding, thereby shortening the process time and preventing damage to the semiconductor layer due to pressure.

1 is a cross-sectional perspective view for explaining a light emitting device according to the present invention.
2 is a view for explaining a host substrate according to the present invention.
3 and 4 are cross-sectional views illustrating a method of manufacturing a light emitting device according to another embodiment of the present invention.
5 to 10 are views for explaining the manufacturing method of the light emitting device according to the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. It will be apparent to those skilled in the art that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, It is provided to let you know. Wherein like reference numerals refer to like elements throughout.

1 is a cross-sectional perspective view for explaining a light emitting device according to the present invention.

Referring to FIG. 1, a light emitting device according to the present invention includes a semiconductor layer 120, 130 and 140, and a host substrate 300 having a predetermined cutting pattern provided on the semiconductor layers 120, 130 and 140. .

The semiconductor layers 120, 130, and 140 refer to the N-type semiconductor layer 120 and the P-type semiconductor layer 140. In addition, the semiconductor device further includes an active layer 130 formed between the N-type semiconductor layer 120 and the P-type semiconductor layer 140. In addition, a buffer layer (not shown) may be further included below the N-type semiconductor layer 120. In addition, the ohmic electrode layer may be further included on the P-type semiconductor layer 140. Of course, the present invention is not limited thereto, and may further include various semiconductor material layers capable of improving luminous efficiency.

At least one metal layer for bonding provided between the host substrate 300 and the semiconductor layers 120, 130, and 140 is included. As the host substrate 300, at least one of gold, silver, copper, tungsten, nickel, platinum, zinc, aluminum, molybdenum, silicon, germanium, titanium, gallium, indium, tin, and lead is used. The host substrate 300 may be formed on the semiconductor layers 120, 130, and 140 through a growth method, a plating method, or the like, and may be manufactured through a separate process, and then, on the semiconductor layers 120, 130, and 140. You can also bond to.

The cutting pattern is formed at the edge of the host substrate 300. Preferably, the semiconductor layer is formed in an unbonded region. In the present embodiment, the shape of the cutting pattern is formed in an uneven shape in the edge region of the host substrate 300.

Separate electrodes may be formed under the semiconductor layers 120, 130, and 140, and electrodes may also be formed on the host substrate 300.

2 is a view for explaining a host substrate according to the present invention.

FIG. 2A is a perspective view of the host substrate, FIG. 2B is a plan view, FIG. 2C is a sectional view taken along line II ′ of FIG. 2B, and FIG. 2D is a sectional view taken along line II-II ′ of FIG. 2B.

2A to 2D, the light emitting device host substrate 300 according to the present invention includes a conductive plate 200 and a plurality of bonding metal layers 210 formed in predetermined regions under the conductive plate 200. A cutting pattern 215 is formed on the conductive plate 200 between the bonding metal layers 210.

The cutting pattern 215 is preferably at least one through hole. The cutting pattern 215 is not limited to the through hole, and may have various structures and shapes that may facilitate the cutting of the host substrate 300. As shown in FIGS. 2A and 2D, the cutting patterns 215 may be formed in a plurality of quadrangular shapes aligned in the cutting plane direction at the center of the region between the bonding metal layers 210. Of course, it is not limited to this, various shapes are possible for the convenience of cutting. That is, when viewed in plan, various shapes including a polygonal shape, a circular shape, an elliptic shape, a linear shape, a mesh shape, and the like are possible. At this time, if the width / diameter of the through hole is too large, a problem arises in that the lower semiconductor layer cannot be supported. In the present embodiment, when the area between the bonding metal layers 210 is 1, the ratio of the area penetrated by the through hole is 0.05 to 0.9. Preferably it is 0.15 to 0.7. More preferably, it is made 0.2 to 0.6.

The host substrate 300 includes at least one of gold, silver, copper, tungsten, nickel, platinum, zinc, aluminum, molybdenum, silicon, germanium, titanium, gallium, indium, tin, and lead.

Hereinafter, the vertical light emitting device formed using the host substrate 300 having the predetermined cut pattern as described above will be described.

3A, 3B and 4 are cross-sectional views illustrating a method of manufacturing a light emitting device according to another embodiment of the present invention.

3A and 3B, the semiconductor layers 120, 130, and 140 patterned on the growth substrate 110 are bonded to the host substrate 300. In this case, predetermined metal layers 150 and 155 are formed on the patterned semiconductor layers 120, 130, and 140 to be bonded to the bonding metal layer 210 of the host substrate 300. In this case, the bonding is performed by mounting the host substrate 300 on the semiconductor layers 120, 130, and 140 on which the metal layers 150 and 155 are formed, and the metal layers 150, 155 and the host substrate of the semiconductor layers 120, 130, and 140, respectively. The bonding metal layers 150 and 155 of (300) are matched and then pressed to bond the two metal layers 150, 155 and 210 to bond the patterned semiconductor layers 120, 130 and 140 to the host substrate 300. do.

Referring to FIG. 4, the growth substrate 110 under the patterned semiconductor layers 120, 130, and 140 is separated, and then the host substrate 300 is processed to manufacture individual light emitting devices.

The growth substrate 110 is separated from the growth substrate 110 under the semiconductor layers 120, 130, and 140 through a separation process using a laser. In this case, the semiconductor layers 120, 130, and 140 may be bonded to the host substrate 300 to be supported when the growth substrate 110 is separated. Subsequently, individual light emitting devices are manufactured by cutting the host substrate 300 between the bonding metal layers 210, and a cutting pattern 215 including through holes is formed in the region between the bonding metal layers 210, thereby forming a host substrate ( 300) is very easy to cut. In particular, when the host substrate 300 is formed of a metal, since the cutting pattern 215 that is a through hole is not formed in the existing host substrate, there are many difficulties in cutting it. However, in the present invention, only the area between the through holes is cut. There is this.

As described above, a separate host substrate may be manufactured and then pressed to support the patterned semiconductor layer when the growth substrate is removed, as well as to connect the patterned semiconductor layers through a predetermined plating process on the semiconductor layer. A metal plating layer may be formed to support the patterned semiconductor layer.

5 to 10 are views for explaining the manufacturing method of the light emitting device according to the present invention. 5A to 10A are cross-sectional views and FIGS. 5B to 10B are plan views.

5A and 5B, the N-type semiconductor layer 120, the active layer 130, and the P-type semiconductor layer 140 are sequentially formed on the growth substrate 110. A portion of the P-type semiconductor layer 140, the active layer 130, and the N-type semiconductor layer 140 is removed through the patterning process.

As the substrate 110, at least one of Al 2 O 3 , SiC, ZnO, Si, GaAs, GaP, LiAl 2 O 3 , BN, AlN, and GaN is used. In this embodiment, a sapphire substrate is used. In the present exemplary embodiment, a buffer layer (not shown) may be formed on the substrate 110 as a buffer for forming the N-type semiconductor layer 120.

The N-type semiconductor layer 120 preferably uses a gallium nitride (GaN) film in which N-type impurities are implanted, and is not limited thereto. A material layer having various semiconductor properties may be used. In this embodiment, an N-type semiconductor layer 120 including an N-type Al x Ga 1 - x N (0 ≦ x ≦ 1) film is formed. In addition, the P-type semiconductor layer 140 also uses a gallium nitride film implanted with P-type impurities. In this embodiment, a P-type semiconductor layer 140 including a P-type Al x Ga 1 - x N (0 ≦ x ≦ 1) film is formed. In addition, an InGaN film may be used as the semiconductor layer film. In addition, the N-type semiconductor layer 120 and the P-type semiconductor layer 140 may be formed of a multilayer film. In the above, Si is used as the N-type impurity, Zn is used when InGaAlP is used as the P-type impurity, and Mg is used in the case of nitride.

As the active layer 130, a multilayer film in which a quantum well layer and a barrier layer are repeatedly formed on an N-type Al x Ga 1 - x N (0≤x≤1) film is used. As the barrier layer and the well layer, binary compounds GaN, InN, AlN, etc. may be used, and ternary compounds In x Ga 1 - x N (0 ≦ x1 ) and Al x Ga 1 - x N (0 and the like ≤x≤1), can be used 4 won compound Al x In y Ga 1 -x- y N (0≤x + y≤1). Of course, the N-type semiconductor layer 120 and the P-type semiconductor layer 140 may be formed by implanting predetermined impurities into the two- to four-membered compounds.

The above-described material layers can be deposited and grown in a variety of ways including metal organic chemical vapor deposition (MOCVD), molecular beam growth (MBE), hydride vapor phase epitaxy (HVPE), and the like. Is formed through the method.

Thereafter, a photoresist film is coated on the P-type semiconductor layer 140, and then a photolithography process is performed using a mask to form a photoresist pattern. An etching process using the photoresist pattern as an etching mask is performed to etch the P-type semiconductor layer 140, the active layer 130, and the N-type semiconductor layer 120 to pattern the semiconductor layers 120, 130, and 140. Isolate electrically. Thereafter, the photoresist pattern is removed through a predetermined strip process.

Next, metal layers 150 and 155 are formed on the patterned P-type semiconductor layer 140. In this embodiment, the metal layers 150 and 155 are formed in multiple layers. The transparent electrode layer 150 is formed on the P-type semiconductor layer 140, and a metal film 155 for bonding is formed thereon. The metal layers 150 and 155 may be formed in the entire region of the upper portion of the P-type semiconductor layer 140 or may be formed in a partial region. The metal layers 150 and 155 may be transparent and use layers having ohmic characteristics. It is preferable to include at least one of nickel, zinc, silver, gallium, ruthenium, platinum, and iridium as a base material constituting the metal layers 150 and 155.

Of course, the present invention is not limited thereto, and the metal layers 150 and 155 are formed on the P-type semiconductor layer 140, and then the photoresist pattern is formed on the metal layers 150 and 155, followed by an etching process using the same. 150 and 155, the P-type semiconductor layer 140, the active layer 130, and the N-type semiconductor layer 120 are removed. In addition, a portion of the growth substrate 110 may be etched together during the etching.

6A and 6B, regions in which the P-type semiconductor layer 140, the active layer 130, and the N-type semiconductor layer 120 are removed are filled with a predetermined barrier layer 160. In this case, the metal layers 150 and 155 formed on the P-type semiconductor layer 140 are exposed.

To this end, a barrier layer 160 having a thickness sufficient to fill a region between the patterned metal layers 150 and 155, the P-type semiconductor layer 140, the active layer 130, and the N-type semiconductor layer 120 is formed on the entire structure. Next, the barrier layer 160 formed on the metal layers 150 and 155 is removed to fill the barrier layer 160 with the material layer removed therefrom. In this case, the barrier layer 160 may be formed of a material including an oxide film, a nitride film, and a photoresist film, but may be formed of a material having a large etching difference with the P-type semiconductor layer 140, the active layer 130, and the N-type semiconductor layer 120. It is desirable to. This facilitates the removal through subsequent processes.

In the present embodiment, the barrier layer 160 is formed by applying a photoresist film to a region between the metal layers 150 and 155, the P-type semiconductor layer 140, the active layer 130, and the N-type semiconductor layer 120 patterned using the photoresist film. Form.

Referring to FIGS. 7A, 7B, 8A, and 8B, a first metal plating layer 180 having at least one through hole 185 formed in a part of the barrier layer 160 to be used as a cutting pattern is formed on the entire structure. .

To this end, first, the first seed layer 170 is formed in a region except a part of the barrier layer 160. In order to form the first seed layer 170, a predetermined mask pattern for shielding a part of the barrier layer 160 is formed on the entire structure, and then the first seed layer 170 is formed. In this case, the shape of the through hole 185 may be variously changed according to the mask pattern.

Thereafter, when the metal plating process is performed, the first metal plating layer 180 is formed on the region where the first seed layer 170 is formed. The metal plating process may perform a variety of plating processes, including electroplating, molten metal immersion plating, dissolution spray plating, deposition plating, cathode spray plating and the like. In the present embodiment, the first metal plating layer 180 is formed by electroplating. The first metal plating layer 180 is formed to a target thickness through one electroplating, or a plurality of electroplating processes are repeated to form a target thickness. The first metal plating layer 180 is formed to a thickness of 0.001 um or more. That is, it is formed to a thickness of 0.001 to 1000um. In addition, at least one of gold, silver, copper, tungsten, nickel, platinum, zinc, aluminum, molybdenum, silicon, germanium, titanium, gallium, indium, tin, and lead may be used as the first metal plating layer 180. .

As described above, when the lower growth substrate 110 is removed by forming the first metal plating layer 180, the patterned plurality of metal layers 150 and 155, the P-type semiconductor layer 140, the active layer 130, and the N-type are formed. It serves to support the semiconductor layer 120. In addition, it is formed on the P-type semiconductor layer 140 may not only serve to apply external power to the semiconductor layer, but also may emit heat emitted from the semiconductor layer to the outside. In addition, the present invention may facilitate the cutting of the first metal plating layer 180 because the first metal plating layer 180 formed in the region between the metal layers 150 and 155 has a predetermined through hole 185. Therefore, after removing the growth substrate 110, problems occurring when forming individual devices may be reduced.

The shape of the through hole 185 is a plurality of quadrangular shapes arranged in the cutting plane direction on the top of the barrier layer 160, that is, the region between the metal layers 150 and 155, as shown in FIGS. 7 and 8. Is formed. Of course, it is not limited to this, various shapes are possible for the convenience of cutting. That is, when viewed in plan, various shapes including a polygonal shape, a circular shape, an elliptic shape, a linear shape, a mesh shape, and the like are possible.

In this case, if the diameter of the through hole 185 is too large, a problem arises in that the lower semiconductor layers 120, 130, and 140 cannot be supported. In the present embodiment, when the area between the metal layers 150 and 155 is 1, the ratio of the first metal plating layer 180 that connects and supports the metal layers is 0.1 to 0.95. Preferably from 0.3 to 0.85. More preferably, it is 0.4-0.8.

9A and 9B, a second metal plating layer 190 is formed on the first metal plating layer 180 in the upper regions of the metal layers 150 and 155. To this end, a second seed layer (not shown) is formed on the first metal plating layer 180 in the upper regions of the metal layers 150 and 155, and then the second metal is formed in the region where the second seed layer is formed through an electroplating process. The plating layer 190 is formed.

Referring to FIG. 10, the growth substrate 110 under the N-type semiconductor layer 120 is removed and then formed in a region between the patterned P-type semiconductor layer 140, the active layer 130, and the N-type semiconductor layer 120. The barrier layer 160 is removed. Thereafter, the first metal plating layer 180 is processed to manufacture an independent light emitting device.

Here, the growth substrate 110 is removed through a laser lift-off process, and the barrier layer 160 is removed through wet etching. Thereafter, the first metal plating layer 180 of the through hole region of the first metal plating layer 180 is cut to manufacture individual light emitting devices. Through this, cutting of the first metal plating layer 180 may be facilitated. The cutting pattern, that is, the first metal plating layer 180 in the area between the through holes 185 may be easily cut because of its width.

110: growth substrate 120: N-type semiconductor layer
130: active layer 140: P-type semiconductor layer
150, 155: metal layer 160: barrier layer
170: seed layer 180, 190: metal plating layer
185: through hole 200: conductive plate
210: bonding metal layer 215: cutting pattern
300: host board

Claims (7)

  1. a semiconductor layer comprising an n-type nitride semiconductor layer, an active layer and a p-type nitride semiconductor layer;
    A transparent electrode layer provided on the p-type nitride semiconductor layer of the semiconductor layer;
    A bonding metal layer provided on the transparent electrode layer and including at least one of nickel, zinc, silver, gallium, ruthenium, platinum, or iridium; And
    And a host substrate provided on the bonding metal layer, wherein a layer including at least one of tungsten, nickel, molybdenum, indium, or tin is stacked in at least two layers.
  2. The light emitting device of claim 1, wherein at least two layers of the host substrate include a first metal plating layer and a second metal plating layer.
  3. The light emitting device of claim 2, wherein the second metal plating layer is provided on the first metal plating layer, and the width of the second metal plating layer is smaller than the width of the first metal plating layer.
  4. The light emitting device of claim 2, wherein the first metal plating layer is provided on the bonding metal layer.
  5. delete
  6. delete
  7. delete
KR1020100045658A 2010-05-14 2010-05-14 Luminescence device KR101330250B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020100045658A KR101330250B1 (en) 2010-05-14 2010-05-14 Luminescence device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020100045658A KR101330250B1 (en) 2010-05-14 2010-05-14 Luminescence device

Publications (2)

Publication Number Publication Date
KR20100057004A KR20100057004A (en) 2010-05-28
KR101330250B1 true KR101330250B1 (en) 2013-11-15

Family

ID=42280905

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020100045658A KR101330250B1 (en) 2010-05-14 2010-05-14 Luminescence device

Country Status (1)

Country Link
KR (1) KR101330250B1 (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003088320A2 (en) 2002-04-09 2003-10-23 Oriol, Inc. A method of fabricating vertical devices using a metal support film
WO2003088318A2 (en) 2002-04-09 2003-10-23 Oriol, Inc. Method of fabricating vertical structure leds

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003088320A2 (en) 2002-04-09 2003-10-23 Oriol, Inc. A method of fabricating vertical devices using a metal support film
WO2003088318A2 (en) 2002-04-09 2003-10-23 Oriol, Inc. Method of fabricating vertical structure leds

Also Published As

Publication number Publication date
KR20100057004A (en) 2010-05-28

Similar Documents

Publication Publication Date Title
US9660163B2 (en) Semiconductor light-emitting device and method of manufacturing the same
US8794501B2 (en) Method of transferring a light emitting diode
US7872276B2 (en) Vertical gallium nitride-based light emitting diode and method of manufacturing the same
JP5855422B2 (en) Light emitting device and manufacturing method thereof
KR100714589B1 (en) Method for Manufacturing Vertical Structure Light Emitting Diode
JP5347200B2 (en) Semiconductor light emitting device
US8263985B2 (en) Semiconductor light emitting device having one or more recesses on a layer
JP2005108863A (en) Vertical gallium nitride light emitting diode and its manufacturing method
JP2006086489A (en) Nitride semiconductor light emitting device having electrostatic discharge protection capability
JP5165276B2 (en) Vertical structure gallium nitride based light-emitting diode device and method of manufacturing the same
KR100856089B1 (en) Vertically structured GaN type Light Emitting Diode device And Manufacturing Method thereof
KR101166922B1 (en) Method of manufacturing light emitting diode
JP2007096300A (en) Gallium nitride based semiconductor light emitting device and method of manufacturing same
JP4999696B2 (en) GaN-based compound semiconductor light emitting device and manufacturing method thereof
KR101154758B1 (en) Semiconductor light emitting device and LED package having the same
JP5237570B2 (en) Vertical light emitting device manufacturing method
US8242530B2 (en) Light emitting device and method for fabricating the same
US8987776B2 (en) Light-emitting device
EP2270880A2 (en) Semiconductor light emitting device
KR101106148B1 (en) Luminous device
EP2290707B1 (en) Semiconductor light-emitting device
KR100890467B1 (en) METHOD FOR PRODUCING THIN GaN LIGHT EMITTING DIODE DEVICE
KR101064053B1 (en) Light emitting device and manufacturing method
US8384100B2 (en) InGaAIN light-emitting device and manufacturing method thereof
US20090315069A1 (en) Thin gallium nitride light emitting diode device

Legal Events

Date Code Title Description
A107 Divisional application of patent
A201 Request for examination
E902 Notification of reason for refusal
E90F Notification of reason for final refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20160907

Year of fee payment: 4

FPAY Annual fee payment

Payment date: 20170911

Year of fee payment: 5