KR101324669B1 - Memory device and setting method of power of the same - Google Patents

Abstract

A memory device and a voltage setting method of the memory device are disclosed. In an embodiment, a memory device may include a memory cell array including memory cells that store data in a latch; And a first voltage generator, a second voltage generator, and a third voltage for generating a first voltage, a second voltage, and a third voltage applied to the memory cell array, respectively, to test the noise margin of the memory cells in a test mode. And a test voltage setting unit configured to include a generator and positioned inside the memory device.

Description

Memory device and setting method of power of the same}

 The present invention relates to a memory device and a voltage setting method of the memory device, and more particularly, a memory device and a voltage setting method of a memory device capable of efficiently testing a noise margin of a memory cell or ensuring a sufficient noise margin of the memory cell. It is about.

In order to correctly write data into a memory cell or to accurately read data stored in the memory cell, the memory cell must be able to overcome noise due to charges flowing into the memory cell. However, as the degree of integration of memory devices increases, more memory cells do not have sufficient noise margins. Memory cells that do not have sufficient noise margin must be processed to fail to maintain the reliability of the memory device, but there is a problem in that a test for detecting memory cells that do not have noise margin takes time and cost.

SUMMARY OF THE INVENTION The present invention has been made in an effort to efficiently test a noise margin of a memory cell or to provide a memory device and a voltage setting method of the memory device capable of sufficiently securing a noise margin of the memory cell.

According to another aspect of the present invention, there is provided a memory device including a memory cell array including memory cells for storing data in a latch; And a first voltage generator, a second voltage generator, and a third voltage for generating a first voltage, a second voltage, and a third voltage applied to the memory cell array, respectively, to test the noise margin of the memory cells in a test mode. And a test voltage setting unit configured to include a generator and positioned inside the memory device.

According to another aspect of the present invention, there is provided a memory device including a memory cell array including memory cells for storing data in a latch; And a common voltage generator configured to generate a first voltage and a second voltage applied to the memory cell array as common voltages having the same voltage level, respectively, to test noise margins of the memory cells in a test mode. And an independent voltage generator configured to generate an applied third voltage as an independent voltage having a voltage level different from that of the first voltage and the second voltage, and having a test voltage setting unit located inside the memory device.

According to another aspect of the present invention, there is provided a memory device including a memory cell array including memory cells for storing data in a latch; And in response to a mode selection signal, generate a first voltage, a second voltage, and a third voltage applied to the memory cell array as test voltages for testing noise margins of the memory cells in a test mode, respectively, or in a normal mode. A first voltage generator, a second voltage generator, and a third voltage generator configured to generate an operating voltage for writing and reading data into the memory cells, the test voltage setting unit being disposed inside the memory device. do.

According to the memory device and the voltage setting method of the memory device according to an embodiment of the present invention, when testing the noise margin of the memory cell of the memory device, it is possible to easily change the test environment while improving the reliability of the test. In addition, according to the memory device and the voltage setting method of the memory device according to an embodiment of the present invention, it is possible to provide the same voltage level to different memory chips. Furthermore, according to the memory device and the voltage setting method of the memory device according to an embodiment of the present invention, there is an advantage that the optimized voltage level can be set for each operation of the memory device.

BRIEF DESCRIPTION OF THE DRAWINGS A brief description of each drawing is provided to more fully understand the drawings recited in the description of the invention.
1 is a block diagram schematically illustrating a memory device according to an exemplary embodiment of the present invention.
FIG. 2 is a diagram illustrating an example of a memory cell and a precharge unit included in the memory cell array of FIG. 1.
3 is a diagram illustrating an example in which a test voltage is applied to a pad on a wafer.
4 is a diagram illustrating an example of a reference voltage generator for generating a reference voltage applied to the voltage generators of FIG. 1.
5 and 7 are graphs showing examples of voltage levels of the reference voltage of FIG. 4 that may occur when an active voltage divider of the reference voltage generator of FIG. 4 is used or not.
6 is a diagram illustrating an example of a reference voltage divider included in the voltage generators of FIG. 1.
8 to 12 are diagrams schematically illustrating a memory device according to another exemplary embodiment of the present invention.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Embodiments of the present invention are provided to more fully describe the present invention to those skilled in the art, and the following embodiments may be modified in various other forms, The present invention is not limited to the following embodiments. Rather, these embodiments are provided so that this disclosure will be more thorough and complete, and will fully convey the concept of the invention to those skilled in the art.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an," and "the" include plural forms unless the context clearly dictates otherwise. Also, " comprise "and / or" comprising "when used herein should be interpreted as specifying the presence of stated shapes, numbers, steps, operations, elements, elements, and / And does not preclude the presence or addition of one or more other features, integers, operations, elements, elements, and / or groups. As used herein, the term "and / or" includes any and all combinations of one or more of the listed items.

Although the terms first, second, etc. are used herein to describe various elements, regions and / or regions, it should be understood that these elements, components, regions, layers and / Do. These terms are not intended to be in any particular order, up or down, or top-down, and are used only to distinguish one member, region or region from another member, region or region. Thus, the first member, region or region described below may refer to a second member, region or region without departing from the teachings of the present invention.

Hereinafter, embodiments of the present invention will be described with reference to the drawings schematically showing embodiments of the present invention. In the figures, for example, variations in the shape shown may be expected, depending on manufacturing techniques and / or tolerances. Accordingly, embodiments of the present invention should not be construed as limited to any particular shape of the regions illustrated herein, including, for example, variations in shape resulting from manufacturing.

1 is a diagram illustrating a memory device according to an exemplary embodiment of the present invention.

Referring to FIG. 1, a memory device MDEV according to an embodiment of the present invention includes a memory cell array MCA and a test voltage setting unit TVSU. The memory cell array MCA includes memory cells in which data is stored. The test voltage setting unit TVSU sets a test voltage applied to the memory cell array MCA in the test mode.

When the memory device MDEV according to the embodiment of the present invention is an SRAM, the memory cell array MCA may include a word line WL, a bit line BL, and a complementary bit line BLB, as shown in FIG. 2. ) And a precharge unit PREU precharges the bit line and the complementary bit line BLB. FIG. 2 particularly shows a 6T SRAM. The memory cell MC of the 6T SRAM has one end connected to a latch part LAT, in which data is stored, and a bit line BL and a complementary bit line BLB, respectively, and the other end connected to a latch part LAT. The gate includes pass transistors PT connected to the word line. The precharge unit PREU applies the precharge voltage VINTP to the bit line BL and the complementary bit line BLB in response to the precharge signal PREB.

2 illustrates only a precharge unit connected to one memory cell, a pair of bit lines BL, and a complementary bit line BLB, for convenience of illustration, but according to an embodiment of the present invention, The MCA may include a plurality of memory cells and a precharge unit.

For the memory cell MC as shown in FIG. 2, the test voltage setting unit TVSU adjusts data by adjusting at least one voltage among the first voltage V1, the second voltage V2, and the third voltage V3. The noise margin of the memory cell MC in the write operation to write, the read operation to read data from the memory cell MC as shown in FIG. 2, and the precharge operation are tested. The first voltage V1 of the present invention is a precharge voltage VINTP for precharging the bit line BL, and the second voltage V2 is a cell voltage VINTC for supplying a voltage of the memory cell MC. The third voltage V3 may correspond to the word line voltage VINTW applied to the word line WL. The precharge voltage VINTP, the cell voltage VINTC, and the word line voltage VINTW in the normal mode performing the normal operation other than the test mode are the first voltage V1 and the second voltage V2 in the test mode. And the voltage level may be different from the third voltage V3. This is because the test voltages of the first voltage V1, the second voltage V2, and the third voltage V3 are changed to perform the test to check the noise margin of the memory cell under various conditions.

The test voltage setting unit TVSU according to an embodiment of the present invention may include a first voltage generator VGEN1 for generating a first voltage V1, a second voltage generator VGEN2 for generating a second voltage V2, and a first voltage generator. And a third voltage generator VGEN3 for generating three voltages V3. However, the present invention is not limited thereto. The precharge voltage VINTP, the cell voltage VINTC, and the type or level of the voltage applied to the memory cell array MCA to perform an operation such as writing, reading, or precharging the memory cell MC are described above. If the word line voltage VINTW is further present, the test voltage setting unit TVSU according to the embodiment of the present invention may further include an additional voltage generator to further apply the additional voltage to the memory cell array MCA.

Each of the first voltage generator VGEN1, the second voltage generator VGEN2, and the third voltage generator VGEN3 included in the test voltage setting unit TVSU may change activation in response to a corresponding test enable signal. have. For example, the first voltage generator VGEN1 is activated in response to the first test enable signal TEN1, and the second voltage generator VGEN2 is activated in response to the second test enable signal TEN2. The third voltage generator VGEN3 may be activated in response to the third test enable signal TEN3. In this case, the first test enable signal TEN1, the second test enable signal TEN2, and the third test enable signal TEN3 may be activated together or separately in the test mode.

The first voltage generator VGEN1, the second voltage generator VGEN2, and the third voltage generator VGEN3 are respectively based on the reference voltage VINT_REF and the first voltage V1, the second voltage V2, and the third voltage generator VGEN3. The voltage level of the corresponding voltage among the voltages V3 may be set. A detailed description of the first voltage generator VGEN1, the second voltage generator VGEN2, and the third voltage generator VGEN3 according to the embodiment of the present invention will be described later.

As such, the memory device MDEV according to the embodiment of the present invention may set voltage levels of the first voltage V1, the second voltage V2, and the third voltage V3 in the test mode, respectively. As illustrated in FIG. 3, a memory device MDEV includes a wafer in which a precharge voltage VINTP and a cell voltage VINTC are mounted with a memory device (or a memory chip MCIP) to test a noise margin. The on-resistance of the pass transistor PT of FIG. 2 and the precharge voltage of the bit line pair BL and BLB, which may be generated when applied to the pads VINTP_PAD and VINTC_PAD provided in the WAF, VINTP) may not cause a problem as it changes simultaneously. When the on resistance of the pass transistor PT and the precharge voltage VINTP of the bit line pairs BL and BLB are simultaneously changed, it is difficult to accurately evaluate the level of the noise margin. In addition, the test voltage setting unit TVSU according to an embodiment of the present invention may generate the first voltage V1, the second voltage V2, and the third voltage V3 in the memory device MDEV. Since it is generated by the test voltage setting unit TVSU, the test is not limited to being performed only in the wafer state as shown in FIG. 3, and the test may be performed even in the package state. In the wafer state, the test can be performed by applying a test voltage to the pad by adding a pad for the test. On the other hand, when the memory device is finally shipped in a packaged state, it may be difficult to detect an error that may occur during the packaging process because the pad cannot be connected to the package pin. Since the test voltage setting unit is located inside the device, the test in a package state can be easily performed.

Referring back to FIG. 1, as described above, the test voltage setting unit TVSU may generate a corresponding test voltage based on the reference voltage VINT_REF. In this case, the memory device MDEV according to the embodiment of the present invention may further include a reference voltage generator VRG as shown in FIG. 4 to generate the reference voltage VINT_REF.

Referring to FIG. 4, the reference voltage generator VRG according to an embodiment of the present invention has a reference generator RG and a die-to-die variation with less variation in process, voltage and temperature (PVT). It can be implemented as a negative feedback circuit including a trimming unit (TRMU) to reduce the. The reference voltage generator VRG further includes an active voltage divider EVD to prevent the influence of the variation (voltage level or current amount) caused by the reference generator RG from being reflected in the reference voltage VINT_REF, and The voltage VINT_REF may be generated to be proportional to the external power supply voltage VDD as shown in FIG. 5. The external power supply voltage VDD is a power supplied to a chip (for example, MCIP of FIG. 3), and the reference generator RG may generate an initial reference voltage VREF0 based on the external power supply voltage VDD. .

The reference voltage generator VRG will be described in more detail. The active voltage divider EVD is respectively gated by an NMOS transistor NT and a PMOS transistor PT gated by a test enable signal TEN indicating a test mode and an inversion signal / TEN of the test enable signal TEN. It is provided. In addition, the active voltage divider EVD further includes resistors R, which are connected between the output of the reference generator RG and the NMOS transistor NT and the PMOS transistor PT, respectively.

Thus, in the test mode, i.e., when the test enable signal TEN is activated to logic high, the voltage level of the initial reference voltage VREF0 is determined by the output of the resistor divider (resistors R).

In order to apply the same voltage level (the same reference voltage) to the different memory chips (memory devices), the variable resistors included in the trimming unit TRMU take into consideration the PVT variation of each memory chip at the initial reference voltage VREF0. The size is set. Accordingly, the reference voltage VINT_REF according to the embodiment of the present invention may be generated in the same manner for memory devices (memory chips) of different environments. That is, the die-to-die variation of the reference voltage between the memory devices according to the embodiment of the present invention can be reduced.

6 is a diagram illustrating an example of a reference voltage divider included in the voltage generators of FIG. 1.

1 and 6, in accordance with an embodiment of the present invention, the first voltage generator VGEN1, the second voltage generator VGEN2, and the third voltage generator VGEN3 may be a reference voltage VINT_REF and a ground, respectively. Between the voltages VSS, a plurality of resistors may have a voltage divider VDIV including a resistor string connected in series. For example, if the voltage divider VDIV is provided with a resistor string to which n resistors are connected, the first voltage V1 may be set to be equal to or higher than the node voltage between the i th resistor and the i + 1 th resistor. The second voltage V2 may be set above the node voltage between the jth resistor and the j + 1th resistor, and the third voltage V3 may be set above the node voltage between the kth resistor and the k + 1th resistor. Can be. At this time, i, j and k are natural numbers of n or less.

According to the above example, the first voltage V1, the second voltage V2, and the third voltage V3 according to the embodiment of the present invention may be generated at the voltage level belonging to the hatched portion of FIG. 7. The first voltage generator VGEN1, the second voltage generator VGEN2, and the third voltage generator VGEN3 according to the embodiment of the present invention each use different voltages by using reference voltages VINT_REF having different voltage levels. By generating the first voltage V1, the second voltage V2, and the third voltage V3 of the level, it is possible to accurately determine the level of the noise margin. Furthermore, the memory device MDEV according to the embodiment of the present invention changes the voltage level of the reference voltage VINT_REF by using the voltage divider VDIV implemented as a resistor string as shown in FIG. You can keep the difference constant.

8 is a diagram illustrating a memory device MDEV according to another exemplary embodiment of the present invention, in which voltage generators are connected to each other through a power switch. For example, the first voltage generator VGEN1 and the third voltage generator VGEN3 are connected to the first power switch PS1, and the third voltage generator VGEN3 and the second voltage generator VGEN2 are the third power. The third voltage generator VGEN3 and the first voltage generator VGEN1 may be connected to the second power switch PS2.

In this case, the power switches PS1 to PS3 may be provided as PMOS transistors that are gated in response to the corresponding test enable signal TEN among the test enable signals. For example, the first power switch PS1 is gated by the first test enable signal TEN1, the second power switch PS2 is gated by the second test enable signal TEN2, and the third The power switch PS3 is gated by the third test enable signal TEN3.

The power switches may be distributed around the memory cell array so that each of the power switches according to the embodiment of the present invention can perform the switching operation stably. In addition, in the normal mode other than the test mode, for example, when all of the test enable signals TEN1 to TEN3 are deactivated, the first voltage V1, the second voltage V2, and the third voltage V3. ) May be connected to each other to maintain the same voltage level. In the memory device of FIG. 1 or FIG. 8 described above, each independent voltage may be set to allow the memory device to operate under optimum operating conditions in consideration of yield, speed, and current consumption. However, the above description has been made only for the memory device in which each voltage applied to the memory cell array is independently set. However, the present invention is not limited thereto.

As shown in FIG. 9, according to the memory device MDEV according to another embodiment of the present invention, some voltages may be integrated by a common voltage generator, and only some voltages may be separated. 9 illustrates a common voltage generator VGENC, in which the test voltage setting unit TVSU generates the first voltage V1 and the second voltage V2 of FIG. 1 to a common voltage Vcom, that is, the same voltage level. The example with which is provided is shown. The test voltage setting unit TVSU of FIG. 9 may also generate the third voltage V3 of FIG. 1 as an independent voltage Vin at a voltage level different from the first voltage V1 and the second voltage V2. And a voltage generator VGENI.

In this case, the common voltage Vcom may be the precharge voltage VINTP and the cell voltage VINTC of FIG. 2, and the independent voltage Vind may be the wordline voltage VINTW of FIG. 2. The voltage levels of the common voltage Vcom and the independent voltage Vind are similar to those of the voltage levels of FIG. 1 or 8, so that the memory device may operate at an optimum operating condition in consideration of yield, speed, and current consumption. Can be set.

In the above, only the example in which the test voltage setting unit generates each voltage is described. However, the present invention is not limited thereto. As shown in FIG. 10, each voltage applied to the memory cell array to test the noise margin of the memory cell may be applied from the outside through the pad.

Referring to FIG. 10, the test voltage setting unit TVSU together with the first voltage generator VGEN1, the second voltage generator VGEN2, and the third voltage generator VGEN3 may include a first pad PAD1 and a second pad. And a third pad PAD3. The first pad PAD1 transfers the first voltage V1 applied from the outside to the memory cell array MCA. The second pad PAD2 transfers the second voltage V2 applied from the outside to the memory cell array MCA. The third pad PAD3 transfers the third voltage V3 applied from the outside to the memory cell array MCA.

The first voltage generator VGEN1, the second voltage generator VGEN2, and the third voltage generator VGEN3 of FIG. 10 are formed by the first pad PAD1, the second pad PAD2, and the third pad PAD3. When the first voltage V1, the second voltage V2, and the third voltage V3 are applied to the memory cell array MCA, the voltage generation enable signals EN_G1, EN_G2, and EN_G3 are applied to avoid collisions. Disable it. That is, the test voltage setting unit TVSU of FIG. 10 activates the voltage generation enable signals EN_G1, EN_G2, and EN_G3 when voltages are applied to the memory cell arrays MCA by the respective voltage generators. Are operated, and voltage generation enable signals EN_G1, EN_G2, and EN_G3 are applied when the voltages are applied to the memory cell arrays MCA by the pads PAD1, PAD2, and PAD3. Deactivate the voltage generators VGEN1, VGEN2, and VGEN3.

FIG. 11 is a diagram illustrating a part of the test voltage setting unit of FIG. 10 in more detail.

Referring to FIG. 11, one of the node voltages Vn−x + 1 to Vn of the voltage divider of FIG. 6 is selected through a mux. The voltage output from the mux is applied to the driver. At this time, the driver is activated when the voltage generation enable signals EN_G1, EN_G2, and EN_G3 are activated, and when the voltage is to be applied by the pads PAD1, PAD2, and PAD3, the voltage generation enable signals ( As EN_G1, EN_G2, EN_G3) are deactivated, they are turned off. 11 illustrates an example in which the power switches PS1 to PS3 of FIG. 8 are connected to both ends of the voltage generators, respectively.

In the above, only the voltage setting for the test in the test mode has been described. However, the present invention is not limited thereto. Referring to the test voltage setting unit TVSU of FIG. 12 according to another embodiment of the present invention, the voltage in the normal mode as well as the test mode may be set in response to the mode signal XMOD applied to the mux. For example, the first voltage V1, the second voltage V2, and the third voltage V3, which are test voltages in the test mode, may be set in response to the mode signal XMOD of the first logic level. . Alternatively, the first voltage V1, the second voltage V2, and the third voltage V3, which are test voltages in the normal mode, may be set in response to the mode signal XMOD of the second logic level. In the normal mode, the first voltage V1, the second voltage V2, and the third voltage V3 may be used as the precharge voltage VINTP, the cell voltage VINTC, and the word line voltage VINTW of FIG. 2. have.

In this case, the first voltage V1, the second voltage V2, and the third voltage V3 set in the normal mode may be fixed through fuse cutting. As described above, the memory device according to the embodiment of the present invention can set the optimized voltage in the normal operation as well as the test operation.

As described above, optimal embodiments have been disclosed in the drawings and the specification. Although specific terms are employed herein, they are used for purposes of describing the present invention only and are not used to limit the scope of the present invention. Therefore, those skilled in the art will appreciate that various modifications and equivalent embodiments are possible without departing from the scope of the present invention. Accordingly, the true scope of the present invention should be determined by the technical idea of the appended claims.

Claims (15)

In the memory device,
A memory cell array including memory cells for storing data in a latch; And
A first voltage generator, a second voltage generator, and a third voltage generator for generating a first voltage, a second voltage, and a third voltage applied to the memory cell array, respectively, to test the noise margin of the memory cells in a test mode. And a test voltage setting unit positioned inside the memory device. The method according to claim 1,
The first voltage corresponds to a precharge voltage applied to the memory cell array, the second voltage corresponds to a cell voltage applied to the memory cell array, and the first voltage is a word applied to the memory cell array. And a memory device corresponding to the line voltage. The method according to claim 1,
The first voltage generator, the second voltage generator and the third voltage generator each include a voltage divider for dividing the reference voltage by the node voltage of each node of the resistance string connected in series between the reference voltage and the ground voltage. And a memory device. The method of claim 3,
The first voltage is generated at a voltage level equal to or greater than the node voltage of the first node of the resistance string, the second voltage is generated at a voltage level equal to or greater than the node voltage of the second node of the resistance string, and the third voltage is equal to the And at a voltage level equal to or greater than the node voltage of the third node of the resistor string. The method of claim 3, wherein the test voltage setting unit,
To generate the first voltage, the second voltage and the third voltage from the reference voltage, one of each node voltage of the resistance string corresponds to one of the first voltage, the second voltage and the third voltage. The memory device further comprises a mux to select the voltage. The memory device of claim 3, wherein the memory device comprises:
And a reference voltage generator configured to generate the reference voltage. The method of claim 5, wherein the reference voltage generator,
And a trimming unit to equally adjust a voltage level of the reference voltage used in other memory devices having the same structure as the memory device. The memory device of claim 1, wherein the memory device comprises:
A first power switch, a second power switch, and a third power source connected to both ends of the first voltage generator, the second voltage generator, and the third voltage generator and gated to a corresponding test enable signal; The memory device further comprises a switch. The method of claim 1, wherein the test voltage setting unit,
A first pad that receives the first voltage from the outside and applies it to the memory cell array, a second pad that receives the second voltage from the outside and applies it to the memory cell array, and receives the third voltage from the outside And a third pad applied to the memory cell array. 10. The method of claim 9,
The first voltage generator, the second voltage generator and the third voltage generator, respectively,
And deactivate when the first pad, the second pad, and the third pad are activated. The method according to claim 1,
The first voltage, the second voltage and the third voltage are each set differently. In the memory device,
A memory cell array including memory cells for storing data in a latch; And
A common voltage generator for generating a first voltage and a second voltage applied to the memory cell array as common voltages having the same voltage level, respectively, to test the noise margin of the memory cells in a test mode; And an independent voltage generator configured to generate a third voltage to be an independent voltage having a voltage level different from that of the first voltage and the second voltage, and including a test voltage setting unit located inside the memory device. Memory device. In the memory device,
A memory cell array including memory cells for storing data in a latch; And
In response to a mode selection signal, a first voltage, a second voltage, and a third voltage applied to the memory cell array are respectively generated as test voltages for testing noise margins of the memory cells in a test mode, or in a normal mode. A first voltage generator, a second voltage generator, and a third voltage generator configured to generate an operating voltage for writing and reading data into the memory cells, and including a test voltage setting unit disposed in the memory device. A memory device, characterized in that. The method of claim 13,
The first voltage in the normal mode is used as a precharge voltage applied to the memory cell array, the second voltage is used as a cell voltage applied to the memory cell array, and the first voltage is applied to the memory cell array. And a word line voltage applied thereto. The method of claim 13,
Wherein the first voltage, the second voltage, and the third voltage each have a fixed voltage level by fuse cutting.

Images