KR101318233B1 - A display device and a method for driving the same - Google Patents

Abstract

The present invention relates to a display device and a driving method thereof, which can increase the charging time of a pixel cell and to prevent a luminance difference between the pixel cells. The present invention relates to at least one first pixel cell group and at least one second pixel. A display unit including a cell group; A first data line connected to pixel cells in the first pixel cell group; A second data line connected to pixel cells in the second pixel cell group; A gate driver for simultaneously driving at least one pixel cell in the first pixel cell group and at least one pixel cell in the second pixel cell group; And receiving first and second gray voltage groups having different magnitudes, selecting a gray voltage from the first gray voltage group according to a data signal, and supplying the gray voltage to the first data line. And a data driver for selecting a gray voltage and supplying it to the second data line.

LCD, FSC, subframe, gradation voltage, luminance difference

Description

A display device and a method for driving the same}

1 is a view for explaining the driving of a conventional FSC type liquid crystal display device

2 illustrates a display device according to an exemplary embodiment of the present invention.

3 is a view for explaining a driving method for the portion A of FIG.

4A is a diagram illustrating a structure of a first pixel cell included in a first pixel cell group of FIG. 3.

4B illustrates a structure of a fourth pixel cell included in the second pixel cell group of FIG. 3.

4C is a diagram illustrating a structure of a seventh pixel cell included in the third pixel cell group of FIG. 3.

FIG. 5 is a cross-sectional view taken along line I-I of FIG. 4A

6A through 6C are diagrams for describing an operation of the pixel cell illustrated in FIG. 3.

7 is a diagram illustrating a data driver and first to third gray voltage generators supplying a gray voltage to the data driver.

8 is a diagram illustrating a circuit configuration of the first to third gray voltage generators of FIG. 7; FIG.

* Explanation of symbols on the main parts of the drawings

201: gate driver 202: data driver

203: timing controller 204: backlight unit

205: light source driver GL: data line

DL: Data line Gr: Pixel cell group

PXL: pixel cell 200: display unit

A: pixel cell array

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device, and more particularly, to a display device and a driving method thereof capable of increasing a charging time of a pixel cell.

Recently, various flat panel display devices that can reduce weight and volume, which are disadvantages of cathode ray tubes, have emerged. Such flat panel displays include a liquid crystal display, a field emission display, a plasma display panel, a light emitting display, and the like.

In general, a plurality of liquid crystal cells are disposed in a region defined by a plurality of data lines and a plurality of gate lines, and a thin film transistor (TFT), which is a switch element, is disposed in each liquid crystal cell. The formed TFT substrate and the color filter substrate on which the color filter is formed are maintained at regular intervals and include a liquid crystal layer formed therebetween.

However, since the liquid crystal display implements a color image by using light passing through the TFT substrate and the color filter substrate, color reproducibility is lowered due to the characteristics of the color filter.

In order to solve the low color reproducibility of the liquid crystal display device according to the related art, a liquid crystal display device having a field sequential color (hereinafter referred to as FSC) method has been proposed.

1 is a view for explaining the driving of a conventional FSC type liquid crystal display device.

In the FSC type liquid crystal display, as shown in FIG. 1, one frame is divided into three sub-frames, and the red light R and the green light G in each sub-frame. And blue light B additionally mixed to display a color image. For example, an FSC type liquid crystal display device which time-divides one frame into three subframes and drives the red light R in the first subframe, the green light G and the third in the second subframe The blue light B in the sub-frame is additively mixed at a constant ratio to display a color image.

To this end, the FSC type liquid crystal display does not require a color filter and includes a backlight unit for an FSC (not shown) which generates red light (R), green light (G), and blue light (B). The FSC backlight unit may include a red light source, a green light source, and a blue light source, and each light source may include a light emitting diode.

That is, the FSC type liquid crystal display device charges red data to the liquid crystal cell during the scan time of the gate line, turns on the red lamp after the response time of the liquid crystal, and displays red color for a time shorter than the ⅓ frame period. . After red is displayed, green and blue are displayed by writing green data and lighting of the green lamp, followed by writing of blue data and lighting of the blue lamp.

However, as the display device becomes larger and the number of gate lines increases, the driving time of each gate line becomes shorter. That is, the display device must drive all of the gate lines for a predetermined frame time. As the number of gate lines increases, each scan time of each gate line is inevitably shortened. Accordingly, the turn-on time of the thin film transistors connected to the respective gate lines is inevitably shortened.

In addition, when the scan time is shortened, it becomes difficult for each gate line to be sufficiently charged to the corresponding voltage. Conventionally, the charging problem is solved by setting the size of the thin film transistor to be large.

However, since the size of the thin film transistor is restricted by the design rule, the size of the thin film transistor cannot be increased indefinitely.

Therefore, the conventional FSC type liquid crystal display still has a problem due to the reduction of the scan time.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and the scan time of a thin film transistor can be increased by driving a plurality of pixel cells into pixel cell groups and providing data lines to each pixel cell group individually. The present invention provides a display device and a driving method thereof.

According to an aspect of the present invention, there is provided a display device including a display unit including at least one first pixel cell group and at least one second pixel cell group; A first data line connected to pixel cells in the first pixel cell group; A second data line connected to pixel cells in the second pixel cell group; A gate driver for simultaneously driving at least one pixel cell in the first pixel cell group and at least one pixel cell in the second pixel cell group; And receiving first and second gray voltage groups having different magnitudes, selecting a gray voltage from the first gray voltage group according to a data signal, and supplying the gray voltage to the first data line, from the second gray voltage group. And a data driver for selecting a gray voltage and supplying it to the second data line.

In addition, a driving method of a display device according to the present invention for achieving the above object, the display unit including at least one first pixel cell group and at least one second pixel cell group; A first data line connected to pixel cells in the first pixel cell group; A second data line connected to pixel cells in the second pixel cell group; A method of driving a display device, comprising: at least one pixel cell in the first pixel cell group and a gate driver for simultaneously driving at least one pixel cell in the second pixel cell group, wherein the gray level is obtained from a first gray voltage group. Selecting and supplying a voltage to the first data line; And selecting a gray voltage from a second gray voltage group having a different size from that of the first gray voltage group and supplying the gray voltage to the second data line.

Hereinafter, a display device according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

2 illustrates a display device according to an exemplary embodiment of the present invention.

The liquid crystal display according to the exemplary embodiment of the present invention includes a display unit 200 in which pixel cells PXL are formed in each region defined by data lines DL and gate lines GL, and the display unit 200. A backlight unit 204 for sequentially irradiating green, red, and blue light to the light; and a data driver for supplying data to the data lines DL of the display unit 200 by time-dividing one frame into a plurality of subframes. 202, a gate driver 201 for driving the gate lines GL of the display unit 200, and a timing controller for controlling the data driver 202, the gate driver 201, and the backlight unit 204. 203.

Herein, the components listed above will be described in more detail.

The timing controller 203 generates a data control signal DCS and a gate control signal GCS using horizontal / vertical synchronization signals Vsync and Hsync and a main clock MCLK. Here, the data control signal DCS includes a dot clock Dclk, a source start pulse SSP, a source shift clock SSC, a source output enable SOE, and a polarity. Control signal POL and the like. The gate control signal GCS includes a gate start pulse GSP, a gate shift clock GSC, a gate output enable GOE, and the like.

In addition, the timing controller 203 sequentially sequentially the red, green, and blue light sources 221, 222, and 223 for one frame using the horizontal / vertical synchronization signals Vsync and Hsync and the main clock MCLK supplied from the outside. A light source control signal LCS for driving the light source is generated and supplied to the backlight unit 204.

In addition, the timing controller 203 rearranges the source data RGB input from the outside in the order of green, red, and blue data so as to be suitable for the field sequential color (FSC) driving scheme, and one frame. The green, red, and blue data aligned for each subframe of S1 are sequentially supplied to the data driver 202.

The gate driver 201 may include a shift register that sequentially generates scan pulses in response to a gate start pulse GSP among the gate control signals GCS from the timing controller 203, and stores the voltage of the scan pulses in the pixel cell PXL. It is composed of a level shifter for shifting to a level suitable for driving. The gate driver 201 sequentially shifts the gate start pulse GSP supplied from the timing controller 203 according to the gate shift clock, and supplies scan pulses to the gate lines for each subframe of one frame. do. In this case, the gate driver 201 simultaneously drives at least two gate lines GL.

The data driver 202 samples the data supplied from the timing controller 203 according to the data control signal DCS from the timing controller 203, and then latches the sampled data by one line and gamma voltages of the latched data. The analog data is converted into analog data corresponding to and supplied to the data lines DL. Accordingly, the data driver 202 supplies red data to the data lines DL in the first subframe of one frame, and green data to the data lines DL in the second subframe. The blue data is supplied to the data lines DL in the subframe SF3.

The backlight unit 204 includes a red light source 221 for irradiating red light R to the display unit 200, a green light source 222 for irradiating green light G to the display unit 200, and a display unit. A blue light source 223 for irradiating blue light B to the 200 and a light source driver 205 for driving each of the red, green, and blue light sources 221, 222, and 223 are provided.

Each of the red, green, and blue light sources 221, 222, and 223 generates red light (R), green light (G), and red light (R) sequentially during one frame in response to a drive signal from the light source driver 205. The display unit 200 is irradiated. Each of the red, green, and blue light sources 221, 222, and 223 may be a fluorescent lamp or a light emitting diode.

The light source driver 205 sequentially drives each of the red, green, and blue light sources 221, 222, and 223 for one frame in response to the light source control signal LCS from the timing controller 203. The driver 205 drives the red light source 221 in the second half of the first subframe of one frame in response to the light source control signal LCS, and drives the green light source 222 in the second half of the second subframe. The blue light source 223 is driven in the second half of the three subframes.

Here, the display unit 200 will be described in more detail with reference to FIG. 3.

FIG. 3 is a diagram illustrating part A of FIG. 2 and specifically illustrates one pixel cell column of FIG. 2.

Here, since each pixel cell column A of the display unit 200 of the present invention has the same structure, only one pixel cell column A will be representatively described.

Meanwhile, for convenience of explanation, it is assumed that the pixel cell column A has nine pixel cells PXL. In addition, it is assumed that the first to third pixel cell groups Gr1 to Gr3 divide the nine pixel cells PXL. That is, each pixel cell group has three pixel cells PXL. In other words, the first pixel cell group Gr1 has first to third pixel cells PX1 to PXL3, and the second pixel cell group Gr2 has fourth to sixth pixel cells PXL4 to PXL6. And the third pixel cell group Gr3 has seventh to ninth pixel cells PXL7 to PXL9.

The first to ninth gate lines GL1 to GL9 are independently connected to the first to ninth pixel cells PXL1 to PXL9, respectively.

One such pixel cell column A has three data lines DL1 to DL3. That is, the number of pixel cell groups and the number of data lines included in each pixel cell column A are the same.

At this time, each pixel cell group Gr1 to Gr3 is connected to a different data line.

That is, the first data line DL1 may include pixel cells in the first pixel cell group Gr1, that is, the first pixel cell PXL1, the second pixel cell PXL2, and the third pixel cell PXL3. Is commonly connected to. The second data line DL2 is connected to the pixel cells in the second pixel cell group Gr2, that is, the fourth pixel cell PXL4, the fifth pixel cell PXL5, and the sixth pixel cell PXL6. Commonly connected. The third data line DL3 includes pixel cells in the third pixel cell group Gr3, that is, a seventh pixel cell PXL7, an eighth pixel cell PXL8, and a ninth pixel cell PXL9. Is commonly connected to.

Here, the gate lines GL1 to GL9 connected to the pixel cells PXL in the same pixel cell group are sequentially driven.

That is, the first to third scan pulses sequentially output to the first to third gate lines GL1 to GL3 connected to the first to third pixel cells PX1 to PXL3 in the first pixel cell group Gr1. It is driven in turn by receiving (SP1 to SP3). Accordingly, the first to third pixel cells PX1 to PXL3 are sequentially driven in the first direction.

The fourth to sixth scan pulses sequentially output to the fourth to sixth gate lines GL4 to GL6 connected to the fourth to sixth pixel cells PXL4 to PXL6 in the second pixel cell group Gr2. It is driven sequentially by receiving (SP4 to SP6). Accordingly, the fourth to sixth pixel cells PXL4 to PXL6 are sequentially driven in the first direction.

The seventh through ninth scan pulses sequentially output from the seventh through ninth gate lines GL7 through GL9 connected to the seventh through ninth pixel cells PXL7 through PXL9 in the third pixel cell group Gr3. It is driven sequentially by receiving (SP7 to SP9). Accordingly, the seventh to ninth pixel cells PXL7 to PXL9 are sequentially driven in the first direction.

In this case, the gate lines GL1 to GL9 connected to the corresponding pixel cells PXL1 to PXL9 between the pixel cell groups Gr1 to Gr3 are simultaneously driven.

That is, the first gate line GL1 connected to the first pixel cell PXL1, the fourth gate line GL4 connected to the fourth pixel cell PXL4, and the seventh pixel cell PXL7. The connected seventh gate line GL7 is driven at the same time by receiving the scan pulses SP1, SP4, and SP7 at the same timing, and is connected to the second pixel cell PXL2 and the fifth gate line GL7. The fifth gate line GL5 connected to the pixel cell PXL5 and the eighth gate line GL8 connected to the eighth pixel cell PXL8 receive scan pulses SP2, SP5, and SP8 at the same timing. A third gate line GL3 driven simultaneously and connected to the third pixel cell PXL3, a sixth gate line GL6 connected to the sixth pixel cell PXL6, and the ninth pixel cell PXL9. The ninth gate line GL9 connected to is supplied with scan pulses SP3, SP6, and SP9 at the same timing and simultaneously driven.

To this end, the first scan pulse SP1 supplied to the first gate line GL1, the fourth scan pulse SP4 supplied to the fourth gate line GL4, and the seventh gate line GL7. The seventh scan pulse SP7 supplied to the second output pulse is simultaneously output and the second scan pulse SP2 supplied to the second gate line GL2 and the fifth scan pulse SP5 supplied to the fifth gate line GL5. ) And the eighth scan pulse SP8 supplied to the eighth gate line GL8 are simultaneously output and the third scan pulse SP3 and the sixth gate line supplied to the third gate line GL3. The sixth scan pulse SP6 supplied to GL6 and the ninth scan pulse SP9 supplied to the ninth gate line GL9 are simultaneously output.

Herein, the structure of each pixel cell PXL will be described in detail.

4A is a diagram illustrating a structure of a first pixel cell included in the first pixel cell group of FIG. 3.

As illustrated in FIG. 4A, the first pixel cell PXL1 outputs a data signal from the first data line DL1 in response to the first scan pulse SP1 from the first gate line GL1. A thin film transistor TFT, a pixel electrode PE for receiving a data signal from the thin film transistor TFT, a common electrode (not shown) facing the pixel electrode PE, and the pixel electrode ( A liquid crystal layer (not shown) formed between the PE) and the common electrode.

The thin film transistor TFT is formed near the intersection of the first gate line GL1 and the first data line DL1. The thin film transistor TFT includes a gate electrode GE connected to the first gate line GL1, a semiconductor layer 401 formed on the gate electrode GE so as to overlap the gate electrode GE, and the A source electrode SE connected to the first data line DL1 and a drain electrode DE connected to the pixel electrode PE are included.

In particular, since the second and third data lines DL2 and DL3 cross the first pixel cell PXL1, the second and third data lines DL2 and DL3 overlap the pixel electrode PE of the first pixel cell PXL1. Accordingly, a capacitor is formed at a portion where the pixel electrode PE and the second data line DL2 overlap and a portion where the pixel electrode PE and the third data line DL3 overlap.

When the capacitor is formed, the data signal applied to the pixel electrode PE may fluctuate. Therefore, it is important to minimize the overlapping portion between the pixel electrode PE and the second and third data lines DL3. .

To this end, the pixel electrode PE connects the three transparent electrodes TE1, TE2 and TE3 and two connection electrodes BE1 and BE2 electrically connecting the transparent electrodes TE1, TE2 and TE3. Have

Here, the first transparent electrode TE1 is positioned between the first data line DL1 and the second data line DL2, and the second transparent electrode TE2 is the second data line DL2 and the third data. The third transparent electrode TE3 is disposed between the lines DL3 and is disposed in the third data line DL3 and the first data line DL1 (the pixel cell PXL adjacent to the first pixel cell PXL1). Positioned between the first data line DL1). The drain electrode DE of the TFT may include the first transparent electrode TE1, the second transparent electrode TE2, the third transparent electrode TE3, the first connection electrode BE1, and the first electrode. The second connection electrode BE2 may be connected to any one, but is preferably connected to the first transparent electrode TE1 on the position of the thin film transistor TFT.

The first connection electrode BE1 is electrically connected between the first transparent electrode TE1 and the second transparent electrode TE2, and the second connection electrode BE2 is the second transparent electrode TE2. And the third transparent electrode TE3 are electrically connected to each other.

Therefore, the first to third transparent electrodes TE1 to TE3 do not overlap the second and third data lines DL2 and DL3. However, the first connection electrode BE1 overlaps a part of the second data line DL2, and the second connection electrode BE2 overlaps a part of the third data line DL3. Accordingly, the overlapping portion between the pixel electrode PE and the second and third data lines DL2 and DL3 can be minimized.

Here, in order to further minimize the overlapping portion, it is preferable to minimize the areas of the first and second connection electrodes BE1 and BE2. That is, the first and second connection electrodes BE1 and BE2 preferably have an area such that the transparent electrodes TE1, TE2, and TE3 are not electrically separated from each other.

Meanwhile, the remaining pixel cells PXL included in the first pixel cell group Gr1 also have the same configuration as the first pixel cell PXL1 described above. That is, the second and third pixel cells PXL2 and PXL3 also have the same configuration as the first pixel cell PXL1.

4B is a diagram illustrating a structure of a fourth pixel cell included in the second pixel cell group of FIG. 3.

As shown in FIG. 4B, the fourth pixel cell PXL4 outputs a data signal from the second data line DL2 in response to the fourth scan pulse SP4 from the fourth gate line GL4. A thin film transistor TFT, a pixel electrode PE receiving a data signal from the thin film transistor TFT, a common electrode positioned to face the pixel electrode PE, a pixel electrode PE and a common electrode It includes a liquid crystal layer formed between.

The thin film transistor TFT is formed near the intersection of the fourth gate line GL4 and the second data line DL2. The thin film transistor TFT includes a gate electrode GE connected to the fourth gate line GL4, a semiconductor layer 401 formed on the gate electrode GE so as to overlap the gate electrode GE, and the A source electrode SE connected to the second data line DL2 and a drain electrode DE connected to the pixel electrode PE.

The pixel electrode PE provided in the fourth pixel cell PXL4 also has the same shape as the pixel electrode PE of the first pixel cell PXL1 described above. However, in the fourth pixel cell PXL4, the drain electrode DE of the thin film transistor TFT is formed of the first transparent electrode TE1, the second transparent electrode TE2, the third transparent electrode TE3, and the third transparent electrode TE3. Any one of the first connection electrode BE1 and the second connection electrode BE2 may be connected, but it is preferably connected to the second transparent electrode TE2 on the position of the thin film transistor TFT.

Meanwhile, the remaining pixel cells PXL included in the second pixel cell group Gr2 also have the same configuration as that of the fourth pixel cell PXL4 described above. That is, the fifth and sixth pixel cells PXL5 and PXL6 also have the same configuration as that of the fourth pixel cell PXL4.

4C is a diagram illustrating a structure of a seventh pixel cell included in the third pixel cell group of FIG. 3.

As shown in FIG. 4C, the seventh pixel cell PXL7 outputs a data signal from the third data line DL3 in response to the seventh scan pulse SP7 from the seventh gate line GL7. A thin film transistor TFT, a pixel electrode PE to receive a data signal from the thin film transistor TFT, a common electrode positioned to face the pixel electrode PE, and common to the pixel electrode PE. It includes a liquid crystal layer formed between the electrodes.

The thin film transistor TFT is formed near the intersection of the seventh gate line GL7 and the third data line DL3. The thin film transistor TFT includes a gate electrode GE connected to the seventh gate line GL7, a semiconductor layer 401 formed on the gate electrode GE so as to overlap the gate electrode GE, and the A source electrode SE connected to the third data line DL3 and a drain electrode DE connected to the pixel electrode PE are included.

The pixel electrode PE provided in the seventh pixel cell PXL7 also has the same shape as the pixel electrode PE of the first pixel cell PXL1 described above. However, the drain electrode DE of the thin film transistor TFT in the seventh pixel cell PXL7 includes the first transparent electrode TE1, the second transparent electrode TE2, the third transparent electrode TE3, and the third transparent electrode TE3. Any one of the first connection electrode BE1 and the second connection electrode BE2 may be connected, but it is preferably connected to the third transparent electrode TE3 on the position of the thin film transistor TFT.

Meanwhile, the remaining pixel cells PXL included in the third pixel cell group Gr3 also have the same configuration as the seventh pixel cell PXL7 described above. That is, the eighth and ninth pixel cells PXL8 and PXL9 also have the same configuration as the seventh pixel cell PXL7.

Here, the pixel cells PXL7, PXL8, and PXL9 included in the third pixel cell group Gr3 may have a data driver (PXL4, PXL5, PXL6) than the pixel cells PXL4, PXL5, and PXL6 included in the second pixel cell group Gr2. The pixel cells PXL4, PXL5, and PXL6 disposed in the second pixel cell group Gr2 are located farther from 202, and the pixel cells PXL1, which are included in the first pixel cell group Gr1. It is located farther from the data driver 202 than PXL2 and PXL3. That is, the pixel cells PXL1, PXL2, and PXL3 included in the first pixel cell group Gr1 are located closest to the data driver. Accordingly, the distortion degree of the data signal supplied to the pixel cells PXL7, PXL8, and PXL9 of the third pixel cell group Gr3 is equal to the pixel cells PXL4, PXL5, and the second pixel cell group Gr2. The distortion degree of the data signal larger than the distortion degree of the data signal supplied to the PXL6 and supplied to the pixel cells PXL4, PXL5, and PXL6 of the second pixel cell group Gr2 is the first pixel cell group Gr1. Is larger than the distortion degree of the data signal supplied to the pixel cells PXL1, PXL2, and PXL3.

In order to reduce such distortion deviations between the respective pixel cell groups, the width of the first data line DL1 connected to the first pixel cell group Gr1 is minimized, and the second pixel cell group Gr2 is connected. Making the width of the second data line DL2 larger than the width of the first data line DL1 and making the width of the third data line DL3 larger than the width of the second data line DL2. It is preferable.

In the display device according to the exemplary embodiment of the present invention, as shown in FIG. 5, a gate electrode GE formed on the substrate 500 and a gate formed on the entire surface of the substrate 500 including the gate electrode GE. A semiconductor layer 401 formed on the gate insulating layer GI so as to overlap the insulating layer GI and the gate electrode GE, and source / drain electrodes SE and DE formed at both edges of the semiconductor layer 401. ) And protection formed on the entire surface of the substrate 500 including the data lines DL2 and DL3 formed on the gate insulating layer GI, and the source / drain electrodes SE and DE and the data lines DL2 and DL3. And a pixel electrode PE connected to the drain electrode DE through a layer 514 and a contact hole C penetrating the protective layer 514 to expose a portion of the drain electrode DE.

Here, an ohmic contact layer 502 is further formed between the source / drain electrodes SE and DE and the semiconductor layer 401.

A capacitor may be formed at a portion where the pixel electrode PE and the data lines DL2 and DL3 overlap, and the protective layer 514 is preferably formed using an organic insulating layer to prevent the formation of such a capacitor. Do.

The protective layer 514 may be formed using an inorganic insulating film.

Since the organic insulating film has a lower dielectric constant than the inorganic insulating film and can be deposited thicker than the inorganic insulating film, the protective layer 514 is preferably formed of an organic insulating film.

The operation of the display device according to the embodiment of the present invention configured as described above will be described in detail as follows.

6A through 6C are diagrams for describing an operation of a display device according to an exemplary embodiment of the present invention.

First, as shown in FIG. 6A, the gate driver 201 simultaneously outputs the first, fourth, and seventh scan pulses SP1, SP4, and SP7 to output the first scan pulse SP1 to the first gate. The line GL1 is supplied, the fourth scan pulse SP4 is supplied to the fourth gate line GL4, and the seventh scan pulse SP7 is supplied to the seventh gate line GL7. Accordingly, the first, fourth, and seventh gate lines GL1, GL4, and GL7 are simultaneously driven.

Then, the first pixel cell PXL1 connected to the first gate line GL1, the fourth pixel cell PXL4 connected to the fourth gate line GL4, and the seventh gate line GL7. The connected seventh pixel cell PXL7 is driven simultaneously. That is, the thin film transistor TFT of the first pixel cell PXL1, the thin film transistor TFT of the fourth pixel cell PXL4, and the thin film transistor TFT of the seventh pixel cell PXL7 are simultaneously turned on. Is on.

In addition, the data driver 202 simultaneously outputs first to third data signals data1 to data3 to supply the first data signal data1 to the first data line DL1 and to supply the second data signal ( data2 is supplied to the second data line DL2, and the third data signal data3 is supplied to the third data line DL3.

Then, the first pixel cell (data1) charged in the first data line DL1 is connected to the first data line DL1 and has a first pixel cell TFT having a turn-on thin film transistor TFT. PXL1). That is, the first data signal data1 is supplied to the pixel electrode PE of the first pixel cell PXL1 through the turned-on thin film transistor TFT of the first pixel cell PXL1. Accordingly, the first pixel cell PXL1 displays an image according to the first data signal data1.

In addition, a fourth pixel cell having a turned-on thin film transistor TFT connected to the second data line DL2 is connected to the second data line DL2. PXL4). That is, the second data signal data2 is supplied to the pixel electrode PE of the fourth pixel cell PXL4 through the turned-on thin film transistor TFT of the fourth pixel cell PXL4. Accordingly, the fourth pixel cell PXL4 displays an image corresponding to the second data signal data2.

The third data signal data3 charged in the third data line DL3 is connected to the third data line DL3 and has a seventh pixel cell having a thin film transistor TFT in a turn-on state. PXL7). That is, the third data signal data3 is supplied to the pixel electrode PE of the seventh pixel cell PXL7 through the turned-on thin film transistor TFT of the seventh pixel cell PXL7. Accordingly, the seventh pixel cell PXL7 displays an image according to the third data signal data3.

Subsequently, as illustrated in FIG. 6B, the gate driver 201 simultaneously outputs the second, fifth, and eighth scan pulses SP2, SP5, and SP8 to output the second scan pulse SP2 to the second. The gate line GL2 is supplied, the fifth scan pulse SP5 is supplied to the fifth gate line GL5, and the eighth scan pulse SP8 is supplied to the eighth gate line GL8. Accordingly, the second, fifth, and eighth gate lines GL2, GL5, and GL8 are simultaneously driven.

Then, the second pixel cell PXL2 connected to the second gate line GL2, the fifth pixel cell PXL5 connected to the fifth gate line GL5, and the eighth gate line GL8. The connected eighth pixel cell PXL8 is driven simultaneously. That is, the thin film transistor TFT of the second pixel cell PXL2, the thin film transistor TFT of the fifth pixel cell PXL5, and the thin film transistor TFT of the eighth pixel cell PXL8 are simultaneously turned on. Is on.

In addition, the data driver 202 simultaneously outputs the fourth to sixth data signals data4 to data6 to supply the fourth data signal data4 to the first data line DL1, and the fifth data signal. Data5 is supplied to the second data line DL2, and the sixth data signal data6 is supplied to the third data line DL3.

Then, the second pixel cell having the turned-on thin film transistor TFT connected to the first data line DL1 is connected to the fourth data signal data4 charged in the first data line DL1. PXL2). That is, the fourth data signal data4 is supplied to the pixel electrode PE of the second pixel cell PXL2 through the turned-on thin film transistor TFT of the second pixel cell PXL2. Accordingly, the second pixel cell PXL2 displays an image according to the fourth data signal data4.

The fifth pixel cell charged with the second data line DL2 is connected to the second data line DL2 and has a turn-on thin film transistor TFT. PXL5). That is, the fifth data signal data5 is supplied to the pixel electrode PE of the fifth pixel cell PXL5 through the turned-on thin film transistor TFT of the fifth pixel cell PXL5. Accordingly, the fifth pixel cell PXL5 displays an image corresponding to the fifth data signal data5.

The sixth data signal data6 charged in the third data line DL3 is connected to the third data line DL3 and has an eighth pixel cell having a thin film transistor TFT in a turn-on state. PXL8). That is, the sixth data signal data6 is supplied to the pixel electrode PE of the eighth pixel cell PXL8 through the turned-on thin film transistor TFT of the eighth pixel cell PXL8. Accordingly, the eighth pixel cell PXL8 displays an image corresponding to the sixth data signal data6.

Subsequently, as illustrated in FIG. 6C, the gate driver 201 simultaneously outputs the third, sixth, and ninth scan pulses SP3, SP6, and SP9 to generate the third scan pulse SP3. The sixth scan pulse SP6 is supplied to the gate line GL3, the sixth scan pulse SP6 is supplied to the sixth gate line GL6, and the ninth scan pulse SP9 is supplied to the ninth gate line GL9. Accordingly, the third, sixth, and ninth gate lines GL3, GL6, and GL9 are simultaneously driven.

Then, the third pixel cell PXL3 connected to the third gate line GL3, the sixth pixel cell PXL6 connected to the sixth gate line GL6, and the ninth gate line GL9. The connected ninth pixel cell PXL9 is driven simultaneously. That is, the thin film transistor TFT of the third pixel cell PXL3, the thin film transistor TFT of the sixth pixel cell PXL6, and the thin film transistor TFT of the ninth pixel cell PXL9 are simultaneously turned on. Is on.

In addition, the data driver 202 simultaneously outputs the seventh to ninth data signals data7 to data9 to supply the seventh data signal data7 to the first data line DL1, and the eighth data signal. Data8 is supplied to the second data line DL2, and the ninth data signal data9 is supplied to the third data line DL3.

Then, the third pixel cell having the seventh data signal data7 charged in the first data line DL1 is connected to the first data line DL1 and has a thin film transistor TFT in a turn-on state. PXL3). That is, the seventh data signal data7 is supplied to the pixel electrode PE of the third pixel cell PXL3 through the turned-on thin film transistor TFT of the third pixel cell PXL3. Accordingly, the third pixel cell PXL3 displays an image according to the seventh data signal data7.

The sixth pixel cell (8) having the eighth data signal data8 charged in the second data line DL2 is connected to the second data line DL2 and has a thin film transistor TFT in a turn-on state. PXL6). That is, the eighth data signal data8 is supplied to the pixel electrode PE of the sixth pixel cell PXL6 through the turned-on thin film transistor TFT of the sixth pixel cell PXL6. Accordingly, the sixth pixel cell PXL6 displays an image corresponding to the eighth data signal data8.

The ninth pixel cell data9 charged in the third data line DL3 is connected to the third data line DL3 and has a ninth pixel cell TFT having a turn-on thin film transistor TFT. PXL9). That is, the ninth data signal data9 is supplied to the pixel electrode PE of the ninth pixel cell PXL9 through the turned-on thin film transistor TFT of the ninth pixel cell PXL9. Accordingly, the ninth pixel cell PXL9 displays an image corresponding to the ninth data signal data9.

In this way, the first subframe is completed. The first to ninth data signals data1 to data9 are R data signals for representing red color, and the red light R is emitted from the backlight unit 204 during the first subframe.

Thereafter, when the second and third subframes are completed by the above-described operation, one frame is completed. In this case, a G data signal for expressing green is supplied to the first to third data lines DL1 to DL3 in the second subframe. The backlight unit 204 emits green light G during the second sub frame to which the G data signal is supplied. The B data signal for expressing blue is supplied to the first to third data lines DL1 to DL3 in the third subframe. The backlight unit 204 emits blue light B during the third sub frame to which the B data signal is supplied.

As described above, in the present invention, since the gate lines GL1 to GL9 of the pixel cell groups Gr1 to Gr3 are simultaneously driven, the scan time of each gate line GL can be increased relatively compared to the conventional art.

In this case, the scan time of each gate line GL increases as the number of pixel cell groups Gr1 to Gr3 increases. That is, the scan time increases as the number of gate lines GL driven simultaneously increases.

For example, a conventional display device scans each gate line GL1 to GL9 for one horizontal time to drive nine gate lines GL in one sub frame time (assuming 9 horizontal time periods). . In contrast, the display device of the present invention scans the gate lines GL1 to GL9 for three horizontal hours in order to drive the nine gate lines GL1 to GL9 within one sub frame time.

Therefore, the display device of the present invention can scan each gate line GL for about three times longer than the conventional display device. As a result, the thin film transistor TFT provided in each pixel cell PXL can remain turned on for about three times longer than the conventional one, and according to the present invention, the size of the thin film transistor TFT The charging time of each pixel cell PXL can be sufficiently secured even if the size of the pixel cell PXL is not increased.

Here, the pixel cells PXL7, PXL8, and PXL9 included in the third pixel cell group Gr3 may have a data driver (PXL4, PXL5, PXL6) than the pixel cells PXL4, PXL5, and PXL6 included in the second pixel cell group Gr2. The pixel cells PXL4, PXL5, and PXL6 disposed in the second pixel cell group Gr2 are located farther from 202, and the pixel cells PXL1, which are included in the first pixel cell group Gr1. It is located farther from the data driver 202 than PXL2 and PXL3. That is, the pixel cells PXL1, PXL2, and PXL3 included in the first pixel cell group Gr1 are located closest to the data driver 202.

Accordingly, the distortion degree of the data signal supplied to the pixel cells PXL7, PXL8, and PXL9 of the third pixel cell group Gr3 is equal to the pixel cells PXL4, PXL5, and the second pixel cell group Gr2. The distortion degree of the data signal larger than the distortion degree of the data signal supplied to the PXL6 and supplied to the pixel cells PXL4, PXL5, and PXL6 of the second pixel cell group Gr2 is the first pixel cell group Gr1. Is larger than the distortion degree of the data signal supplied to the pixel cells PXL1, PXL2, and PXL3.

In order to solve this problem, the data driver 202 of the present invention supplies data signals having different sizes to the first data line DL1, the second data line DL2, and the third data line DL3. .

7 is a diagram illustrating a data driver and first to third gray voltage generators supplying a gray voltage to the data driver.

The data signal represents a gray voltage, and the gray voltage is supplied from the first to third gray voltage generators 701 to 703 to the data driver 202.

The data driver 202 may control the R, G, and B data signals from the timing controller and the gray voltages V1_F to V64_F, V1_S to V64_S, and V1_T to the first to third gray voltage generators 701 to 703. The gray voltage corresponding to the data signal is selected from among the gray voltages V1_F to V64_F, V1_S to V64_S, and V1_T to V64_T, and is supplied to the data lines.

If the data signal supplied to the data driver 202 is 6 bits, a total of 64 gray voltages are required.

To this end, the first to third gray voltage generators 701 to 703 generate the first to 64th gray voltages V1_F to V64_F, V1_S to V64_S, and V1_T to V64_T, and the data driver 202 generates them. To feed.

In this case, the first gray voltage generator 701 generates the first to 64th gray voltages V1_F to V64_F using the first reference voltage VDD1, and the second gray voltage generator 702 The first to 64 th gray voltages V1_S to V64_S are generated using the second reference voltage VDD2, and the third gray voltage generator 703 uses the first to third to use the third reference voltage VDD3. Generates 64 gray voltages (V1_T ~ V64_T).

The first to third gray voltage generators 701 to 703 have a circuit configuration as follows.

FIG. 8 is a diagram illustrating a circuit configuration of the first to third gray voltage generators of FIG. 7.

As illustrated in FIG. 8, the first gray voltage generator 701 includes a plurality of resistors R1 to R65 for dividing the first reference voltage VDD1. The resistors R1 to R65 are connected in series between a first terminal receiving the first reference voltage VDD1 and a ground terminal. The voltage that is divided and output between the resistors R1 to R65 is a gradation voltage.

The second gray voltage generator 702 includes a plurality of resistors R1 to R65 for dividing the second reference voltage VDD2. The resistors R1 to R65 are connected in series between a second terminal receiving the second reference voltage VDD2 and a ground terminal. The voltage that is divided and output between the resistors R1 to R65 is a gradation voltage.

The third gray voltage generator 703 includes a plurality of resistors R1 to R65 for dividing the third reference voltage VDD3. The resistors R1 to R65 are connected in series between a third terminal for supplying the third reference voltage VDD3 and a ground terminal. The voltage that is divided and output between the resistors R1 to R65 is a gradation voltage.

Here, the first reference voltage (VDD1) is the smallest, the third reference voltage (VDD3) is the largest, the second reference voltage (VDD2) is greater than the first reference voltage (VDD1) and the third reference voltage (VDD3). Suppose it is smaller than

Then, the gray voltages V1_F to V64_F output from the first gray voltage generator 701 have the smallest magnitude, and the gray voltages V1_T to V64_T output from the third gray voltage generator 703. ) Represents the largest size. The gray voltages V1_S to V64_S output from the second gray voltage generator 702 may be larger than the gray voltages V1_F to V64_F output from the first gray voltage generator 701. The size of the third gray voltage generator 703 is smaller than the gray voltages V1_T to V64_T output from the third gray voltage generator 703.

At this time, the gradation voltages having gradation values corresponding to each other are different from each other. For example, the first gray voltage V1_S from the second gray voltage generator 702 is greater than the first gray voltage V1_F from the first gray voltage generator 701, and the third gray voltage generator It is smaller than the first gradation voltage V1_T from 703.

The data driver 202 is supplied with the data signal supplied thereto, and the gray voltages V1_F to V64_F, V1_S to V64_S, and V1_T to V64_T supplied from the first to third gray voltage generators 701 to 703. Gray level voltages having a gray level value corresponding to the data signal are selected and supplied to each data line.

In this case, the data driver 202 selects one of the gray voltages V1_F to V64_F from the first gray voltage generator 701 and supplies it to the first data line DL1. Then, one of the gray voltages V1_S to V64_S from the second gray voltage generator 702 is selected and supplied to the second data line DL2. Then, one of the gray voltages V1_T to V64_T from the third gray voltage generator 703 is selected and supplied to the third data line DL3.

 That is, since the first pixel cell group Gr1 is located at the closest distance from the data driver 202, a first gray voltage is generated in the first data line DL1 to which the first pixel cell group Gr1 is connected. Since the gradation voltage from the part 701 is supplied, and the third pixel cell group Gr3 is located at the furthest distance from the data driver 202, the third data connected to the third pixel cell group Gr3. The gray level voltage from the third gray voltage generator 703 is supplied to the line DL3. Since the second pixel cell group Gr2 is positioned at an intermediate distance, the gray voltage from the second gray voltage generator 702 is supplied to the second pixel cell group Gr2.

When the voltage corresponding to the first gray level is supplied to all of the first to third data lines DL3, even if the distance between each pixel cell group Gr1 to Gr3 from the data driver 202 is different, each of the first to third data lines DL3 is different. Since the magnitudes of the gradation voltages V1_F, V1_S, and V1_T corresponding to the first gradations supplied to the three data lines DL1 to DL3 are different, the luminance difference according to the distance difference between the respective pixel cell groups Gr1 to Gr3 is compensated for. do.

The number of reference voltages increases in proportion to the number of pixel cell groups. For example, if the number of pixel cell groups is n (n is a natural number), it is preferable to set the number of the reference voltages to n.

In the above embodiment, the case where n is 3 has been described. In this case, the data driver 202 includes 3k + 1 (k is a natural number including 0) th data lines including the first data line DL1. The gray voltage selected from the first gray voltage generator 701 is supplied to the 3k + 2th data lines including the second data line DL2, and the gray scale selected from the second gray voltage generator 702 is provided. A voltage is supplied, and a gray voltage selected from the third gray voltage generator 703 is supplied to a 3k + 3th data line including the third data line DL3.

The above-described gray voltages V1_F to V64_F, V1_S to V64_S, and V1_T to V64_T describe positive gray voltages, that is, gray voltages having a larger value than the common voltage.

Although not shown in the drawings, in order to prevent deterioration of the liquid crystal, each gray voltage generator 701 to 703 may include negative gray voltages in addition to the positive gray voltages V1_F to V64_F, V1_S to V64_S, and V1_T to V64_T. That is, the gray scale voltages having a smaller value than the common voltage are further output.

The positive gray voltages V1_F to V64_F and the negative gray voltages from the first gray voltage generator 701 have different polarities, and are absolute of the positive gray voltage and the negative gray voltage having corresponding gray levels. The magnitude of the values is the same.

The positive gray voltages V1_S to V64_S and the negative gray voltages from the second gray voltage generator 702 have different polarities, and are absolute of the positive gray voltage and the negative gray voltage having corresponding gray levels. The magnitude of the values is the same.

The positive gray voltages V1_T to V64_T and the negative gray voltages from the third gray voltage generator 703 have different polarities, and are absolute of the positive gray voltage and the negative gray voltage having corresponding gray levels. The magnitude of the values is the same.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents. Will be clear to those who have knowledge of.

As described above, the display device according to the present invention has the following effects.

The display device according to the present invention drives at least two gate lines simultaneously, and increases the scan time of the gate lines by allowing each pixel cell connected to the simultaneously driven gate lines to be driven by different data lines. have.

In addition, the display device according to the present invention supplies a gray scale voltage having a different magnitude to the data lines of each pixel cell group, so that the pixel cells in the different pixel cell groups according to the distance difference between the pixel cell groups from the data driver are different. The luminance difference can be prevented.

Claims (13)

A display unit including at least one first pixel cell group and at least one second pixel cell group; A first data line connected to pixel cells in the first pixel cell group; A second data line connected to pixel cells in the second pixel cell group; A gate driver for simultaneously driving at least one pixel cell in the first pixel cell group and at least one pixel cell in the second pixel cell group; And The first and second gray voltage groups having different sizes are supplied, and the gray voltage is selected from the first gray voltage group according to a data signal and supplied to the first data line, and the gray voltage is supplied from the second gray voltage group. A data driver for selecting and supplying the second data line; And the gate driver simultaneously drives arbitrary pixel cells of the 2n-1 pixel cell group and pixel cells belonging to the 2n pixel cell group and corresponding to the arbitrary pixel cells. The method of claim 1, A first gray voltage generator configured to receive a first reference voltage and generate the first gray voltage group; And And a second gray voltage generator configured to receive a second reference voltage having a different magnitude from the first reference voltage to generate the second gray voltage group. The method of claim 2, The first gray voltage generator includes a plurality of resistors connected in series between a first terminal receiving the first reference voltage and a ground terminal; And, And the second gray voltage generator includes a plurality of resistors connected in series between a second terminal receiving the second reference voltage and a ground terminal. The method of claim 1, The first and second gray voltage group, A display device comprising a plurality of positive grayscale voltages and a plurality of negative grayscale voltages. The method of claim 1, And the gate driver sequentially drives the pixel cells of the first pixel cell group in a first direction, and sequentially drives the pixel cells of the second pixel cell group in the first direction. delete The method of claim 1, And the gate driver simultaneously drives a pixel cell located at an uppermost side in the 2n-1 pixel cell group and a pixel cell located at an uppermost side in the 2n pixel cell group. The method of claim 1, Each pixel cell, A switching element for switching a data signal from a data line in response to a scan pulse from the gate driver; A pixel electrode configured to receive a switched data signal from the switching device; A common electrode positioned to face the pixel electrode; And And a liquid crystal layer formed between the pixel electrode and the common electrode. The method of claim 1, Wherein each pixel cell displays a red image during a first subframe, a green image during a second subframe, and a blue image during a third subframe. The method of claim 9, Supply red light to the pixel cells during the first subframe, supply green light to the pixel cells during the second subframe, and supply blue light to the pixel cells during the third subframe. And a back light unit. A display unit including at least one first pixel cell group and at least one second pixel cell group; A first data line connected to pixel cells in the first pixel cell group; A second data line connected to pixel cells in the second pixel cell group; A method of driving a display device, comprising: a gate driver for simultaneously driving at least one pixel cell in the first pixel cell group and at least one pixel cell in the second pixel cell group; Selecting a gray voltage from a first gray voltage group and supplying the gray voltage to the first data line; And Selecting a gray voltage from a second gray voltage group different from the first gray voltage group and supplying the gray voltage to the second data line; And the gate driver simultaneously drives arbitrary pixel cells of the 2n-1 pixel cell group and pixel cells belonging to the 2n pixel cell group and corresponding to the arbitrary pixel cells. The method of claim 11, The first gray level voltage group is generated by dividing a first reference voltage, and the first gray level voltage group is generated by dividing a second reference voltage having a different magnitude from the first reference voltage. Driving method. The method of claim 1, Pixel cells in the second pixel cell group are farther from the data driver than pixel cells in the first pixel cell group; And, And the gradation voltage selected from the second gradation voltage group corresponds to the gradation voltage and has a value greater than the gradation voltage selected from the first gradation voltage group.

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