KR101306272B1 - A cascade comparator and control method therof - Google Patents

Abstract

The present invention relates to a cascade comparator and a control method thereof. When multiple comparators are cascaded, a clock signal applied to a comparator is generated in a multi-phase form and applied to each comparator. Before the shear comparator is reset, the trailing comparator is regenerated to remove the hold switch between the comparators. According to this, since the area and parasitic components due to the hold switch can be reduced, high-speed operation is possible, and glitches generated in the hold switch are eliminated, thereby improving the linearity of the entire system.

Cascade, comparator, analog-to-digital converter, reset phase, regeneration phase, clock signal.

Description

Cascade comparator and control method {a cascade comparator and control method therof}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a comparator and a control method thereof, particularly in a cascade comparator used in an analog-to-digital converter (ADC), in which a hold switch for storing the output result of the front end is removed. And a control method thereof.

A comparator is a device that compares an input signal with a reference signal and outputs a result, and is used in analog-to-digital converters (ADCs) that convert analog signals to digital. For example, it is possible to utilize the analog-to-digital converter by comparing the sampled analog voltage with a reference voltage and outputting 1 when the sampled voltage is larger than the reference voltage and outputting 0 when the sampled voltage is larger than the reference voltage.

On the other hand, there are various types of analog / digital converters (ADCs), such as parallel comparison type, sequential comparison type, simple counting type, and integral type. (flash ADC) has been used a lot lately. This parallel comparison type performs an analog-to-digital conversion by comparing an analog input signal with a reference voltage divided by several resistance ladders.

It is also possible to use only one stage comparator, depending on the number of bits to be converted, but if only one comparator is used, the bit error rate (BER) of the entire system is very short when the sampling clock period is very short. There is a problem with this increase. Thus, it is common to use cascade comparator composed of multi stages. Here, cascade connection refers to a multi-stage amplification method that connects the output terminals of the 4-terminal network to the input terminals of the next 4-terminal network in order. Cascading multiple comparators in this way increases the regeneration gain of the signal and reduces the chance of falling into a meta-stable state.

In this case, when a plurality of comparators are cascaded, it is necessary to keep the output of the front end constant and deliver it to the rear end input. This is because, in the case of the multi-stage comparator, the stages are sequentially operated according to the phase of the operation clock, so that the front stage enters the reset state when the rear stage is operated. When the front output goes into the reset state, the rear input also becomes the reset state and the input voltage changes so that the certainty of the output data cannot be guaranteed after going through a plurality of comparators.

In order to prevent this phenomenon, a method of holding a signal by inserting a hold switch between multiple comparators is generally used. The principle is that the hold switch is also turned on during the operation of the front end, and the output voltage of the front end is charged to the input parasitic capacitance of the rear end through the hold switch. By operating the rear stage by the stored input voltage, even if the output of the front stage is reset, it is possible to perform a stable cascading operation without affecting the input of the rear stage.

In other words, if multiple comparators are cascaded, it is necessary to keep the output of the previous stage at the value at the sampling point, so that a hold switch can be inserted between the comparators to store the input, regardless of the output change of the preceding stage. It is configured to maintain.

However, the hold switch between comparators has a problem of unnecessarily increasing the area of the entire circuit. As the area increases, parasitic components also increase, which can increase power consumption in high-speed circuits (e.g., high-speed ADCs, etc.), and glitches caused by hold switches can interfere with linear operation. It can degrade performance.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problems, and an object thereof is to provide a cascade comparator and a method of controlling the same, by eliminating a hold switch formed between the comparators to reduce area, parasitic components, nonlinear components, and the like.

The above object is achieved by appropriately adjusting the clock signal applied to the comparator so that the regeneration of each comparator is sequentially overlapped with some overlap.

More specifically, the cascade comparator according to the present invention compares two input signals, amplifies the difference, outputs a differential signal, and a plurality of comparators connected to each other in a cascade structure. ; And applying a clock signal to each of the plurality of comparators to independently adjust a reset phase and a regeneration phase of each comparator, wherein the regeneration phases of the comparators are partially overlapped and sequentially. It characterized in that it comprises a; clock generator for generating two or more clock signals to generate.

In addition, the clock generation unit generates a second clock signal that partially overlaps the first clock signal input to the front end comparator such that the rear end comparator is regenerated before the output of the front end comparator is reset. It is preferable.

The comparator may further include: a first comparator, in which a pre-amplifier and a regeneration amplifier are combined to repeat reset and replay at regular intervals; And a second comparator connected to a rear end of the first comparator and activated during operation of the regeneration amplifier.

The second comparator may include a precharge unit configured to charge an output of the first comparator; And a cross-coupled inverter connected to the precharge unit and maintaining an output of the second comparator.

In addition, such a cascade comparator is preferably used in a high speed analog-to-digital converter (ADC).

Meanwhile, the cascade comparator control method according to the present invention compares two input signals, amplifies the difference, outputs a differential signal, and resets and reproduces periodically according to a clock signal. CLAIMS What is claimed is: 1. A method of controlling a cascade comparator comprising a plurality of repeating comparators, the method comprising: generating and applying a first clock signal to a first comparator; And generating and applying a second clock signal, which is partially overlapped with the first clock signal, to the second comparator such that the second comparator is reproduced before the first comparator is reset. do.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following description of the present invention, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear. In addition, terms to be described later are terms defined in consideration of functions in the present invention, which may vary according to a user, an operator's intention or custom. Therefore, the definition should be based on the contents throughout this specification.

1 shows a schematic configuration of a cascade comparator according to an embodiment of the present invention, and shows an example used as one component of a high speed analog-to-digital converter (ADC).

Referring to FIG. 1, a comparator according to an embodiment of the present invention includes a plurality of comparators 100 and a clock generator 200 for applying a clock signal to the comparator 100. . In addition, a track / hold switch 301 is provided at the front of the comparator 100 and an encoder 302 is provided at the rear of the comparator 100 so as to be used as a converter for converting an analog signal into a digital signal.

The comparator 100 has a cascade structure, and a plurality of the comparators are connected to each other. As illustrated, the comparator 100 includes a first comparator 101, a second comparator 102, and an n th comparator 103. can do. Each of the comparators 101, 102, and 103 compares two input signals, amplifies the difference, and outputs a differential signal. For example, the inputted received voltage and the reference voltage are compared to output a differential voltage corresponding to the difference, and the output differential voltage is used as a later input again.

The clock generator 200 applies predetermined clock signals to the comparators 101, 102, and 103, respectively, and resets the reset phases of the comparators 101, 102, and 103, respectively. Independently adjust the regeneration phase. Here, the reset phase is a stage in which the output signal is amplified by the gain of the amplifier as the input signal is transmitted to the amplifier or the comparator. If the reset switch is turned on at the output stage and the two output stages are connected, the output voltage difference may be smaller than the gain of the amplifier. The regeneration phase refers to a step in which a slight voltage difference appearing at the output stage in the reset state is greatly amplified by positive feedback of the regeneration amplifier. Accordingly, in response to the clock signal of the clock generator 200, the comparison units 101, 102, 103 are periodically reset and regeneration, and the output of the front comparator is applied to the rear comparator. do.

In this case, the clock generator 200 generates at least two or more clock signals such that the regeneration phases of the comparators 101, 102, and 103 partially overlap each other to sequentially generate the at least two clock signals. 102 and 103 respectively. For example, the clock generator 200 may be applied to the first comparator 101 such that the second comparator 102 is regenerated before the output of the first comparator 101 is reset. The second clock signal, which partially overlaps the clock signal, may be generated and applied to the second comparator 102. Therefore, it is possible to use a signal delayed slightly from the first clock signal as the second clock signal.

As described above, when two or more multi-phase clocks are used as a signal for controlling the comparator 100, the regeneration time overlaps with a part of the regeneration time. It is possible to remove the hold switch formed between the (101) (102) and (103).

2 illustrates a circuit configuration of each comparison unit, and FIG. 3 illustrates a clock signal generated by the clock generator.

In FIG. 2, only the first comparator 101 and the second comparator 102 are shown, but at the rear end of the second comparator 102, a circuit having the same configuration as the second comparator 102 is repeatedly provided. Can be connected. In addition, vip and vin represent an input signal (e.g., an input voltage), and vop and von represent an output signal (e.g., an output voltage). Since the first comparator 101 and the second comparator 102 are connected in a cascade structure, the output signal of the first comparator 101 is used as an input signal of the second comparator 102.

The first comparator 101 includes a pre-amplifier 401 and a regeneration amplifier 402 formed by interconnecting n-type or p-type morph transistors. The first clock signal clke 601 of FIG. 3 is applied to the first comparator 101. The nMOS 403 formed on the preamplifier 401 and the nMOS 404 formed on the reproducing amplifier 402 are provided to the first comparator 101. The direction of the applied clock signal is opposite to each other, and since the path switching switch 405 is formed at the connection portion, the preamplifier 401 and the reproduction amplifier 402 are alternately operated by the first clock signal 601. . At this time, since the path switching switch 405 is turned on while the preamplifier 401 is operating, a reset phase is performed along a reset path, and the path switching is performed while the reproducing amplifier 402 is operating. The switch 405 is turned off and a regeneration phase is performed along the regeneration path.

For example, in the reset phase, assuming clke is low (clkeb represents the bar signal of clke, therefore, clkeb is high when clke is low. ) Is turned on so that only the preamplifier 401 is turned on and the regeneration amplifier 402 is turned off. Then, the preamplifier 401 amplifies the input difference vip-vin to generate a slight voltage difference Vop-von at the output terminal. In a subsequent regeneration, if clke goes high and clkeb goes low, the path switch 405 turns off and the slight voltage difference seen in the previous reset phase is regenerated. By amplifying again by gain of), it acts on the output load and the differential output appears.

The second comparator 102 is connected to the rear end of the first comparator 101 and is activated while the regeneration amplifier 402 is operating. In addition, the second comparator 102 is connected to the precharge unit 501 to which the output of the first comparator 101 is charged and the precharge unit 501 to maintain the output of the second comparator 102. It consists of a cross-coupled inverter (502). At this time, the switch 503 formed in the precharge unit 501 and the switch 504 formed in the cross-coupled inverter 502 are each formed of different types of transistors to precharge at a predetermined period with respect to a predetermined clock signal. ) And regeneration can be repeated. Therefore, of course, a dynamic comparator may be used as the second comparator 102.

In order to enable the second comparator 102 while the regenerative amplifier 402 of the first comparator 101 is operating, it is preferable to apply a clock signal as shown in FIG. 3. Referring to FIG. 3, the first clock signal 601 is applied to the first comparator 101 and the second clock signal 602 is applied to the second comparator 102. Here, it can be seen that the second clock signal 602 is a signal delayed slightly so as to be regenerated before the first clock signal 601 is reset again.

When the clock signal as shown in FIG. 3 is applied to the first comparator 101 and the second comparator 102, respectively, the output of the first comparator 101 is applied to the differential input of the second comparator 102. At this time, since a regeneration clock signal is also applied to the second comparator 102, the precharge switch 503 of the second comparator 102 is turned on and the second comparator 102 is activated. it is enabled and regeneration occurs. In addition, the second comparator 102 includes a cross-coupled inverter 502 so that the output remains unchanged even when the first comparator 101 returns to the reset state.

FIG. 4 exemplarily illustrates a configuration of a clock generator that generates a multi-phase clock as described above. As shown in FIG. 4, when the basic period clk is input and the appropriate number of inverters is passed, the second clock signal slightly delayed from the first clock signal clke 601 and the first clock signal clke 601. It is possible to generate (clkd).

As a result, in the past, a hold switch was formed between the front / rear comparator and the front end and rear end inputs were cut off using the hold switch to maintain the rear end input even when the front end output was reset. Likewise, if the clock signal is properly adjusted to overlap the point of time when regeneration occurs, the rear end output can be maintained as it is when the front end output is reset without using a conventional hold switch. .

5 is a flowchart illustrating a cascade comparator control method according to an embodiment of the present invention.

In the present embodiment will be described by citing the above-described cascade comparator. Accordingly, the cascade comparator compares two input signals, amplifies the difference, outputs a differential signal, and a plurality of comparators which periodically reset and regenerate the clock signal according to a clock signal. It is possible to be connected to each other. For example, the first comparator 101 of FIG. 2 may be used as the front comparator, and the second comparator 102 of FIG. 2 may be used as the back comparator.

The process of controlling such a cascade comparator is as follows.

First, a first clock signal 601 as shown in FIG. 3 is generated and applied to the first comparator 101 (S701). The first clock signal 601 may use a pulse signal in which low / high is repeated at a constant period. As described above, the first comparator 101 repeats the reset and the reproduction in accordance with the first clock signal 601. When the first clock signal 601 is low, the reset is performed.

Next, the second clock signal 602 as shown in FIG. 3 is generated and applied to the second comparator 102 (S702). That is, the second clock signal 602 is a signal (eg, overlapped with a portion of the first clock signal so that the second comparator 102 is reproduced before the first comparator 101 is reset). Slightly delayed compared to the first clock signal).

In addition, when three or more comparators are connected, it is possible to similarly delay the clock signal applied to the front comparator to be applied to the rear comparator so that the rear comparator can be reproduced before the front comparator is reset.

As such, when multiple stage comparators are cascaded, the hold switch can be removed by generating a multi-phase clock so that the regeneration phase overlaps. This reduces the area of the entire circuit and reduces parasitic components, enabling high speed operation.

In addition, power consumption is reduced overall because no driver is required to drive the hold switch. In particular, linearity is improved by eliminating glitches that can occur at the hold switch and affect either the front output or the back input.

Although the preferred embodiments of the present invention have been described, the present invention is not limited to the specific embodiments described above. It will be apparent to those skilled in the art that numerous modifications and variations can be made in the present invention without departing from the spirit or scope of the appended claims. And equivalents should also be considered to be within the scope of the present invention.

1 is a block diagram showing the overall configuration of a cascade comparator according to an embodiment of the present invention,

2 is a circuit diagram of a cascade comparator according to an embodiment of the present invention;

3 is a reference diagram illustrating a partially overlapping clock signal according to an embodiment of the present invention;

4 is a circuit diagram illustrating a clock generator according to an exemplary embodiment of the present invention;

5 is a flowchart illustrating a control method of the cascade comparator according to an embodiment of the present invention.

DESCRIPTION OF THE RELATED ART [0002]

101: first comparator 102: second comparator

200: clock generator 401: preamplifier

402: regeneration amplifier 501: precharge unit

502: cross coupled inverter 601: first clock signal

602: second clock signal

Claims (10)

Comparing a plurality of input signals and amplifying the difference to output a differential signal, and a plurality of comparison units connected to each other in a cascade structure; And Respectively applied to the plurality of comparators to independently adjust the reset phase and the regeneration phase of each comparator, so that the regeneration phase of each comparator is partially overlapped and sequentially generated. And a clock generator for generating two or more clock signals to be adjusted. The method of claim 1, The clock generation unit generates a second clock signal partially overlapping the first clock signal input to the front end comparator such that the rear end comparator is regenerated before the output of the front end comparator is reset. Cascade comparator. The method of claim 1, Wherein, A first comparator formed by combining a pre-amplifier operating in the reset step and a regeneration amplifier operating in the reproducing step; And And a second comparator connected to a rear end of the first comparator, wherein a second comparator is generated while the regeneration amplifier is operating. The method of claim 3, wherein The second comparison unit, A precharge unit charging an output of the first comparator; And And a cross-coupled inverter connected to the precharge unit and configured to maintain an output of the second comparator. The method of claim 3, wherein The second comparator is formed by combining a plurality of dynamic comparator (cascade comparator), characterized in that. The method of claim 1, Wherein each comparator amplifies an input voltage and outputs a differential voltage. The method of claim 1, The cascade comparator is used for a high speed analog-to-digital converter (ADC). Compares two input signals, amplifies the difference, outputs a differential signal, and controls a cascade comparator consisting of a plurality of comparators which repeat reset and regeneration periodically according to a clock signal. As a method, Generating and applying a first clock signal to the first comparator; And Generating and applying to the second comparator a second clock signal which is partially overlapped with the first clock signal so that the second comparator is reproduced before the first comparator is reset. Cascade comparator control method. 9. The method of claim 8, The first comparator controls a cascade comparator, wherein a pre-amplifier and a regeneration amplifier are combined to reset and regenerate according to the first clock signal. Way. 9. The method of claim 8, The second comparison unit, A precharge unit charging an output of the first comparator; And And a cross-coupled inverter connected to the precharge unit and maintaining an output of the second comparator.

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