JPH1084260A - Comparator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To output the normal result of comparison with fast clock frequency against the delicate analog input of a low voltage level by preparing an N- channel MOS transistor TR Which functions as a constant current source for the differential pair of a pre-amplifier. SOLUTION: A pre-amplifier 2 consists of the NPN TR Q5 and Q6 whose bases are connected to the emitters of the NPN TR Q1 and Q2 with collectors connected to one of both ends of each of resistances R5 and R6 constructing a collector load circuit and the emitters connected in common to each other and constructing a differential pair respectively, and an N-channel MOS TR MN1 which receives the bias power voltage Vb2 via its gate and has a drain connected to a common emitter of both TR Q5 and Q6 and a source connected to a power supply Vcc2 respectively. The TR MN1 uses an NMOSFET having a large W/L (channel width/length), so that a saturated state can be kept even at a low drain-source voltage level.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a comparison circuit,
In particular, the present invention relates to a comparison circuit which is suitable for use in a low power supply voltage / high speed analog / digital converter (referred to as “A / D converter”).

[0002]

2. Description of the Related Art Conventionally, as a conversion method for realizing a high-speed and high-precision A / D converter, an all-parallel type and a series-parallel type are generally used. In this type of conversion method, a high-speed and high-input-accuracy comparison circuit is indispensable for converting an analog signal into a digital code.

[0003] A conventional comparison circuit of this type is disclosed in, for example, Reference 1 (IEICE Technical Report ICD91-85) and Reference 2 (IEEE 1987 ISSCC Digest).
oftechnical papers pp. 98-
99), etc., it mainly includes an emitter follower, a preamplifier, and a strobe comparator. FIG. 3 shows a circuit configuration of a conventional comparison circuit of this type.

Referring to FIG. 3, this conventional comparison circuit comprises an emitter follower 1 having an analog input signal as an input, a preamplifier 2 having a differential input as an output of the emitter follower 1, and a preamplifier 2 having a differential input. And a strobe comparator 3 for inputting differential outputs of the transistors Q1 and Q2. The emitter follower 1 has transistors Q1 and Q2 having analog input voltages Vin1 and Vin2 input to a base and collectors connected to a power supply Vcc1, and a base connected to a base. Bias power supply voltage Vb1
, And transistors Q3 and Q4 each having one end of each of resistors R1 and R2 connected to the emitter.

The preamplifier 2 has a base connected to the emitters of the transistors Q1 and Q2, a collector connected to one ends of resistors R5 and R6 forming the collector load circuit 4, and an emitter connected to the transistor Q5. , Q6 and a bias power supply voltage Vb
1, a transistor Q16 whose collector is connected to the commonly connected emitters of the transistors Q5 and Q6, and whose emitter is connected to one end of the resistor R9.

The strobe comparator 3 has a base connected to the output of the preamplifier 2 (a connection point between the transistors Q5 and Q6 and the load resistors R5 and R6), and a collector connected to one ends of the resistors R3 and R4. , Transistors Q7 and Q8 whose emitters are connected in common, and transistors Q9 and Q10 whose collectors are connected to one ends of resistors R3 and R4 and whose bases are connected to one ends of resistors R4 and R3, respectively, and whose emitters are connected in common. , Base are applied with first and second clock signals CLK and CLKB, respectively, and collectors are connected to transistors Q8 and Q9, respectively.
, A common emitter of transistors Q9 and Q10, transistors Q11 and Q12 whose emitters are commonly connected, and a bias power supply voltage Vb1 at the base.
And a constant current source 5 formed by a transistor Q15 having one end connected to the emitter of the resistor R8.

[0007] Each circuit constituting the comparison circuit of FIG. 3 will be described.

The emitter follower 1 keeps the input current of the comparison circuit constant so as to reduce the distortion of the input signal, and reduces the sneak of kickback noise to the input signal.

The preamplifier 2 amplifies a very small analog input voltage to reduce conversion errors and enable high-speed operation.

The strobe comparator 3 amplifies the outputs Vout1 and Vout2 of the comparison circuit to a digital signal level by controlling the first and second clock signals CLK and CLKB which are complementary to each other.

Therefore, a small analog input can be compared by a high-speed clock operation by a comparison circuit composed of the emitter follower 1, the preamplifier 2, and the strobe comparator 3, and the result can be amplified to a digital level.

Next, the operation of the conventional comparison circuit shown in FIG. 3 will be briefly described with reference to a signal waveform diagram shown in FIG.
FIG. 4 shows analog input signal voltages Vin1 and Vin2.
(FIG. 4A), output voltages Vout1, Vout2
(FIG. 4B) shows the timing signal waveforms of the first and second clock signals CLK and CLKB (FIG. 4C) which are complementary to each other.

In the conventional comparator shown in FIG. 3, when the positive-phase clock signal CLK is at a high level (CLKB is at a low level),
The two analog inputs Vin1 and Vin2 are compared, and the output follows the input (follow mode). That is,
When the positive-phase clock signal CLK is at a high level, the transistor Q
11 is turned on (transistor Q12 is turned off), and the output of a differential pair consisting of transistors Q7 and Q8 having the output of preamplifier 2 as input is digital output Vout1, Vout.
It is transmitted to t2.

On the other hand, when the inverted phase clock signal CLKB is at a high level, the output at the moment when the clock signal is switched is re-amplified to a digital level (latch mode). That is, when the inverted-phase clock signal CLKB is at a high level, in the strobe comparator 3, the transistor Q12 is turned on (the transistor Q11 is turned off) and the transistor Q12 is turned off.
9 and Q10 are transistors Q8 and Q7.
(Therefore, Vout2, Vout2)
1) is used as a base input, and the output at the time when the clock is switched is latched.

As shown in FIG. 4, a small difference voltage (0.5
mV), and the result is amplified and transmitted to the digital output.

[0016]

However, the above-mentioned conventional comparison circuit has a problem that analog inputs at low voltage levels cannot be compared normally. This problem is solved by the circuit configuration diagram shown in FIG.
This will be described below with reference to the signal waveform diagram shown in FIG.

Referring to FIG. 3, in the conventional comparison circuit, Vbe is a base-emitter voltage of a bipolar transistor, VIb is a voltage required for a constant current source of a preamplifier 2 composed of a bipolar transistor. Expressions (1) and (2) are given.

Vbe ≒ 0.8 V (1) VIb ≧ 0.6 V (2)

VIb includes the collector-emitter voltage required so that transistor Q16 acting as a constant current source does not saturate. Therefore, in the conventional comparison circuit, the analog input voltages Vin1, V1
in2 needs to approximately satisfy the condition of the following equation (3).

Vin1, Vin2 ≧ 2.2V (3)

When the above equation (1) is not satisfied,
That is, when a low analog voltage that does not satisfy the above equation (3) is input, the transistor Q16 is saturated, and the operating current of the preamplifier 2 is not constant.

For this reason, as shown in FIG. 5, analog inputs Vin1 and Vin2 are added to the conventional comparison circuit shown in FIG.
When a small difference voltage near 1.8 V is input (see FIG. 5A), the outputs Vout1 and Vo of the comparison circuit are output.
ut2 (see FIG. 5B) does not correspond to the analog input.

Accordingly, the present invention has been made in view of the above circumstances, and has as its object to output a normal comparison result at a high clock frequency with respect to a small analog input at a low voltage level. To provide a comparison circuit.

[0024]

In order to achieve the above object, a comparison circuit according to the present invention comprises a preamplifier having a differential pair having an output of an emitter follower having an input as an analog input signal to be compared and having an input as an output. A circuit that receives an output of the preamplifier as an input under the control of a clock signal, amplifies the output and outputs it to an output terminal, and then controls the output level to be latched in accordance with the inversion of the clock signal;
Wherein an N-channel MOS transistor is provided as a constant current source of the differential pair of the preamplifier.

In the present invention, the N-channel MOS
The W / L (channel width / channel length) ratio of the transistor is set to a predetermined value.

[0026]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below. In a preferred embodiment of the comparison circuit according to the present invention, referring to FIG. 1, an emitter follower 1, a preamplifier 2, a strobe comparison circuit 3
And the emitter follower 1 has a collector of the first type.
A first transistor Q connected to a power supply and a base connected to the first and second analog input terminals, respectively;
1 and Q2, the collectors of which are connected to the emitters of the first and second transistors Q1 and Q2, the base is connected to the first bias power supply Vb1, and the emitters are connected at one end to the second power supply Vcc2. 1, the second resistor R
1, and third and fourth transistors Q3 and Q4 connected to the other ends of R2.

The preamplifier 2 has a first power supply Vcc1
And a collector load circuit 4 having first and second preamplifier outputs, and a collector connected to the collector load circuit 4 and a base connected to the first and second transistors Q1 and Q2 of the emitter follower circuit, respectively. Fifth and sixth bipolar transistors Q5 and Q6 connected to the emitter, the emitters being connected in common, the drain is connected to the commonly connected emitters of the fifth and sixth transistors Q5 and Q6, and the gate is connected to the 2 bias power supply Vb2,
N-channel MO whose source is connected to the second power supply Vcc2
And an S transistor MN1.

The strobe comparator 3 has a collector connected to the other ends of the fourth and third resistors R4 and R3, one ends of which are connected to the first power supply Vcc1, respectively.
The seventh and eighth transistors Q7 and Q8 whose bases are connected to the first and second preamplifier outputs, the emitters are connected in common, and the collectors are respectively connected to the first and second digital output terminals Vout1 and Vout2. Ninth and tenth transistors Q9 and Q10 connected to the second digital output terminals Vout1 and Vout2, the bases are connected to the second and first digital output terminals Vout2 and Vout1, respectively, and the emitters are commonly connected;
Collectors are respectively connected to the emitters of the seventh and eighth transistors and emitters of the ninth and tenth transistors, and the bases are connected to the first and second clock signal terminals C, respectively.
LK, CLKB, and eleventh and twelfth transistors Q11 and Q12, whose emitters are connected in common,
The first and second transistors Q11 and Q12 are configured to include a constant current source connected between the emitters of the transistors Q11 and Q12 and the second power supply Vcc2.

In the embodiment of the present invention, the N-channel MOS transistor of preamplifier 2 has its W / L
The ratio of (channel width / channel length) is preferably about 50 to
100.

[0030]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of the present invention; FIG. 1 is a diagram showing a configuration of a comparison circuit according to one embodiment of the present invention.

Referring to FIG. 1, a comparison circuit according to the present embodiment includes an emitter follower 1 having an analog input signal as input, a preamplifier 2 having an output of emitter follower 1 as a differential input, and a preamplifier 2 And a strobe comparator 3 for inputting the differential output of
Analog input voltages Vin1 and Vin2 are input to the base, NPN transistors Q1 and Q2 whose collectors are connected to power supply Vcc1, and bias power supply voltage Vb1 is connected to the base.
And NPN transistors Q3 and Q4 whose emitters are connected to one ends of resistors R1 and R2, respectively.

The preamplifier 2 has an NPN base.
The resistors R5 and R5 are connected to the emitters of the transistors Q1 and Q2, respectively.
NPN transistors Q5 and Q6 each connected to one end of R6 and having a common emitter connected to form a differential pair;
An N-channel MOS transistor MN1 having a gate supplied with a bias power supply voltage Vb2, a drain connected to a common emitter of the NPN transistors Q5 and Q6, and a source connected to the power supply Vcc2.

The strobe comparator 3 has an NPN transistor having a base connected to the differential output of the preamplifier, a collector connected to one end of each of resistors R3 and R4 connected to the power supply Vcc1, and an emitter connected in common. Q7 and Q8 and collectors are resistors R3 and R, respectively.
4 and the bases are respectively connected to resistors R4 and R3.
Q9, Q9, which are connected to one end of
10 and the first and second clock signals CL at the base, respectively.
K and CLKB are applied, and the collectors are respectively connected to the common emitters of the NPN transistors Q8 and Q9, the common emitters of the NPN transistors Q9 and Q10, and the NPN transistors Q11 and Q12 whose emitters are commonly connected.
And a constant current source 5 formed by Q15 having a base supplied with a bias power supply voltage Vb1 and an emitter connected to one end of a resistor R8.

Next, the features of the comparison circuit according to the embodiment of the present invention will be described with reference to FIG. In the comparison circuit of FIG. 1, Vbe is a voltage between the base and the emitter of the bipolar transistor, and VIM is a voltage required for a constant current source of the preamplifier 2 composed of a MOSFET. By using an NMOSFET having a large W / L ratio (channel width / channel length ratio) as the constant current source transistor MN1, a saturated state can be maintained even at a low drain-source voltage.

For this reason, in this embodiment, for example, VIM <0.6V (4) can be satisfied, and the analog input voltage can be reduced to Vin1, Vin2 <2.2V (5). It is.

Although it depends on the process, for example, 50 to 1
By using a MOSFET having a large W / L ratio of 00,
VIM can be reduced to about 0.2 V. In this embodiment, even when a small difference voltage of, for example, about 1.8 V is input, the above-described conventional comparison circuit (see FIG. 3)
Unlike in FIG. 5, the operating current of the preamplifier 2 is kept constant.
As shown in (C), the comparison circuit outputs Vout1, Vout
As t2, a normal comparison result corresponding to the analog input is output.

Further, instead of the constant current source transistor Q15 of the strobe comparator 3, an N-channel MOS transistor to which a predetermined gate bias voltage is applied may be used.

In the above embodiment shown in FIG. 1, an example is shown in which the collector load circuit 4 is constituted by two resistors R5 and R6, but in another embodiment, as shown in FIG.
The collector load circuit 4 may be constituted by a pair of cascode connection transistors and three resistors in order to enable a wide band input.

That is, referring to FIG.
Collector load circuit 4 includes three resistors R5, R6, R7
And two transistors Q13 and Q14. The two transistors Q13 and Q14 have their collectors connected to the other ends of two resistors R5 and R6 each having one end connected to the power supply Vcc1. Second
Is connected to the preamplifier output of the
The common is connected to the other end of the resistor R7 connected to cc1, and the emitters are connected to the collectors of the fifth and sixth transistors Q5 and Q6, respectively.

Since the lower limit of the analog input of the comparison circuit in the embodiment shown in FIG. 2 is the same as that of the above embodiment shown in FIG. 1, the description of the configuration and operation will be omitted.

[0041]

As described above, according to the comparison circuit according to the present invention, since the constant current source of the preamplifier is constituted by the MOSFET having a large W / L ratio, a small analog input at a low voltage level can be obtained. Thus, a normal comparison result can be output at a high clock frequency.

[Brief description of the drawings]

FIG. 1 is a diagram showing a circuit configuration of an embodiment of the present invention.

FIG. 2 is a diagram showing a circuit configuration of another embodiment of the present invention.

FIG. 3 is a diagram showing a circuit configuration of a conventional comparison circuit.

FIG. 4 is a diagram showing operation waveforms of a conventional comparison circuit.

FIG. 5 is a diagram showing a comparison between operation waveforms of a conventional circuit and an embodiment of the present invention.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 Emitter follower 2 Preamplifier 3 Strobe comparator 4 Collector load circuit 5 Constant current source CLK First clock signal CLKB Second clock signal MN1 N-type MOS transistor Q1 to Q16 npn bipolar transistor R1 to R7 Resistance Vb1, Vb2 Bias power supply voltage Terminal Vbe Base-emitter voltage Vcc1, Vcc2 Power supply voltage terminal Vin1, Vin2 Analog input voltage Vout1, Vout2 Digital output voltage VIb Voltage required for constant current source composed of bipolar transistor VIM For constant current source composed of MOS transistor Required voltage

Claims (8)

[Claims] 1. A preamplifier having a differential pair having an output of an emitter follower having an analog input signal to be compared as an input and an output of the preamplifier having an output under the control of a clock signal. A circuit for amplifying and outputting the amplified signal to an output terminal, and then controlling the output level to be latched in accordance with the inversion of the clock signal. An N-channel as a constant current source of a differential pair of the preamplifier M
A comparison circuit comprising an OS transistor. 2. The comparison circuit according to claim 1, wherein said N-channel MOS transistor has a W / L (channel width / channel length) ratio set to a predetermined value. 3. A first and second transistor having a collector connected to the first power supply and a base connected to the first and second analog input terminals, respectively, and a collector having the first and second transistors, respectively. Connected to the emitter, the base is connected to the first bias power supply,
A first in which the emitters are each connected at one end to a second power supply;
An emitter-follower circuit including third and fourth transistors connected to the other end of the second resistor; and the preamplifier is connected to a first power supply, and outputs the first and second preamplifier outputs. A collector load circuit having the collector connected to the load circuit, a base connected to the emitters of the first and second transistors of the emitter follower circuit, and an emitter commonly connected to the fifth and sixth transistors, respectively. A bipolar transistor, an N-channel transistor having a drain connected to the commonly connected emitters of the fifth and sixth transistors, a gate connected to the second bias power supply, and a source connected to the second power supply;
A preamplifier comprising an S transistor; and a collector connected to the other ends of the third and fourth resistors each having one end connected to the first power supply, and
And a seventh and an eighth transistor, whose bases are connected to the first and second preamplifier outputs, and whose emitters are connected in common, and whose collectors are the first and second digital outputs, respectively. Ninth and tenth transistors, each having a base connected to the second and first digital output terminals and having an emitter connected in common, and a collector connected to the emitters of the seventh and eighth transistors, respectively. Eleventh and twelfth transistors connected to the emitters of the ninth and tenth transistors, the bases are connected to the first and second clock signal terminals, respectively, and the emitters are connected in common; A strobe comparison circuit comprising: a constant current source connected between the emitter of the twelfth transistor and the second power supply; Comparison circuit. 4. The comparison circuit according to claim 1, wherein said N-channel MOS transistor of said preamplifier has a W / L (channel width / channel length) ratio of approximately 50 to 100. 5. The collector load circuit of the preamplifier has one end connected to a first power supply, the other end connected to the collectors of the fifth and sixth transistors, respectively, and the first and second preamplifier outputs. The comparison circuit according to claim 3, wherein the comparison circuit is configured by two resistors connected to the comparator. 6. A preamplifier having a collector load circuit comprising:
The two transistors have collectors connected to the other ends of the two resistors each having one end connected to the first power supply, and connected to the first and second preamplifier outputs. 5. The device according to claim 3, wherein one end of the base is commonly connected to the other end of the resistor connected to the first power supply, and the emitter is connected to the collectors of the fifth and sixth transistors. Comparison circuit. 7. The constant current source of the strobe comparator has a drain connected to a commonly connected emitter of the eleventh and twelfth transistors, a gate connected to a third bias power supply, and a source connected to a second bias power supply. 7. The comparison circuit according to claim 5, wherein the comparison circuit is formed by an N-channel MOS transistor connected to a power supply. 8. A constant current source of the strobe comparator is formed by a resistor and a bipolar transistor, and a collector of the NPN transistor is connected to the eleventh and the first.
And the base is connected to the first
The comparison circuit according to claim 4, wherein the comparator is connected to a bias power supply, and one end of the emitter is connected to the other end of the resistor connected to the second power supply.