KR101304417B1 - Liquid crystal display - Google Patents

Abstract

The present invention relates to a liquid crystal display device. A liquid crystal display device according to an exemplary embodiment of the present invention is a liquid crystal display device including a plurality of pixels arranged in a matrix, the liquid crystal display device being formed on a first substrate and the first substrate and transmitting a gate signal to the pixels. A gate line, and a plurality of data sets intersecting the gate line and including a first data line, a second data line, a third data line, and a fourth data line, respectively; Is connected.

quaterG4D, PLS, IPS, FFS, SPVA, OCB, TN

Description

[0001] LIQUID CRYSTAL DISPLAY [0002]

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

2 is an equivalent circuit diagram of a pixel of a liquid crystal display according to an embodiment of the present invention.

3 is a diagram illustrating a spatial arrangement of pixels and signal lines of a liquid crystal display according to an exemplary embodiment of the present invention.

4 is a layout view showing one pixel and a signal line of a liquid crystal panel assembly according to an exemplary embodiment of the present invention.

5 and 6 are cross-sectional views of the liquid crystal panel assembly shown in FIG. 4 taken along the lines V-V and VI-VI.

7 is a layout view illustrating other pixels and signal lines of a liquid crystal panel assembly according to an exemplary embodiment of the present invention.

FIG. 8 is a cross-sectional view of the liquid crystal panel assembly of FIG. 7 taken along the line VII-VII. FIG.

9 is a layout view of a liquid crystal panel assembly according to another exemplary embodiment of the present invention.

FIG. 10 is a cross-sectional view of the liquid crystal panel assembly of FIG. 9 taken along the line VII-VII. FIG.

11 is a diagram illustrating an alignment state of liquid crystals before voltage is applied to the liquid crystal display according to another exemplary embodiment of the present invention.

12 illustrates an alignment state of liquid crystals after applying a predetermined voltage to a liquid crystal display according to another exemplary embodiment of the present invention.

13 is a layout view of a liquid crystal panel assembly according to another exemplary embodiment of the present invention.

FIG. 14 is a cross-sectional view of the liquid crystal panel assembly illustrated in FIG. 13 taken along the line IV-XIV.

15 is an equivalent circuit diagram of one pixel of a liquid crystal display according to another exemplary embodiment of the present invention.

16 is a layout view illustrating two pixels and a signal line of a liquid crystal panel assembly according to another exemplary embodiment of the present invention.

FIG. 17 is a cross-sectional view of the liquid crystal panel assembly illustrated in FIG. 16 taken along a line VII-VII.

18A and 18B are waveform diagrams showing pixel electrode voltages of the liquid crystal panel assembly shown in FIG. 16 together with sustain electrode voltages;

≪ Description of reference numerals &

12, 22: polarizing plates 11, 21: alignment film

81, 82c-f: contact auxiliary member

110, 210: substrate

121: gate line 124: gate electrode

131, 131u, 131d, and 131l: sustain electrode wire

137, 137u, 137d: sustain electrode

140: gate insulating film 154: semiconductor

163 and 165: ohmic contact member

171c-f: data line

173: source electrode

175, 175a, 175b, 177, 177a, 177b: drain electrode

180: shield

181, 182, 182c-f, 183, 185a, 185b, 187, 188: contact hole

191, 191a, and 191b: pixel electrodes

220: light blocking member 230: color filter

250: overcoat 270: common electrode

300: liquid crystal panel assembly 400: gate driver

500: Data driver 600: Signal controller

700: sustain electrode driver 800: gray voltage generator

The present invention relates to a liquid crystal display device.

The liquid crystal display is one of the most widely used flat panel display devices. The liquid crystal display includes two display panels on which an electric field generating electrode such as a pixel electrode and a common electrode are formed, and a liquid crystal layer interposed therebetween. Is applied to generate an electric field in the liquid crystal layer, thereby determining the orientation of the liquid crystal molecules of the liquid crystal layer and controlling the polarization of incident light to display an image.

The liquid crystal display device further includes a switching element connected to each pixel electrode, and a plurality of signal lines such as a gate line and a data line for controlling the switching element to apply a voltage to the pixel electrode.

As the liquid crystal display device is widely used not only as a display device of a computer but also as a display screen such as a television, a need for displaying a moving image is increasing. However, since the response speed of the liquid crystal is slow in the liquid crystal display device, it is difficult to display the moving image. Therefore, a liquid crystal display device that drives faster than a conventional driving speed has been developed.

As the size of the liquid crystal display increases, the number of pixels, gate lines, and data lines increases. Since the charging time of one pixel is inversely proportional to the total number of gates, as the number of gate lines increases, the charging time of the pixels is shortened. In addition, it is difficult to secure a sufficient charging time of the pixel in the liquid crystal display device with high speed driving.

On the other hand, in a liquid crystal display, parasitic capacitance is generated between data lines of pixel electrodes. The parasitic capacitance affects the pixel electrode voltage. In particular, when the low gray voltage is applied, the luminance is changed by changing the subpixel electrode voltage to which the high voltage of the subpixel is applied. As a result, vertical cross talk occurs, and the vertical cross talk serves to deteriorate the quality of the liquid crystal display.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a liquid crystal display device capable of securing a sufficient charging time even when high speed driving is performed in a large area liquid crystal display device.

Another object of the present invention is to prevent vertical crosstalk from occurring in the liquid crystal display.

Another object of the present invention is to efficiently arrange signal lines of a liquid crystal display.

A liquid crystal display device according to an exemplary embodiment of the present invention is a liquid crystal display device including a plurality of pixels arranged in a matrix, the liquid crystal display device being formed on a first substrate and the first substrate and transmitting a gate signal to the pixels. A gate line, and a plurality of data sets intersecting the gate line and including a first data line, a second data line, a third data line, and a fourth data line, respectively; Is connected.

The first and second data lines may be disposed on the left side of the pixel, and the third and fourth data lines may be disposed on the right side of the pixel.

The first data line may be disposed outside the second data line based on the pixel, and the fourth data line may be disposed outside the third data line based on the pixel.

The pixel may include a plurality of pixel electrodes formed on the first substrate, and a plurality of switching elements connected to the pixel electrode, the gate line, and the first to fourth data lines, respectively.

The switching elements of the neighboring pixels in the column direction may be connected to different data lines.

The switching element of the pixel of the i th row and the switching element of the pixel of the i + 1 th row may be connected to different data lines of the second data line and the third data line.

The switching element of the pixel of the i + 2 th row and the switching element of the pixel of the i + 3 th row may be connected to different data lines of the first data line and the fourth data line.

The switching elements of pixels neighboring in the column direction may be connected to data lines disposed opposite to each other with respect to the pixels.

The switching elements of pixels neighboring in the row direction may be connected to different data lines.

The switching elements of pixels neighboring in the row direction may be connected to data lines disposed opposite to each other with respect to the pixel.

Polarities of the data voltages applied to the first and second data lines may be the same, and polarities of the data voltages applied to the third and fourth data lines may be the same.

Polarities of the data voltages applied to the first and second data lines and polarities of the data voltages applied to the third and fourth data lines may be opposite to each other.

Voltage polarities of the pixel electrodes neighboring in the column direction or the row direction may be opposite to each other.

At least one of the first and second data lines may overlap the pixel electrode, and at least one of the third and fourth data lines may overlap the pixel electrode.

The pixel electrode may include two pairs of peripheral edges parallel to each other.

The liquid crystal layer may further include a second substrate facing the first substrate, a common electrode formed on the second substrate, and a liquid crystal layer interposed between the pixel electrode and the common electrode. In the non-formed state, the long axis may be arranged in parallel with the first and second substrates.

Each of the switching elements may include a gate electrode, a source electrode, and a drain electrode, and the drain electrode may be electrically connected to each of the first to fourth data lines through a connection member.

The planar areas of the four connection members connecting each of the first to fourth data lines and the drain electrode may be substantially the same.

And a passivation layer formed between the data line group and the pixel electrode, wherein the passivation layer includes a plurality of first contact holes exposing each of the first to fourth data lines and a second contact hole exposing the drain electrode. The connection member may connect the first to fourth data lines with the drain electrode through the first and second contact holes.

The passivation layer may include an organic insulating material.

The display device may further include a storage electrode overlapping the pixel electrode.

The pixel electrode may further include first and second subpixel electrodes that are separated from each other.

An area of the first subpixel electrode may be smaller than an area of the second subpixel electrode.

The switching element may include a first switching element connected to the first subpixel electrode and a second switching element connected to the second subpixel electrode.

The first and second switching devices may be connected to the same gate line and data line.

A first storage electrode line receiving a periodic signal, a second storage electrode line receiving a periodic signal different from the first storage electrode line, and a third storage electrode line receiving a constant voltage, wherein the first subpixel electrode is formed in the The second subpixel electrode may overlap the first or second storage electrode line, and the second subpixel electrode may overlap the third storage electrode line.

The phases of the signals applied to the first storage electrode line and the second storage electrode line may be reversed.

The voltage of the first subpixel electrode and the voltage of the second subpixel electrode may be different from each other.

The voltage of the first subpixel electrode may be higher than the voltage of the second subpixel electrode.

At least one of the first and second data lines may overlap the second subpixel electrode, and at least one of the third and fourth data lines may overlap the second subpixel electrode.

At least one of the first and second subpixel electrodes may have a first oblique direction determining member.

The first radial direction determining member may include an incision.

A second substrate facing the first substrate, a common electrode formed on the second substrate, and a liquid crystal layer interposed between the pixel electrode and the common electrode, wherein the common electrode has a second inclined direction determining member; It may include.

The second inclination direction determining member may include a cutout or a protrusion.

The liquid crystal molecules constituting the liquid crystal layer may have their long axes perpendicular to the first and second substrates without an electric field being formed.

The display device may further include a common electrode formed on the first substrate and facing the pixel electrode.

The pixel electrode may include a plurality of cutouts that form an oblique angle with the gate line.

The display device may further include an inorganic insulating layer formed between the pixel electrode and the common electrode.

A liquid crystal display according to another exemplary embodiment of the present invention is a liquid crystal display including a plurality of pixels, and includes a plurality of gate lines for transmitting a gate signal to the pixels, and intersects with the gate lines, and includes a first data line and a first data line. And a data line group including a second data line, a third data line, and a fourth data line, wherein each pixel includes: first and second liquid crystal capacitors, first terminals connected to the first liquid crystal capacitors, and a first terminal; A first sustain capacitor having a first terminal to receive a first sustain electrode signal or a second sustain electrode signal opposite in phase to the first sustain electrode signal, a first terminal connected to the second liquid crystal capacitor, and a constant voltage; And a second storage capacitor, each having a second terminal to which is applied, four neighboring gate lines are electrically connected to each other.

Each pixel includes a first switching element connected to the gate line, the data line group, the first liquid crystal capacitor, and the first storage capacitor, and the gate line, the data line group, the second liquid crystal capacitor, and the second liquid crystal capacitor. The display device may further include a second switching device connected to the storage capacitor.

The first liquid crystal capacitor may include a first subpixel electrode and a common electrode, and the second liquid crystal capacitor may include a second subpixel electrode and a common electrode.

An area of the second subpixel electrode may be larger than an area of the first subpixel electrode.

The liquid crystal layer may further include a second substrate facing the first substrate, a common electrode formed on the second substrate, and a liquid crystal layer interposed between the pixel electrode and the common electrode. It may be splay oriented in a non-formed state, and bend oriented in an electric field.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein.

In the drawings, the thickness is enlarged to clearly represent the layers and regions. Like parts are designated with like reference numerals throughout the specification. It will be understood that when an element such as a layer, film, region, plate, or the like is referred to as being "on" another portion, it includes not only the element directly over another element, Conversely, when a part is "directly over" another part, it means that there is no other part in the middle.

A liquid crystal display according to an embodiment of the present invention will now be described with reference to FIGS. 1 and 2. FIG.

1 is a block diagram of a liquid crystal display according to an embodiment of the present invention, FIG. 2 is an equivalent circuit diagram of one pixel of a liquid crystal display according to an embodiment of the present invention, and FIG. 3 is an embodiment of the present invention. It is a figure which shows the spatial arrangement of the pixel and signal line of the liquid crystal display device which concerns on an example.

1 and 2, a liquid crystal display according to an exemplary embodiment of the present invention includes a liquid crystal panel assembly 300, a pair of gate drivers 400a and 400b and a data driver connected thereto. 500, a gray voltage generator 800 connected to the data driver 500, and a signal controller 600 for controlling the gray voltage generator 800.

The liquid crystal panel assembly 300 includes a plurality of signal lines G _i , G _{i + 1} , and D _j and a plurality of pixels PX connected to the plurality of signal lines G _i , G _{i + 1} , and D _j , and arranged in a substantially matrix form. do. 2, the liquid crystal display panel assembly 300 includes lower and upper display panels 100 and 200 facing each other and a liquid crystal layer 3 interposed therebetween.

First, referring to FIGS. 1 and 2, the signal lines G _i , G _{i + 1} , and D _j are a plurality of gate lines G _i , G _{i + 1} for transmitting a gate signal (also called a “scan signal”). And a plurality of data lines D _j for transmitting data signals. The gate lines G _i and G _{i + 1} extend substantially in the row direction and are substantially parallel to each other, and the data lines D _j extend substantially in the column direction and are substantially parallel to each other.

Each pixel PX includes a switching element Q connected to signal lines G _i and D _j , a liquid crystal capacitor Clc, and a storage capacitor Cst connected thereto. The storage capacitor Cst can be omitted if necessary.

The switching element Q is a three terminal element such as a thin film transistor provided in the lower panel 100. The control terminal is connected to the gate line G _i and the input terminal is connected to the data line D _j And the output terminal is connected to the liquid crystal capacitor Clc and the storage capacitor Cst.

The liquid crystal capacitor Clc has two terminals, the pixel electrode 191 of the lower panel 100 and the common electrode 270 of the upper panel 200, and the liquid crystal layer 3 between the two electrodes 191 and 270 is a dielectric material. Function as. The pixel electrode 191 is connected to the switching element Q and the common electrode 270 is formed on the entire surface of the upper panel 200 to receive the common voltage Vcom. 2, the common electrode 270 may be provided on the lower panel 100. At this time, at least one of the two electrodes 191 and 270 may be linear or bar-shaped.

The storage capacitor Cst serving as an auxiliary capacitor of the liquid crystal capacitor Clc is formed by superimposing a separate signal line (not shown) and a pixel electrode 191 provided on the lower panel 100 with an insulator interposed therebetween, A predetermined voltage such as the common voltage Vcom is applied to the separate signal lines. However, the storage capacitor Cst may be formed such that the pixel electrode 191 overlaps the front gate line G _i-1 directly above the insulator.

Referring to FIG. 3, the liquid crystal panel assembly 300 of the present invention includes a plurality of pixels PX arranged in a matrix. Each pixel PX includes a pixel electrode PE and a switching element Q connected to the pixel electrode PE. A plurality of gate lines G ₁ , G ₂ , G ₃ , and G ₄ extending in the horizontal direction are arranged between each pixel row row, and a plurality of pairs extending in the vertical direction on the left and right sides of the pixel PX. Data lines (D _1c , D _1d , D _1e , D _1f , D _2c , D _2d , D _2e , D _2f , D _3c , D _3d , D _3e , D _3f , D _4c , D _4d , D _4e , D _4f , ... D _mc , D _md , D _me , D _mf ) are arranged. The switching element Q is connected to the gate lines G ₁ -G _n and the data lines D ₁ -D _md .

Referring to the pixel PX of the first column of the first row, one gate line G ₁ and four data lines D _1c , D _1d , D _1e , and D _1f are disposed per pixel PX. It is. Hereinafter, four data lines D _1c , D _1d , D _1e , and D _1f are sequentially disposed from the left to the first data line D _1c , the second data line D _1d , the third data line D _1e , and This is called a fourth data line D _1f .

The first and second data lines D _1c and D _1d are disposed on the left side with respect to the pixel PX, and the first data line D _1c is disposed outside the second data line D _1d . have. The third and fourth data lines D _1e and D _1f are disposed on the right side with respect to the pixel PX, and the fourth data line D _1f is disposed outside the third data line D _1d . have.

The switching elements Q of the pixels PX arranged in the first row and the first row are connected to the second data line D _1d , and the pixels arranged in the first column and the second row ( The switching element Q of the PX is connected to the third data line D _1e , and the switching element Q of the pixel PX disposed in the first column and the third row is the first data line. _1c are connected to D), the switching device (Q) of the first heat ?? pixels (PX) arranged in the fourth row are connected to a fourth data lines (D _1f). That is, the switching elements Q of the pixels PX neighboring each other in the column direction are arranged on different data lines D _1c , D _1d , D _1e , and D _1f arranged in different directions with respect to the pixels PX. It is connected.

The switching elements Q of the pixels PX neighboring in the row direction also have different data lines D _1c-1f , D _2c-2f , D _3c-3f , which are arranged in different directions with respect to the pixel PX. D _4c-4f ,… D _mc-mf ).

Four neighboring gate lines G ₁ , G ₂ , G ₃ , and G ₄ are connected to each other and receive the same gate signal.

The polarity of the data voltage flowing through the data lines D _1c-1f , D _2c-2f , D _3c-3f , D _4c-4f , ... D _mc-mf on the left and right sides of one pixel PX The opposite of each other. That is, the data voltage flowing to the data lines D _1c , D _1d , D _2c , D _2d , D _3c , D _3d , D _4c , D _4d ,..., D _mc , and D _md positioned on the left side of the pixel PX. The polarity of is positive (+) and flows to the data lines (D _1e , D _1f , D _2e , D _2f , D _3e , D _3f , D _4e , D _4f ,… D _me , D _mf ) located on the right side. The polarity of the data voltage is negative.

Accordingly, the polarities of the pixels PX neighboring in the row direction are opposite to each other, and the polarities of the pixels PX neighboring in the column direction are also opposite to each other.

On the other hand, in order to implement color display, each pixel PX uniquely displays one of primary colors (space division), or each pixel PX alternately displays a basic color (time division) So that the desired color is recognized by the spatial and temporal sum of these basic colors. Examples of basic colors include red, green, and blue. 2 shows that each pixel PX has a color filter 230 that indicates one of the basic colors in an area of the upper panel 200 corresponding to the pixel electrode 191 . 2, the color filter 230 may be formed on or below the pixel electrode 191 of the lower panel 100. [

At least one polarizer (not shown) for polarizing light is attached to the outer surface of the liquid crystal panel assembly 300.

Referring again to FIG. 1, the gradation voltage generator 800 generates the total gradation voltage related to the transmittance of the pixel PX or a limited number of gradation voltages (hereinafter referred to as "reference gradation voltage"). The reference gray level voltage may include a positive value and a negative value with respect to the common voltage Vcom.

The gate driver 400 is connected to the gate lines G ₁ -G _n of the liquid crystal panel assembly 300 and supplies a gate signal composed of a combination of the gate-on voltage Von and the gate-off voltage Voff to the gate line G ₁ -G _n .

Data driver 500 is connected with the data lines (D ₁ -D _m) of the liquid crystal panel assembly 300, select a gray voltage from the gray voltage generator 800 and the data lines do this as a data voltage (D ₁ -D _md ). However, when the gradation voltage generator 800 does not provide all of the gradation voltages but only provides a limited number of reference gradation voltages, the data driver 500 divides the reference gradation voltage to select a desired data voltage.

The signal controller 600 controls the gate driver 400, the data driver 500, and the like.

Each of the driving devices 400, 500, 600, and 800 may be directly mounted on the liquid crystal panel assembly 300 in the form of at least one integrated circuit chip, or may be a flexible printed circuit film (not shown) Or may be attached to the liquid crystal panel assembly 300 in the form of a tape carrier package (TCP), or may be mounted on a separate printed circuit board (not shown). Alternatively, these driving devices 400, 500, 600, and 800 may be integrated in the liquid crystal panel assembly 300 together with the signal lines G ₁ -G _n , D ₁ -D _md and the thin film transistor switching element Q. It may be. In addition, the drivers 400, 500, 600, 800 may be integrated into a single chip, in which case at least one of them, or at least one circuit element constituting them, may be outside of a single chip.

4 to 7, a liquid crystal panel assembly according to an embodiment of the present invention will be described in detail.

FIG. 4 is a layout view of one pixel and a signal line of a liquid crystal panel assembly according to an exemplary embodiment of the present invention, and FIGS. 5 and 6 are cut along the lines V-V and VI-VI, respectively. 7 is a layout view of another pixel and a signal line of a liquid crystal panel assembly according to an exemplary embodiment of the present invention.

First, the shapes of the pixels and the signal lines arranged in the first column of the first row will be described in detail with reference to FIGS. 4 to 6.

The lower panel 100 will be described.

A plurality of gate lines 121 and a plurality of storage electrode lines 131 are formed on an insulating substrate 110 made of transparent glass or plastic.

The gate line 121 transmits the gate signal and extends mainly in the horizontal direction. Each gate line 121 includes a plurality of gate electrodes 124 protruding up and down and a wide end portion 129 for connection with another layer or an external driving circuit. When the gate driving circuit is integrated on the substrate 110, the gate line 121 may extend and be directly connected thereto.

The storage electrode line 131 receives a predetermined voltage and almost extends in parallel with the gate line 121. Each storage electrode line 131 is positioned between two adjacent gate lines 121 and is close to a lower side of the two gate lines 121. The storage electrode line 131 includes a storage electrode 137 extending up and down. However, the shape and arrangement of the sustain electrode lines 131 can be variously modified.

The gate line 121 and the storage electrode line 131 may be formed of a metal such as aluminum (Al) or an aluminum alloy, a metal such as silver (Ag) or silver alloy, a copper metal such as copper or copper alloy, Such as molybdenum metal, chromium (Cr), tantalum (Ta), and titanium (Ti), such as molybdenum (Mo) or molybdenum alloy. However, they may have a multi-film structure including two conductive films (not shown) having different physical properties. One of the conductive films is made of a metal having low resistivity, such as aluminum-based metal, silver-based metal, or copper-based metal, so as to reduce signal delay or voltage drop. Alternatively, the other conductive film is made of a material having excellent physical, chemical and electrical contact properties with other materials, particularly indium tin oxide (ITO) and indium zinc oxide (IZO), such as molybdenum metal, chromium, tantalum and titanium. A good example of such a combination is a chromium bottom film, an aluminum (alloy) top film, an aluminum (alloy) bottom film and a molybdenum (alloy) top film. However, the gate line 121 and the sustain electrode line 131 may be made of various other metals or conductors.

Side surfaces of the gate line 121 and the storage electrode line 131 are inclined with respect to the surface of the substrate 110, and the inclination angle is preferably about 30 ° to about 80 °.

A gate insulating layer 140 made of silicon nitride (SiNx) or silicon oxide (SiOx) is formed on the gate line 121 and the storage electrode line 131.

On the gate insulating layer 140, a plurality of island-like semiconductors 154 made of hydrogenated amorphous silicon (amorphous silicon is abbreviated a-Si), polysilicon, or the like are formed. Semiconductor 154 is positioned over gate electrode 124.

On the semiconductor 154, a plurality of island-shaped resistive contact members 163 and 165 are formed. The resistive contact members 163 and 165 may be made of a material such as n + hydrogenated amorphous silicon, or may be made of silicide, which is heavily doped with phosphorous n-type impurities. The ohmic contacts 163 and 165 are paired and disposed on the semiconductor 154.

Side surfaces of the semiconductor 154 and the ohmic contacts 163 and 165 are also inclined with respect to the surface of the substrate 110, and the inclination angle is about 30 ° to 80 °.

Four first, second, third and fourth data lines 171c, 171d, 171e, and 171f and a source electrode are formed on the ohmic contacts 163 and 165 and the gate insulating layer 140. 173 and a drain electrode 175 are formed.

The data lines 171c-f transmit data signals and mainly extend in the vertical direction to cross the gate lines 121 and the storage electrode lines 131. Each data line 171c-f includes end portions 179a, 179b, 179c, and 179d having a large area for connection with another layer or an external driving circuit. When the data driving circuit is integrated on the substrate 110, the data line 171 can extend and be directly connected thereto.

The drain electrode 175 is separated from the data line 171c-f and faces the source electrode 173 with respect to the gate electrode 124. Each drain electrode 175 includes one wide end and the other end having a rod shape. The wide end overlaps the sustain electrode 137, and the rod-shaped end is partially surrounded by the source electrode 173 bent in a U shape.

One gate electrode 124, one source electrode 173 and one drain electrode 175 constitute one thin film transistor (TFT) together with the semiconductor 154, and the channel of the thin film transistor Is formed in the semiconductor 154 between the source electrode 173 and the drain electrode 175. [

The data line 171c-f and the drain electrode 175 are preferably made of a refractory metal such as molybdenum, chromium, tantalum and titanium, or an alloy thereof, and includes a refractory metal film (not shown) and low resistance. It may have a multilayer structure including a conductive film (not shown). Examples of the multilayer structure include a double film of a chromium or molybdenum (alloy) lower film and an aluminum (alloy) upper film, a molybdenum (alloy) lower film, an aluminum (alloy) intermediate film and a molybdenum (alloy) upper film. However, the data line 171c-f and the drain electrode 175 may be made of various metals or conductors.

The side of the data line 171c-f and the drain electrode 175 may also be inclined at an inclination angle of about 30 ° to about 80 ° with respect to the surface of the substrate 110.

The ohmic contacts 163 and 165 exist only between the semiconductor 154 below and the data line 171c-f and the drain electrode 175 thereon, and lower the contact resistance therebetween.

A passivation layer 180 is formed on the data line 171c-f, the drain electrode 175, and the exposed semiconductor 154. The protective film 180 is made of an inorganic insulating material or an organic insulating material and may have a flat surface. Examples of the inorganic insulating material include silicon nitride and silicon oxide. The organic insulating material may have photosensitivity and its dielectric constant is preferably about 4.0 or less. However, the passivation layer 180 may have a double layer structure of the lower inorganic layer and the upper organic layer so as not to damage the exposed portion of the semiconductor 154 while maintaining excellent insulating properties of the organic layer.

The passivation layer 180 has a plurality of contact holes that respectively expose end portions 179a-f of the data lines 171c-f, a source electrode 173, a drain electrode 175, and an intermediate portion of the second data line 171d. (contact holes) 182c, 182d, 182e. 182f, 183, 185, and 187, and the passivation layer 180 and the gate insulating layer 140 expose a plurality of end portions 129 of the gate line 121. The contact hole 181 is formed.

A plurality of pixel electrodes 191, a plurality of contact assistants 81, 82c, 82d, 82e, and 82f, and a connection member 87 are formed on the passivation layer 180. They may be made of a transparent conductive material such as ITO or IZO or a reflective metal such as aluminum, silver, chromium or an alloy thereof.

The pixel electrode 191 is physically and electrically connected to the drain electrode 175 through the contact hole 185 and receives the data voltage from the drain electrode 175. The pixel electrode 191 to which the data voltage is applied is generated between the two electrodes 191 and 270 by generating an electric field together with the common electrode 270 of the other display panel 200 to which the common voltage is applied. Direction of the liquid crystal molecules of the liquid crystal layer 3]. Polarization of light passing through the liquid crystal layer 3 varies depending on the orientation of the liquid crystal molecules thus determined. The pixel electrode 191 and the common electrode 270 form a capacitor (hereinafter, referred to as a "liquid crystal capacitor") to maintain an applied voltage even after the thin film transistor is turned off.

The pixel electrode 191 and the drain electrode 175 connected to the pixel electrode 191 overlap the storage electrode line 131 including the storage electrode 137. A capacitor in which the pixel electrode 191 and the drain electrode 175 electrically connected thereto overlap with the storage electrode line 131 is called a "storage capacitor", and the storage capacitor enhances the voltage holding capability of the liquid crystal capacitor. .

The pixel electrode 191 has a pair of peripheries parallel to each other, and has a substantially rectangular shape.

The pixel electrode 191 overlaps the second and third data lines 171d and 171e. At this time, parasitic capacitance may occur between the pixel electrode 191 and the second and third data lines 171d and 171e. However, as described above, since data voltages having different polarities flow through the second and third data lines 171d and 171e, parasitic capacitances may be formed between the pixel electrode 191 and the second and third data lines 171d and 171e. Each parasitic dose offsets each other even if they occur. Therefore, the opening ratio of the display panel can be improved while preventing vertical crosstalk from occurring.

The contact auxiliary members 81 and 82c-f respectively have an end portion 129 of the gate line 121 and an end portion 179c-f of the data line 171c-f through the contact holes 181 and 182c-f, respectively. Connected with The contact auxiliary members 81 and 82c-f complement and protect the adhesion between the end portion 129 of the gate line 121 and the end portion 179c-f of the data line 171c-f and the external device. do.

The connection member 87 is connected to the source electrode 173 and the second data line 171d through the contact holes 183 and 187. Therefore, the source electrode 173 receives a data voltage through the second data line 171d.

Now, the upper display panel 200 will be described.

A light blocking member 220 is formed on an insulating substrate 210 made of transparent glass or plastic. The light shielding member 220 is also called a black matrix and blocks light leakage. The light blocking member 220 includes a linear portion 221 corresponding to the data lines 171l and 171r and a planar portion corresponding to the thin film transistor, and prevents light leakage between the pixel electrode 191 and faces the pixel electrode 191. An opening area is defined. However, the light shielding member 220 may have a plurality of openings (not shown) facing the pixel electrode 191 and having substantially the same shape as the pixel electrode 191.

A plurality of color filters 230 are further formed on the substrate 210. The color filter 230 is mostly present in a region surrounded by the light shielding member 230 and can be elongated in the longitudinal direction along the column of the pixel electrodes 191. Each color filter 230 may display one of primary colors such as three primary colors of red, green, and blue.

An overcoat 250 is formed on the color filter 230 and the light shielding member 220. The cover film 250 can be made of (organic) insulation and prevents the color filter 230 from being exposed and provides a flat surface. The cover film 250 may be omitted.

A common electrode 270 is formed on the lid 250. The common electrode 270 is made of a transparent conductor such as ITO or IZO.

Alignment layers 11 and 21 are coated on inner surfaces of the display panels 100 and 200 and may be horizontal alignment layers.

Polarizers 12 and 22 are provided on the outer surfaces of the display panels 100 and 200, and the transmission axes of the two polarizers 12 and 22 are orthogonal to each other, and one of the transmission axes is relative to the gate lines 121d and 121u. Side by side is preferred.

The liquid crystal display may include a polarizer 12 and 22, display panels 100 and 200, and a backlight unit (not shown) that supplies light to the liquid crystal layer 3.

The liquid crystal layer 3 has positive dielectric anisotropy, and the liquid crystal molecules of the liquid crystal layer 3 are aligned such that their major axes are horizontal to the surfaces of the two display panels 100 and 200 in the absence of an electric field. Therefore, the incident light is blocked without passing through the orthogonal polarizers 12 and 22.

Referring to FIG. 7, the shapes of the pixels and the signal lines arranged in the first column of the fourth row will be described in detail.

Like the pixels arranged in the first column of the first row, the pixels arranged in the first column of the fourth row also have the lower display panel 100 and the upper display panel 200 facing each other, and the liquid crystal layer 3 interposed between the two display panels. And a pair of polarizers 12 and 22 attached to the outer surfaces of the display panels 100 and 200.

The layered structure of FIG. 7 is usually the same as the layered structure shown in FIGS. 5 and 6.

Referring to the lower panel 100, a plurality of gate conductors including the gate lines 121 are formed on the insulating substrate 110. Each gate line 121 includes a gate electrode 124 and an end portion 129. The gate insulating layer 140 is formed on the gate conductor 121. An island-like semiconductor 154 is formed on the gate insulating layer 140, and a plurality of ohmic contacts 163 and 165 are formed thereon. A data conductor including four data lines 171c-f, a source electrode 173, and a plurality of drain electrodes 175 is formed on the ohmic contacts 163 and 165 and the gate insulating layer 140. The data line 171c-f includes an end portion 179c-f. The passivation layer 180 is formed on the data conductors 171c-f and 175 and the exposed portion of the semiconductor 154, and the contact hole 181, 182c-f, 183, is formed in the passivation layer 180 and the gate insulating layer 140. 185, 188 are formed. The pixel electrode 191, the contact auxiliary members 81 and 82c-f, and the connection member 88 are formed on the passivation layer 180. An alignment layer 11 is formed on the pixel electrode 191, the contact assistants 81 and 82c-f, and the passivation layer 180.

For example, the light blocking member 220, the plurality of color filters 230, the overcoat 250, the common electrode 270, and the alignment layer 21 are formed on the insulating substrate 210.

Unlike the pixel of FIG. 4, the pixel of FIG. 7 is bent to the right of the end of the source electrode 173, and the connection member 88 is connected to the source electrode 173 and the fourth data line 171f. That is, the connection member 88 extends to the fourth data line 171f through the third data line 171e disposed between the source electrode 173 and the fourth data line 171f.

4 and 7, the connecting member 87 of FIG. 4 extends beyond the second data line 171d to the first data line 171c. Therefore, the planar areas of the connecting members 87 and 88 of FIGS. 4 and 7 are substantially the same. Thereby, the optical characteristic of each pixel can be made the same.

Many features of the liquid crystal panel assembly illustrated in FIGS. 4 to 6 may also be applied to the liquid crystal panel assembly illustrated in FIG. 7.

Although not shown in the drawings, the pixels arranged in the first column of the second row and the pixels arranged in the first column of the third row also have a form similar to those of FIGS. 4 and 7, except that the source electrode 173 and the data line 171c are provided. Only the connection relationship of -f) is modified.

A liquid crystal panel assembly according to another exemplary embodiment of the present invention will now be described in detail with reference to FIG. 9.

9 is a layout view illustrating a liquid crystal panel assembly according to another exemplary embodiment of the present invention.

The liquid crystal panel assembly according to the present exemplary embodiment also includes a lower panel 100 and an upper panel 200 facing each other and a liquid crystal layer 3 interposed between the two panels.

The layered structure of the liquid crystal panel assembly according to the present embodiment is usually the same as the layered structure of the liquid crystal panel assembly shown in FIGS. 4 to 6.

Referring to the lower panel, a plurality of gate conductors including the gate lines 121 are formed on the insulating substrate 110. Each gate line 121 includes a gate electrode 124 and an end portion 129. The gate insulating layer 140 is formed on the gate conductor 121. An island-like semiconductor 154 is formed on the gate insulating layer 140, and a plurality of ohmic contacts 163 and 165 are formed thereon. A data conductor including four data lines 171c-f, a source electrode 173, and a plurality of drain electrodes 175 is formed on the ohmic contacts 163 and 165 and the gate insulating layer 140. The data line 171c-f includes an end portion 179c-f. The passivation layer 180 is formed on the data conductors 171c-f and 175 and the exposed semiconductor 154, and the contact holes 181, 182c-f, and 183 are formed in the passivation layer 180 and the gate insulating layer 140. , 185, 188 are formed. The pixel electrode 191, the contact auxiliary members 81 and 82c-f, and the connection member 87 are formed on the passivation layer 180. An alignment layer 11 is formed on the pixel electrode 191, the contact assistants 81 and 82c-f, and the passivation layer 180.

For example, the light blocking member 220, the plurality of color filters 230, the overcoat 250, the common electrode 270, and the alignment layer 21 are formed on the insulating substrate 210.

However, unlike the liquid crystal panel assembly of FIG. 4, in the liquid crystal panel assembly according to the present exemplary embodiment, all data lines 171c-f overlap the pixel electrode 191. Then, the polarities of the data voltages flowing to the data lines 171c, 171d / 171e, and 171f disposed on the opposite side of the data line 171c-f with respect to the pixel PX are opposite to each other, and thus the data lines 171c-f. The parasitic capacitance generated between the pixel electrode 191 and the pixel electrode 191 cancel each other out. Accordingly, the aperture ratio can be further increased while preventing vertical crosstalk from occurring.

The liquid crystal layer 3 of the liquid crystal display according to the present exemplary embodiment includes a nematic liquid crystal having a positive dielectric anisotropy, and is in an initial splay alignment, and is converted into a bend orientation as shown in FIG. 10 by a bend voltage. Is driven for display. The liquid crystal display device having the liquid crystal layer 3 made of the liquid crystal molecules 31 is called an OCB (optically compensated bend) mode, and the liquid crystal display device driven in the OCB mode is normally white, that is, a state in which no voltage is applied. Displays white.

Hereinafter, the OCB mode will be described in detail with reference to FIGS. 11 and 12.

11 is a diagram illustrating an alignment state of the liquid crystal before applying a constant voltage, and FIG. 12 is a diagram illustrating an alignment state of the liquid crystal after applying a bend voltage.

Referring to FIG. 11, in the state in which no voltage is applied, the liquid crystal molecules 31 near the two alignment layers 11 and 21 are horizontally aligned with a pretilt angle θ of which one end faces in the rubbing direction. have. Therefore, the arrangement of the liquid crystal molecules 31 is symmetrical about the plane parallel to the planes of the substrates 110 and 210 and at approximately the same distance from the surfaces of the two alignment layers 11 and 21 (hereinafter referred to as the "center plane"). do. This orientation is called splay orientation.

In this state, when a predetermined voltage, that is, a bend voltage is applied, an electric field is formed in the liquid crystal layer 3, and the liquid crystal molecules 31 are changed from the splay orientation to another orientation.

In more detail, when the voltage is applied to the electrodes (not shown) of the two display panels 100 and 200 and an electric field perpendicular to the surfaces of the two display panels 100 and 200 is generated in the liquid crystal layer 3, the alignment layer The liquid crystal molecules 31 near (11, 21) rise in response to the electric field. However, since the directions in which the surfaces of the two alignment layers 11 and 21 rise are the same, the directions in which the liquid crystal molecules 31 rise in the middle portion of the liquid crystal layer 3 collide with each other to generate a large stress, thereby resulting in an energy stable twist ( transition to twist orientation. This is called a transition splay orientation.

In this state, if the electric field is made stronger, the liquid crystal has a bend orientation as shown in FIG. 12. Such an alignment transition should occur uniformly in the liquid crystal capacitor Clc of the entire liquid crystal panel assembly 300.

Many features of the liquid crystal panel assembly illustrated in FIGS. 4 to 6 may also be applied to the liquid crystal panel assembly illustrated in FIGS. 8 to 10.

Next, a liquid crystal panel assembly according to another exemplary embodiment of the present invention will be described in detail with reference to FIGS. 13 and 14.

13 is a layout view of a liquid crystal panel assembly according to another exemplary embodiment of the present invention, and FIG. 14 is a cross-sectional view of the liquid crystal panel assembly illustrated in FIG. 10 taken along the line IV-XIV.

The liquid crystal panel assembly according to the present exemplary embodiment also has a lower panel 100 and an upper panel 200 facing each other, and an outer surface of the liquid crystal layer 3 and the display panels 100 and 200 interposed between the two display panels 100 and 200. And a pair of polarizers 12 and 22 attached thereto.

The layered structure of the liquid crystal panel assembly according to the present embodiment is usually the same as the layered structure of the liquid crystal panel assembly shown in FIGS. 4 to 6.

Referring to the lower panel 100, the common electrode 270 is formed on the insulating substrate 110. In addition, a plurality of gate conductors including the gate line 121 and the storage electrode line 131 are formed on the insulating substrate 110. Each gate line 121 includes a gate electrode 124 and an end portion 129. The gate insulating layer 140 is formed on the gate conductor 121. An island-like semiconductor 154 is formed on the gate insulating layer 140, and a plurality of ohmic contacts 163 and 165 are formed thereon. A data conductor including four data lines 171c-f, a source electrode 173, and a drain electrode 175 is formed on the ohmic contacts 163 and 165 and the gate insulating layer 140. The data line 171c-f includes an end portion 179c-f. The passivation layer 180 is formed on the data conductors 171c-f and 175 and the exposed portion of the semiconductor 154, and the contact hole 181, 182c-f, 183, is formed in the passivation layer 180 and the gate insulating layer 140. 185 and 187 are formed. The pixel electrode 191, the contact auxiliary members 81 and 82c-f, and the connection member 87 are formed on the passivation layer 180. An alignment layer 11 is formed on the pixel electrode 191, the contact assistants 81 and 82c-f, and the passivation layer 180.

For example, the light blocking member 220, the plurality of color filters 230, the overcoat 250, the common electrode 270, and the alignment layer 21 are formed on the insulating substrate 210.

However, in the liquid crystal panel assembly according to the present exemplary embodiment, unlike the liquid crystal panel assembly of the above-described embodiment, the common electrode 270 is included in the lower panel 100 instead of the upper panel 200. In other words, the common electrode 270 is formed on the insulating substrate 110 of the lower panel 110. The common electrode 270 is made of a transparent conductive material such as ITO and is in contact with the storage electrode line 131, and receives the common voltage Vcom through the storage electrode line 131.

In addition, the passivation layer 180 of the liquid crystal panel assembly according to the present exemplary embodiment is formed of an inorganic layer and is thinner than the passivation layer 180 of the liquid crystal panel assembly described above.

In addition, the pixel electrode 191 according to the present exemplary embodiment is different from the pixel electrode 191 described above. The pixel electrode 191 according to the present exemplary embodiment includes a plurality of cutouts formed between two vertical portions 192a and 192b and two vertical portions 192a and 192b that are substantially parallel to the data lines 171c-f. (193a, 193b). The cutouts 193a and 193b are divided into a first cutout 193a disposed above and a second cutout 193b disposed below the storage electrode line 131. The first cutout 193a forms an acute angle with the storage electrode line 131, and the second cutout 193b forms an obtuse angle with the storage electrode line 131. The first and second cutouts 193a and 193b are substantially symmetrical with respect to the storage electrode line 131.

The electric field generated by the pixel electrode 191 and the common electrode 270 includes both a vertical component perpendicular to the surface of the display panel and a horizontal component parallel to the surface of the display panel and perpendicular to the sides of the cutouts 193a and 193b.

The horizontal component of the electric field rotates the liquid crystal molecules of the liquid crystal layer 3 positioned on the field generating electrodes 270 and 191 on a plane parallel to the surface of the lower panel 100. On the other hand, the vertical component of the electric field tilts these liquid crystal molecules up or down. As such, the polarization of light passing through the liquid crystal layer is changed according to the direction of the liquid crystal molecules determined by the electric field, and the light transmittance is also changed.

In such a liquid crystal display device including the thin film transistor array panel, the long axis of the liquid crystal molecules is dispersed in various directions, so that the reference viewing angle is widened. In addition, since both the horizontal component and the vertical component of the electric field contribute to displaying an image, the aperture ratio and transmittance of the liquid crystal display are very high. In particular, in the case of a transmissive liquid crystal display in which both the common electrode 270 and the pixel electrode 191 are transparent Even more so.

In addition, since only a thin passivation layer 180 of about 2,000 Å is sandwiched between the common electrode 270 and the pixel electrode 191, the gate insulating layer 140 and the passivation layer 180 are disposed between the common electrode 270 and the pixel electrode 191. ), The electric field of the same intensity can be formed in the liquid crystal layer even at a low voltage compared to the case where all of the) are interposed, thereby reducing the cost of the driving integrated circuit.

The pixel electrode 191 and the common electrode 270 form a "liquid crystal capacitor" including a liquid crystal layer as a dielectric and a "storage capacitor" including the protective film 180 as a dielectric. The applied voltage is maintained even after the thin film transistor is turned off.

Many features of the liquid crystal panel assembly shown in FIGS. 4 to 6 may also be applied to the liquid crystal panel assembly shown in FIGS. 13 and 14.

A liquid crystal panel assembly according to another exemplary embodiment of the present invention will now be described in detail with reference to FIGS. 15 to 18B.

15 is an equivalent circuit diagram of one pixel of a liquid crystal panel assembly according to another exemplary embodiment of the present invention.

Referring to FIG. 15, the liquid crystal panel assembly 300 according to the present exemplary embodiment includes the signal lines G, D, and S, and a plurality of pixels PX connected to the signal lines G, D, and S and arranged in a substantially matrix form. In contrast, in the structure shown in FIG. 8, the liquid crystal panel assembly 300 includes lower and upper panels 100 and 200 facing each other and a liquid crystal layer 3 interposed therebetween.

The signal line includes a plurality of gate lines G for transmitting a gate signal (also referred to as a "scan signal") and a plurality of data lines D for transmitting a data signal. The gate lines G extend substantially in the row direction and are substantially parallel to each other, and the data lines D extend substantially in the column direction and are substantially parallel to each other.

The signal line also includes a first storage electrode line S for transmitting the first storage electrode signal and a second storage electrode line (not shown) for transmitting the second storage electrode signal. The phases of the first sustain electrode signal and the second sustain electrode signal are opposite to each other.

Each pixel PX includes first and second subpixels PX1 and PX2, and each of the subpixels PX1 and PX2 includes switching elements Q1 and Q2 and liquid crystal capacitors Clc1 and Clc2. ) And holding capacitors Cst1 and Cst2. The first subpixel PX1 includes a first storage capacitor Cst1, and the second subpixel PX2 includes a second storage capacitor Cst2.

The first and second switching elements Q1 and Q2 include a control terminal connected to the gate line G, an input terminal connected to the data line D, and the liquid crystal capacitors Clc1 and Clc2 and the storage capacitor Cst1. And an output electrode connected to Cst2).

The liquid crystal capacitors Clc1 and Clc2 have two terminals, the subpixel electrodes 191a and 191b of the lower panel 100 and the common electrode 270 of the upper panel 200, and the subpixel electrodes 191a and 191b and the common electrode. The liquid crystal layer 3 between 270 functions as a dielectric. The pair of subpixel electrodes 191a and 191b are separated from each other and form one pixel electrode 191. The common electrode 270 is formed on the front surface of the upper panel 200 and receives the common voltage Vcom. The liquid crystal layer 3 has negative dielectric anisotropy, and the liquid crystal molecules of the liquid crystal layer 3 may be aligned such that their major axes are perpendicular to the surfaces of the two display panels 100 and 200 in the absence of an electric field.

The storage capacitor Cst1 of the first subpixel PX1 is connected to the switching element Q1 and the first storage electrode line S, and the storage capacitor Cst2 of the second subpixel PX2 is a switching element ( It is connected to a signal line (not shown) separate from Q2).

Now, the liquid crystal panel assembly illustrated in FIG. 15 will be described in more detail with reference to FIGS. 16 and 17.

FIG. 16 is a layout view of a liquid crystal panel assembly according to another exemplary embodiment of the present invention, and FIG. 17 is a cross-sectional view of the liquid crystal panel assembly illustrated in FIG. 16 taken along the line VII-VII.

As shown in FIG. 16 and FIG. 17, the liquid crystal panel assembly according to the present exemplary embodiment includes a lower panel 100 and an upper panel 200 facing each other, a liquid crystal layer 3 and a display panel between the two panels. 100, 200) and a pair of polarizers 12, 22 attached to the outer surface.

The layered structure of the liquid crystal panel assembly according to the present embodiment is usually the same as the layered structure of the liquid crystal panel assembly shown in FIGS. 4 to 6.

Referring to the lower panel 100, a plurality of gate conductors including a gate line 121 and first, second, and third storage electrode lines 131u, 131d, and 131l are formed on the insulating substrate 100. . The gate line 121 includes a plurality of gate electrodes 124 and a wide end portion 129. The first, second, and third storage electrode lines 131u, 131d, and 131l include a plurality of first, second, and third storage electrodes 137u, 137d, and 137l, respectively. The gate insulating layer 140 is formed on the gate conductors 121, 131u, 131d, and 131l.

A plurality of linear semiconductors (not shown) including protrusions 154 are formed on the gate insulating layer 140, and a plurality of linear ohmic contacts (not shown) having a protrusion 163 and a plurality of linear semiconductors are formed thereon. An island-type ohmic contact 165 is formed.

First, second, third, and fourth data lines 171c, 171d, 171e, and 171f include a source electrode 173 and first and second drain electrodes 175a and 175b on the ohmic contact member 165. A data conductor is formed. The first to fourth data lines 171c-f include end portions 179c, 179d, 179e, and 179f, respectively. The first drain electrode 175a includes an extension 177a and the second drain electrode 175b includes an extension 177b.

The gate electrode 124, the source electrode 173, and the first drain electrode 175a together with the semiconductor 154 form a first thin film transistor (TFT) Qa, and a channel of the thin film transistor Qa. A channel is formed in the semiconductor 154 between the source electrode 173 and the first drain electrode 175a. In addition, the gate electrode 124, the source electrode 173, and the second drain electrode 175b together with the semiconductor 154 form a second thin film transistor (TFT) Qb, and the thin film transistor Qb A channel is formed in the semiconductor 154 between the source electrode 173 and the second drain electrode 175b.

A passivation layer 180 is formed on the data conductors 171c-f, 173, 175a, and 175b and the exposed semiconductor 154, and the contact hole 181 is formed in the passivation layer 180 and the gate insulating layer 140. 182c, 182d, 182e, 182f, 183, 185a, 185b, and 187 are formed.

The pixel electrode 191 including the first and second subpixel electrodes 191a and 191b, the contact auxiliary members 81, 82c, 82d, 82e, and 82f, and the connection member 87 are formed on the passivation layer 180. have. The connection member 87 connects the source electrode 173 and the second data line 171b through the contact holes 183 and 187.

Each pixel electrode 191 has four peripheral sides substantially parallel to the gate line 121 or the data line 171c-f and has a substantially rectangular shape in which the right corner is chamfered. The hypotenuse of the pixel electrode 191 forms an angle of about 45 ° with respect to the gate line 121.

A pair of first and second sub-pixel electrodes 191a and 191b constituting one pixel electrode 191 are interdigitated with a gap 94 therebetween, and the first sub-pixel electrode 191a And is inserted in the center of the second sub-pixel electrode 191b. The second subpixel electrode 191b has a larger area than the first subpixel electrode 191a.

The first and second subpixel electrodes 191a and 191b are physically and electrically connected to the first and second drain electrodes 175a and 175b through the contact holes 185a and 185b to form the first and second drain electrodes ( Data voltage is applied from 175a / 175b).

The data voltages applied to the sub-pixel electrodes 191a and 191b together with the common electrode 270 generate an electric field to determine the alignment of the liquid crystal molecules in the liquid crystal layer 3 between the two electrodes 191a / 191b and 270. [

As described above, each of the subpixel electrodes 191a and 191b and the common electrode 270 form the liquid crystal capacitors Clc1 and Clc2 to maintain the applied voltage even after the thin film transistors Qa and Qb are turned off. In order to enhance the voltage holding capability, the storage capacitors Cst1 and Cst2 connected in parallel with the liquid crystal capacitors Clca and Clcb are connected to the first and second subpixel electrodes 191a and 191b and the drain electrodes 175a and 175b connected thereto. Is made by overlapping the extension portions 177a and 177b of the () and sustain electrodes 137u, 137d, and 137l. In more detail, the extension part 177a of the first drain electrode 175a overlaps the first storage electrode line 131u and the first storage electrode 137u, and the extension part of the second drain electrode 175b ( 177b overlaps the third storage electrode line 131l and the third storage electrode 137l. Meanwhile, the first drain electrode 175a of another neighboring pixel overlaps the second storage electrode line 131d and the second storage electrode 137d.

An alignment layer 11 is formed on the pixel electrode 191, the contact auxiliary members 81a and 81c-f, and the passivation layer 180.

Meanwhile, the semiconductor 154 extends along the data lines 171c-f and the drain electrodes 175a and 175b to form a linear semiconductor (not shown), and the ohmic contact 163 has the data lines 171c-f. Extending along to form a linear resistive contact member (not shown). The linear semiconductor has substantially the same planar shape as the data conductors 171c-f, 175a, and 175b and the ohmic contacts 163 and 165 thereunder.

In the method of manufacturing the thin film transistor array panel according to the exemplary embodiment of the present invention, the data line 171c-f, the drain electrodes 175a and 175b, the semiconductor 154, and the ohmic contact members 163 and 165 are photographed once. Form by process.

The photosensitive film used in such a photo process differs in thickness according to a position, and especially includes a 1st part and a 2nd part in order of decreasing thickness. The first portion is positioned in the wiring region occupied by the data lines 171c-f and the drain electrodes 175a and 175b, and the second portion is positioned in the channel region of the thin film transistor.

There may be various methods of varying the thickness of the photoresist film according to the position. For example, a method of providing a translucent area in addition to a light transmitting area and a light blocking area in a photomask is possible. have. The translucent region is provided with a slit pattern, a lattice pattern, or a thin film having a medium transmittance or a medium thickness. When using the slit pattern, it is preferable that the width of the slits and the interval between the slits are smaller than the resolution of the exposure machine used for the photographic process. Another example is a method using a reflowable photoresist. That is, a reflowable photoresist film is formed with a normal exposure mask having only a light-transmitting region and a light-shielding region, and then reflowed to flow into a region where the photoresist film is not left, thereby forming a thin portion.

In this way, a one-time photographic process can be reduced, thereby simplifying the manufacturing method.

Referring to the upper panel 200, the common electrode having the light blocking member 220, the plurality of color filters 230, the overcoat 250, and the cutouts 71, 72a, and 72b is disposed on the insulating substrate 210. 270 and the alignment film 21 are formed.

The common electrode 270 is formed with a central cutout 71, an upper cutout 72a, and a lower cutout 72b, and the pixel electrode 191 includes a plurality of cutouts 71, 72a, and 72b. It is divided into partitions. The cutouts 71, 72a, 72b are almost inverted symmetrical with respect to the sustain electrode lines 131u, 131d.

The lower and upper cutouts 72a and 72b extend obliquely from the right side of the pixel electrode 191 to the left side, the upper side, or the lower side. The lower and upper cutouts 72a and 72b are located at the lower half and the upper half with respect to the sustain electrode lines 131u and 131d, respectively. The lower and upper cutouts 72a and 72b extend perpendicular to each other at an angle of about 45 ° with respect to the gate lines 121a and 121b.

The central cutout 71 includes a central longitudinal portion and a pair of diagonal lines. The central longitudinal portion extends perpendicular to the storage electrode lines 131u and 131d, and the pair of diagonal portions extends toward the left side of the pixel electrode 191 at the end of the central longitudinal portion, respectively.

When a common voltage is applied to the common electrode 270 and a data voltage is applied to the pixel electrode 191, an electric field (electric field) substantially perpendicular to the surfaces of the display panels 100 and 200 is generated. In response to the electric field, the liquid crystal molecules attempt to change their long axis to be perpendicular to the direction of the electric field. In the following, the pixel electrode 191 and the common electrode 271 are collectively referred to as an electric field generating electrode.

On the other hand, the gap 94 of the pixel electrodes of the field generating electrodes 191 and 270 and the incisions 71 to 72b of the common electrode and the hypotenuse of the pixel electrode 191 parallel to these distort the electric field to incline the liquid crystal molecules. Create a horizontal component that determines the direction. The horizontal component of the electric field is perpendicular to the hypotenuse of the cutouts 94, 71-72b and the hypotenuse of the pixel electrode 191.

One common electrode cutout set 71 to 72b and the pixel electrode gap 94 divide the pixel electrode 191 into a plurality of sub-areas, and each of the sub-regions is formed around the pixel electrode 191. It has two major edges that are oblique to. Most of the liquid crystal molecules on each subregion are inclined in a direction perpendicular to the periphery thereof, and thus, the inclination directions are approximately four directions. When the direction in which the liquid crystal molecules are tilted is varied in this way, the reference viewing angle of the liquid crystal display device is increased.

At least one cutout 94, 71-72b may be replaced by a protrusion or depression, and the shape and arrangement of the cutouts 94, 71-72b may be modified.

The liquid crystal layer 3 of the liquid crystal display according to the present exemplary embodiment has negative dielectric anisotropy, and the liquid crystal molecules of the liquid crystal layer 3 are aligned such that their major axes are perpendicular to the surfaces of the two display panels in the absence of an electric field. have.

Many features of the liquid crystal panel assembly illustrated in FIGS. 4 to 6 may also be applied to the liquid crystal panel assembly illustrated in FIGS. 16 and 17.

Next, operations of the liquid crystal display shown in FIGS. 15 to 17 will be described in detail with reference to FIGS. 18A and 18B.

FIG. 18A is a waveform diagram illustrating the sustain electrode signal and the pixel electrode voltage when the pixel electrode voltage changes from negative polarity (−) to positive polarity (+) in the liquid crystal display shown in FIGS. 15 to 17, respectively. 18B is a waveform diagram showing the sustain electrode signal and the pixel electrode voltage when the pixel electrode voltage changes from positive polarity (+) to negative polarity (-) in the liquid crystal display shown in FIGS. 15 to 17, respectively.

The first and second storage electrode signals Vcstu and Vcstd having opposite phases are applied to the first storage electrode line 131u and the second storage electrode line 131d, respectively, after the switching elements Q1 and Q2 are turned off. The voltage levels of the first and second sustain electrode signals Vcstu and Vcstd are inverted, respectively. A constant voltage, for example the common voltage Vcom, is applied to the third storage electrode line 131l.

Referring to FIG. 18A, the subpixel electrode 191b of the second subpixel PX2 receiving the third sustain electrode signal is charged after the switching element Q is turned off, so that the voltage is positive in the negative polarity (−). There is little voltage change after changing to polarity (+). At this time, while charging is performed, the voltage of the subpixel electrode 191a of the first subpixel PX1 to which the first sustain electrode signal Vcstu is applied is changed from the negative polarity (−) to the positive polarity (+). 1 sustain electrode signal Vcstu rises. Thereafter, the voltage of the subpixel electrode 191a of the first subpixel PX1 swings according to the first sustain electrode signal Vcstu. In this case, the voltage of the first subpixel electrode 191a is higher than the voltage of the second subpixel electrode 191b by a predetermined degree ΔVp, and thus the voltage across the first liquid crystal capacitor Clc1 is increased. Higher than the voltage across Clc2).

Referring to FIG. 18B, the subpixel electrode 191b of the second subpixel PX2 receiving the third sustain electrode signal is charged after the switching element Q is turned off, so that the voltage is positive. There is little voltage change after changing to negative (-). At this time, as the charging is performed, after the voltage of the subpixel electrode 191a of the first subpixel PX1 to which the first sustain electrode signal Vcstu is applied is changed from the positive polarity (+) to the negative polarity (−), The second sustain electrode signal Vcstd is lowered. Thereafter, the voltage of the subpixel electrode 191a of the first subpixel PX1 swings according to the second sustain electrode signal Vcstd. In this case, the voltage of the first subpixel electrode 191a is lowered to a certain degree (ΔVp) than the voltage of the second subpixel electrode 191b, so that the voltage across the first liquid crystal capacitor Clc1 is reduced to the second liquid crystal capacitor ( Higher than the voltage across Clc2).

In this way, when a potential difference occurs between both ends of the first or second liquid crystal capacitors Clc1 and Clc2, a primary electric field substantially perpendicular to the surfaces of the display panels 100 and 200 is generated in the liquid crystal layer 3. [Hereinafter, the pixel electrode 190 and the common electrode 270 will be referred to as " field generating electrode. &Quot; The angle of inclination is perpendicular, and the degree of change in polarization of incident light in the liquid crystal layer 3 varies according to the degree of inclination of the liquid crystal molecules. This change in polarization is represented by a change in transmittance by the polarizer, through which the liquid crystal display displays an image.

The angle at which the liquid crystal molecules are inclined depends on the intensity of the electric field. Since the voltages of the two liquid crystal capacitors Clc1 and Clc2 are different from each other, the angles at which the liquid crystal molecules are inclined are different, and thus the luminance of the two subpixels PX1 and PX2 is different. . Therefore, if the voltage of the first liquid crystal capacitor Clc1 and the voltage of the second liquid crystal capacitor Clc2 are properly adjusted, the image viewed from the side can be as close as possible to the image viewed from the front, that is, the side gamma curve is the front gamma curve. As close as possible to this, side visibility can be improved.

In addition, when the area of the first subpixel electrode 191a having a high voltage is smaller than the area of the second subpixel electrode 191b, the side gamma curve may be closer to the front gamma curve.

According to the present invention, it is possible to secure sufficient charging time while increasing the response speed and resolution of the liquid crystal display device and to prevent the generation of vertical crosstalk. In addition, the signal lines of the liquid crystal display can be efficiently arranged.

Claims (43)

A liquid crystal display device comprising a plurality of pixels arranged in a matrix, The first substrate, A plurality of gate lines formed on the first substrate and transferring gate signals to the pixels; and A plurality of data sets intersecting the gate lines and including a first data line, a second data line, a third data line, and a fourth data line, respectively; / RTI > Four neighboring gate lines are electrically connected to each other. In claim 1, The first and second data lines are disposed on the left side of the pixel, and the third and fourth data lines are disposed on the right side of the pixel. 3. The method of claim 2, Wherein the first data line is disposed outside the second data line based on the pixel, and the fourth data line is disposed outside the third data line based on the pixel. 4. The method of claim 3, The pixel includes: A plurality of pixel electrodes formed on the first substrate, and A plurality of switching elements connected to the pixel electrode, the gate line, and the first to fourth data lines, respectively. Containing Liquid crystal display device. 5. The method of claim 4, The switching elements of the neighboring pixels in the column direction are connected to different data lines. The method of claim 5, and the switching element of the pixel of the i th row and the switching element of the pixel of the i + 1 th row are connected to different data lines of the second data line and the third data line. The method of claim 6, and the switching element of the pixel of the i + 2th row and the switching element of the pixel of the i + 3th row are connected to different data lines of the first data line and the fourth data line. 8. The method of claim 7, And the switching elements of pixels neighboring in the column direction are connected to data lines disposed opposite to each other with respect to the pixels. 5. The method of claim 4, And the switching elements of pixels neighboring in the row direction are connected to different data lines. The method of claim 9, And the switching elements of pixels neighboring in the row direction are connected to data lines disposed opposite to each other with respect to the pixels. In claim 1, And a polarity of the data voltages applied to the first and second data lines and the same polarity of the data voltages applied to the third and fourth data lines. 12. The method of claim 11, The polarity of the data voltages applied to the first and second data lines and the polarities of the data voltages applied to the third and fourth data lines are opposite to each other. 5. The method of claim 4, The liquid crystal display of claim 1, wherein the voltage polarities of the pixel electrodes adjacent in the column direction or the row direction are opposite to each other. 5. The method of claim 4, At least one of the first and second data lines overlaps the pixel electrode, and at least one of the third and fourth data lines overlaps the pixel electrode. 5. The method of claim 4, The pixel electrode includes two pairs of peripheral edges parallel to each other. 5. The method of claim 4, A second substrate facing the first substrate, A common electrode formed on the second substrate, A liquid crystal layer interposed between the pixel electrode and the common electrode Further comprising: The liquid crystal molecules of the liquid crystal layer have a long axis arranged in parallel with the first and second substrates without an electric field being formed. 5. The method of claim 4, The switching element each includes a gate electrode, a source electrode and a drain electrode, The drain electrode is electrically connected to each of the first to fourth data lines through a connection member. The method of claim 17, And a planar area of four connection members connecting each of the first to fourth data lines and the drain electrode is substantially the same. The method of claim 18, A protective film formed between the first to fourth data lines and the pixel electrode, The passivation layer includes a plurality of first contact holes exposing each of the first to fourth data lines and a second contact hole exposing the drain electrode. The connection member connects each of the first to fourth data lines and the drain electrode through the first and second contact holes. 20. The method of claim 19, The protective layer includes an organic insulating material. 5. The method of claim 4, And a storage electrode overlapping the pixel electrode. 5. The method of claim 4, The pixel electrode further includes first and second subpixel electrodes that are separated from each other. The method of claim 22, The area of the first subpixel electrode is smaller than the area of the second subpixel electrode. 24. The method of claim 23, The switching element includes a first switching element connected to the first subpixel electrode and a second switching element connected to the second subpixel electrode. 25. The method of claim 24, The first and second switching elements are connected to the same gate line and data line. 26. The method of claim 25, A first storage electrode line receiving a periodic signal, a second storage electrode line receiving a periodic signal different from the first storage electrode line, and a third storage electrode line receiving a constant voltage; The first subpixel electrode overlaps the first or second storage electrode line, and the second subpixel electrode overlaps the third storage electrode line. 26. The method of claim 26, The liquid crystal display of claim 1, wherein a phase of a signal applied to the first storage electrode line and the second storage electrode line is reversed. The method of claim 27, The voltage of the first subpixel electrode and the voltage of the second subpixel electrode are different from each other. 29. The method of claim 28, The voltage of the first subpixel electrode is higher than the voltage of the second subpixel electrode. The method of claim 22, At least one of the first and second data lines overlaps the second subpixel electrode, and at least one of the third and fourth data lines overlaps the second subpixel electrode. The method of claim 22, At least one of the first and second subpixel electrodes has a first oblique direction determining member. 32. The method of claim 31, The first tilt direction determining member includes a cutout. 33. The method of claim 32, A second substrate facing the first substrate, A common electrode formed on the second substrate, A liquid crystal layer interposed between the pixel electrode and the common electrode Further comprising: And a second oblique direction determining member in the common electrode. 34. The method of claim 33, The second inclination direction determining member includes a cutout or a protrusion. The method of claim 34, The liquid crystal molecules of the liquid crystal layer have a long axis arranged perpendicularly to the first and second substrates without an electric field being formed. 5. The method of claim 4, And a common electrode formed on the first substrate and facing the pixel electrode. The method of claim 36, The pixel electrode includes a plurality of cutouts formed at an oblique angle with the gate line. The method of claim 36, And an inorganic insulating film formed between the pixel electrode and the common electrode. A liquid crystal display device comprising a plurality of pixels, A plurality of gate lines transferring a gate signal to the pixel, and A data line group intersecting the gate line and including a first data line, a second data line, a third data line, and a fourth data line, respectively; / RTI > Each pixel, First and second liquid crystal capacitors, A first sustain capacitor having a first terminal connected to the first liquid crystal capacitor and a second terminal receiving a first sustain electrode signal or a second sustain electrode signal opposite in phase to the first sustain electrode signal; A second storage capacitor having a first terminal connected to the second liquid crystal capacitor and a second terminal receiving a constant voltage; / RTI > Four neighboring gate lines are electrically connected to each other. The method of claim 39, Each pixel is A first switching element connected to the gate line, the data line group, the first liquid crystal capacitor and the first storage capacitor, and A second switching element connected to the gate line, the data line group, the second liquid crystal capacitor, and the second storage capacitor Liquid crystal display further comprising. 41. The method of claim 40 wherein The first liquid crystal capacitor includes a first subpixel electrode and a common electrode, and the second liquid crystal capacitor includes a second subpixel electrode and a common electrode. 43. The method of claim 41 wherein The area of the second subpixel electrode is larger than the area of the first subpixel electrode. 5. The method of claim 4, A second substrate facing the first substrate, A common electrode formed on the second substrate, A liquid crystal layer interposed between the pixel electrode and the common electrode Further comprising: The liquid crystal molecules constituting the liquid crystal layer are splay aligned in a state in which no electric field is formed, and bend aligned in a state in which the electric field is formed.

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