KR101294368B1 - Method for creating tandem solar cell with high efficiency using si substrate - Google Patents

Abstract

PURPOSE: A method for producing a tandem solar cell with high efficiency using a Si substrate is provided to reduce the number of processes and product costs by forming a nanowire layer. CONSTITUTION: A p/n-GaAs epi is formed on one side of the p+-Si of an n/p-silicon substrate (S10). An n+-Si surface is formed on the other side of the n/p-silicon substrate. A p/n-InGaAs nanowire is formed on the n+-Si surface. The p/n-InGaAs nanowire has small energy bandgap. A p/n-Ge junction process is performed on the upper part of the nanowire (S20). [Reference numerals] (AA) Start; (BB) End; (S10) p/n-GaAs epi is formed on one upper side of the p+-Si of an n/p-silicon substrate; (S20) p/n-InGaAs nanowire, of which energy band gap is smaller than that of Si, is formed on the n+-Si surface which is another side of the n/p-Si substrate, and a p/n-Ge junction process is performed on the upper part of the nanowire

Description

METHOD FOR CREATING TANDEM SOLAR CELL WITH HIGH EFFICIENCY USING SI SUBSTRATE}

The present invention relates to a method for producing a stacked type high efficiency solar cell using a silicon substrate, and more particularly, to a source technology of fusion of silicon photonics and a solar cell, which simultaneously acquires low cost and high efficiency of a solar cell including a compound and a Ge using a silicon substrate. The present invention relates to a technology for providing a new concept based solar cell.

The prior art of fabricating a III-V solar cell on a silicon substrate mainly consists of a structure in which a III-V single junction or multi-junction solar cell is formed on one side using a silicon substrate as a medium.

Referring to Figure 1, the Republic of Korea Patent No. 10-1118929 (manufacturing apparatus and manufacturing method of a thin-film solar cell) is as follows. The prior patent has a first electrode forming portion for forming a first electrode on the substrate, removing the predetermined region of the first electrode to form a first separation; A photoelectric conversion layer forming unit receiving a substrate on which the first electrode and the first separation unit are formed by the first electrode forming unit to form a photoelectric conversion layer on the substrate including the first electrode and the first separation unit; A contact line forming unit receiving a substrate on which the photoelectric conversion layer is formed by the photoelectric conversion layer forming unit and removing a predetermined region of the photoelectric conversion layer formed on the first electrode to form a contact line; The printing unit receives a substrate on which the contact line is formed by the contact line forming unit, and is connected to the first electrode through the contact line and forms a second electrode on the photoelectric conversion layer that is spaced at a predetermined interval with the second separation unit therebetween. ; And an etching process of receiving the substrate on which the second electrode is formed by the printing unit and removing the photoelectric conversion layer in the second separation unit through a wet etching process using the second electrode as a mask to expose the first electrode in the second separation unit. It is configured to include a wealth.

However, the prior patent is a technology for improving the mass productivity by simply shortening the process time of the second electrode / cell separation or the second electrode / cell separation / light transmitting portion, tunnel junction between the silicon substrate and the group III-V on the top The stacked solar cell has not been considered to date.

In addition, all of the III-V compound solar cells grown on the silicon substrate in the present study have applied the same III-V compound with a larger band gap than silicon on one side, and thus, the solar absorption band gap region has a limit.

In contrast, the present invention establishes the tunnel cushion through the high concentration of the interface by intermixing the group III and Si substrate of the III-V group by high temperature heat treatment, and the upper surface of one side has a higher energy band gap than silicon. P / n-Ge material or InGaAs nanowire structure having a band gap less than Si, and a Si substrate is p / n formed by p / n dopant formation. By providing a material of -Si, it provides a source technology for forming a solar cell capable of absorbing a wide solar spectrum.

The present invention provides a method of producing a stacked high efficiency solar cell using a silicon substrate and a method of forming a nanowire layer that replaces the conventional thin film structure, thereby obtaining a silicon photonics and a solar cell structure including a compound and Ge using a silicon substrate. The purpose is to provide a new concept of solar cell based on the original technology of fusion of the battery.

In order to achieve the above technical problem, the method of generating a stacked type high efficiency solar cell using the silicon substrate of the present invention comprises the steps of: forming a p / n-GaAs epi on one side of p ⁺ -Si of an n / p-silicon substrate; ; And (b) forming a p / n-InGaAs nanowire having a smaller energy band gap than Si on the n ⁺ -Si surface, which is the other side of the n / p-silicon substrate, and performing a p / n-Ge bonding process thereon. It includes;

Further, after step (b), the step (c) of growing a III-V stacked solar cell structure on the n / p-GaAs; (D) depositing a protective film such as a SiO ₂ layer or a SiNx layer on the grown III-V stacked solar cell; And (e) forming a highly-concentrated tunnel layer by interfacial diffusion between the Si substrate and III-V through heat treatment.

In addition, the method of producing a laminated high efficiency solar cell using the silicon substrate of the present invention, the step of forming a p / n-GaAs nanowires on the p + -Si substrate surface; (b) forming a p / n- (InxGa1-x) yAl1-yP nanowire layer on the p + -Si substrate when the p / n-GaAs thin film is grown, after tunneling growth on the thin film; After step (a) or (b), the nanowire is covered with the SU8 layer by a spin coater method, and the upper p-type nanowire portion is formed to be exposed, and a process of depositing a ZnO layer thereon is performed. c) step; And (d) performing an Al layer lamination and AR coating lamination process on the ZnO layer.

In addition, the method of producing a stacked type high efficiency solar cell using the silicon substrate of the present invention comprises the steps of: stacking a ZnO layer on the SU8 layer; (b) covering the nanowires with a SU8 layer by a spin coater method, forming a top p-type nanowire portion to expose the nanowires, and depositing a ZnO layer thereon; And (c) performing an Al layer lamination and an AR coating lamination process on the ZnO layer.

In addition, the method of producing a stacked high efficiency solar cell using the silicon substrate of the present invention comprises the steps of: stacking a SU8 layer on top of the ZnO layer; (b) covering the nanowires with a SU8 layer by a spin coater method, forming a top p-type nanowire portion to expose the nanowires, and depositing a ZnO layer thereon; And (c) performing an Al layer lamination and an AR coating lamination process on the ZnO layer.

In addition, the method of producing a laminated high efficiency solar cell using the silicon substrate of the present invention comprises the steps of: (a) forming a nanowire layer; (B) forming a SU8 layer and a ZnO layer; (C) stacking an SU8 layer on the ZnO layer without performing an Al layer lamination and AR coating process on the ZnO layer; (d) depositing a ZnO layer on top of the SU8 layer of step (c); (e) forming a p / n- (InxGa1-x) yAl1-yP nanowire layer on the ZnO layer of step (d); (F) performing a process of forming a ZnO layer on the nanowire layer by covering the nanowires with a SU8 layer by a spin coater method, exposing a top p-type nanowire portion, and depositing a ZnO layer thereon; And (g) performing an Al layer lamination and an AR coating lamination process on the ZnO layer.

In accordance with the present invention as described above, represents a structure for obtaining a high efficiency solar cell using a Si substrate, p ^- - after the formation of the both sides of the Si with p ⁺ -Si and n ⁺ -Si a high concentration p ⁺ -Si surface has By growing III-V compound thin films or nanowires with a larger energy bandgap than silicon, the other n ⁺ -Si plane grows Ge or InGaAs nanowires with an energy bandgap smaller than that of a silicon substrate. Compared to conventional III-V compound solar cells on a silicon substrate, there is an effect that the solar cell can absorb a wide area of 650 nm to 1800 nm by band gap control.

1 is a block diagram showing a conventional surge protector integrated circuit breaker.
Figure 2 is a schematic flow chart illustrating a laminated solar cell epi process of the laminated high efficiency solar cell using a silicon substrate according to the present invention.
Figure 3 is a (a) reaction tube when growing a good quality n-In _1-x Ga _x As (0.98 ≤ x ≤ 1) on the p-Si (100) substrate of the laminated high efficiency solar cell using a silicon substrate according to the present invention Example of the growth temperature of the procedure, and (b) SEM image of the growth of GaAs on the Si substrate.
4 is a structural diagram showing a laminated high efficiency solar cell using a silicon substrate according to the present invention.
5 is a view showing an example of a laminated high efficiency solar cell structure using a silicon substrate according to the present invention.
FIG. 6 is a view illustrating a scanning electron microscope (SEM) photograph in which nanowires are formed on a silicon substrate of a stacked high efficiency solar cell using a silicon substrate according to the present invention. FIG.
7 is a view showing the solar spectrum of the laminated high efficiency solar cell using the silicon substrate according to the present invention and the energy band gap and lattice constant for each material.
8 is a flowchart illustrating a method of generating a stacked high efficiency solar cell using a silicon substrate according to the present invention.
9 is a flowchart illustrating a process after step S20 of the method of generating a stacked high efficiency solar cell using a silicon substrate according to the present invention.
FIG. 10 is a flowchart illustrating a first method of forming a nanowire replacing a conventional thin film process based on steps S10 and S20 of a method of generating a stacked high efficiency solar cell using a silicon substrate according to the present invention.
FIG. 11 is a flowchart illustrating a second method of forming a nanowire replacing a conventional thin film process based on steps S10 and S20 of a method of generating a stacked high efficiency solar cell using a silicon substrate according to the present invention. FIG.
12 is a flowchart illustrating a third method of forming a nanowire replacing the conventional thin film process based on the step S10 and the step S20 of the method for producing a stacked high efficiency solar cell using a silicon substrate according to the present invention.
FIG. 13 is a flowchart illustrating a fourth method of forming a nanowire replacing a conventional thin film process based on steps S10 and S20 of a method of generating a stacked high efficiency solar cell using a silicon substrate according to the present invention. FIG.

Specific features and advantages of the present invention will become more apparent from the following detailed description based on the accompanying drawings. Prior to this, terms and words used in the present specification and claims are to be interpreted in accordance with the technical idea of the present invention based on the principle that the inventor can properly define the concept of the term in order to explain his invention in the best way. It should be interpreted in terms of meaning and concept. In addition, when it is determined that the detailed description of the known function and its configuration related to the present invention may unnecessarily obscure the subject matter of the present invention, it should be noted that the detailed description is omitted.

1. p / n-Si semiconductor formation process

First, as shown in FIG. 2, one side is deposited at 900 nm of SiO ₂ on a p-Si (100) substrate (1-5 × 10 ¹⁵ cm ⁻³ ).

Subsequently, a dopant material is deposited on the other side by a spin on dopant method, and then a heat treatment process is performed at 1100 ° C.

Subsequently, SiO ₂ and phosporous in p-Si were etched in HF for 1 minute and then subjected to Piranha cleaning (H ₂ SO ₄ : H ₂ O ₂ = 3: 1).

Then, SiO ₂ 900nm was deposited by PECVD (Plasma Enhanced Chemical Vapor Deposition) on the surface where n ⁺ -Si was formed, the Boron solution was deposited by spin coating method, and then baked on a hot plate, followed by annealing at 1100 ° C. do.

2. Good quality n-In on p-Si (100) substrate _1-x Ga _x As (0.98 ≤ x ≤ 1) growth

First of all, this structure is a method for forming a good quality n-GaAs buffer layer without anti phase domain on p-Si (100) silicon substrate. The main process is cleaning process, inclination angle of substrate, growth temperature and growth flow rate. Etc.

First, as shown in Figure 3, after etching the surface of the silicon substrate with BOE for 3 to 30 minutes or more, and then put in an organic metal chemical vapor deposition (MOCVD) equipment to remove the natural oxide film at a high temperature of 750 ℃ or more, 380 After lowering to a low temperature of about ℃ to 420 ℃, indium gallium arsenide (In _1-x Ga _x As (0.98≤x≤1)) seed layer is thinly grown to 5nm to 15nm.

Subsequently, the InGaAs layer is grown after the heat treatment while raising the temperature to a general growth temperature without supplying a source. At this time, the growth structure is n / p-InGaAs structure, the wavelength band is 840nm to 900nm region, and in some cases, thermal recycle annealing can be performed to increase the effect of the heat treatment to obtain a high quality good quality structure.

3. Growth of Multi-junction Solar Cells on n-InGaAs Buffer Layer

Figure 4 is a structural diagram showing a red type high efficiency solar cell using a silicon substrate according to the present invention, Figure 5 is a view showing an example of a structure of a red type high efficiency solar cell using a silicon substrate according to the present invention, Figure 6 Is a view illustrating a scanning electron microscope (SEM) photograph in which nanowires are formed on a silicon substrate of an red type high efficiency solar cell using a silicon substrate according to the present invention.

As shown in Figs. 4 to 6, the multi-junction solar cell structure growth technology on the n-InGaAs buffer layer grown by the p / n-Si semiconductor formation process, each p / n as in the general high efficiency solar cell growth technology It must be designed to match the current absorbed by the materials making up the section. Typical structures for each wavelength are p / n-InGaP or p / n-AlGaAs in the range of 650 nm to 700 nm.

4. High concentration tunneling formation by interdiffusion between n-InGaAs and p-Si substrate interface

After growth of the solar cell structure, a protective film such as SiN _x or SiO ₂ is deposited on both surfaces, and as the Si of the silicon substrate is intermixed with GaAs through heat treatment of 900 nm to 1100 nm, a high concentration of n-type GaAs can be formed at the interface portion. have.

5. Formation of high concentration n-Si on p-Si substrate

n-type Si is formed on the p-Si substrate by the diffusion of Phosphorus (P) and Arsenide (As), followed by the deposition of solvent by spin coater method, followed by heat treatment.The Si substrate and CeP5O14 N-type Si may be obtained by arranging the same ceramic material side by side and then doping by heat treatment.

6. Ge growth on Si substrate

As a growth method for overcoming the lattice and thermal expansion mismatch of the Si substrate and the Ge substrate, a high quality Ge thin film can be grown by a similar procedure to the method of growing GaAs on the Si substrate as shown in FIG. 3.

7. Growth of p / n- nanowire using nanowire instead of thin film of solar cell

The use of nanowires such as (5) to (7) shown in FIG. 2 has the advantage of being more efficient than thin films but able to grow at low cost and approaching a wavelength band that is difficult to approach.

As a method for growing 1-D nanowires having a one-dimensional growth direction, a VLS method using a metal catalyst such as Au, a method of growing nanowires on a SiO ₂ pattern using e-beam lithography, and any catalyst Alternatively, there is a Volmer-Weber-type nanowire growth method using strain coming from a gap with a silicon substrate without a pattern, and FIG. 3 is a SEM photograph of a nanowire growth state.

On the other hand, the thin film structure of the high efficiency III-V solar cell using a silicon substrate, can be appropriately replaced with a suitable nano-wire material for each layer. For example, in the left stacked thin film structures (2), (3), and (4) of FIG. 4, the right nanowire utilization structures ((5), (6), and (7)) are as follows. Is a diagram showing the solar spectrum and the energy band gap and lattice constant for each material.

Thin film (3)-> nanowire structure (6) (nanowire bandgap (Eg) ≥ GaAs bandgap)

Thin Film (2) + (3)-> Nanowire Structure (5) + (6)

Thin film (4)-> nanowires (7) (0.3 eV ≤ nanowires InGaAs bandgap ≤ silicon bandgap)

Hereinafter, referring to FIG. 8, the method for generating a stacked type high efficiency solar cell using the silicon substrate according to the present invention is as follows.

First, p / n-GaAs epi is formed on one side of p ⁺ -Si of the n / p-silicon substrate (S10).

In addition, p / n-InGaAs nanowires having a smaller energy band gap than Si are formed on the n ⁺ -Si surface, which is the other side of the n / p-silicon substrate, and a p / n-Ge bonding process is performed thereon (S20). ).

Here, the energy band gap (Eg) refers to the difference between the lowest energy of the conduction band and the highest energy of the consumer electronics band, and detailed description thereof will be omitted.

9, the process after step S20 of the method of generating a stacked type high efficiency solar cell using the silicon substrate according to the present invention will be described below.

After step S20, a III-V stacked solar cell structure is grown on the n / p-GaAs (S30).

Subsequently, a protective film such as an SiO ₂ layer or a SiNx layer is deposited on the grown III-V stacked solar cell (S40).

Then, through the heat treatment to form a high concentration tunnel layer by the interfacial diffusion between the Si substrate and III-V (S50).

Meanwhile, a first method of forming nanowires replacing the conventional thin film process based on steps S10 and S20 of the method of generating a stacked high efficiency solar cell using a silicon substrate according to the present invention with reference to FIGS. 4 and 10. Is shown below.

After the n-AlGaAs or n-InGaAs layer is laminated on the conventional BSF layer, the p-AlGaAs or p-InGaP layer is laminated on the n-AlGaAs or n-InGaAs layer, and then the p ⁺ -GaAs ohmic layer and the Au layer In contrast to the conventional thin film solar cell process that performs the lamination and AR coating process,

In the nanowire formation of the stacked high efficiency solar cell using the silicon substrate according to the present invention, first, p / n-GaAs nanowires are formed on the p + -Si substrate (S110).

Meanwhile, when the p / n-GaAs thin film is grown on the surface of the p + -Si substrate before the step S110, after forming the tunnel junction on the thin film, a p / n- (InxGa1-x) yAl1-yP nanowire layer is formed. (S120).

After step S110 or step S120, the nanowire is covered with a SU8 layer by a spin coater method, and a top p-type nanowire portion is formed to be exposed, and a process of depositing a ZnO layer on the top is performed (S130). .

In addition, an Al layer and an AR coating lamination process are performed on the ZnO layer (S140).

At this time, the nanowire bandgap (Eg) is configured to be greater than or equal to the bandgap of GaAs (nanowire bandgap (Eg) ≥ GaAs bandgap).

In addition, the second method of forming a nanowire to replace the conventional thin film process based on the step S10 and step S20 of the method for producing a stacked high efficiency solar cell using a silicon substrate according to the present invention with reference to FIGS. Is shown below.

In contrast to the conventional thin-film solar cell process in which an n-GaAs layer is laminated on a conventional Tunnel Junction 2 layer, a p-GaAs layer is laminated on an n-GaAs layer, and a Tunnel Junction 1 layer is laminated.

In the nanowire formation of the stacked high efficiency solar cell using the silicon substrate according to the present invention, a ZnO layer is stacked on the SU8 layer (S210).

Subsequently, the nanowire is covered with the SU8 layer by a spin coater method, and the upper surface of the p-type nanowire is formed to be exposed, and a process of depositing a ZnO layer thereon is performed (S220).

In addition, the Al layer and AR coating lamination processes are performed on the ZnO layer (S230).

Also, referring to FIGS. 4 and 12, a third method of forming nanowires replacing conventional thin film processes based on steps S10 and S20 of the method of generating a stacked type high efficiency solar cell using a silicon substrate according to the present invention. Is shown below.

A BSF layer is laminated on a conventional n-Ge substrate, an n-Ge layer is laminated on an BSF layer, a p-Ge layer is laminated on an n-Ge layer, and a Tunnel Junction 3 layer is formed on an p-Ge layer. In contrast to the conventional thin film solar cell process of performing a process of laminating,

In the nanowire formation of the stacked high efficiency solar cell using the silicon substrate according to the present invention, a SU8 layer is stacked on the ZnO layer (S310).

Subsequently, the nanowire is covered with the SU8 layer by a spin coater method, and the upper surface of the p-type nanowire is formed to be exposed, and a process of depositing a ZnO layer thereon is performed (S320).

In operation S330, an Al layer deposition and an AR coating deposition process are performed on the ZnO layer.

In addition, a fourth method of forming a nanowire to replace the conventional thin film process based on the step S10 and step S20 of the method for producing a stacked type high efficiency solar cell using a silicon substrate according to the present invention with reference to FIGS. Is shown below.

Nanowire formation of a laminated high efficiency solar cell using a silicon substrate according to the present invention, first, to form a nanowire layer (S410).

Subsequently, a SU8 layer and a ZnO layer are formed (S420).

Subsequently, without performing the Al layer deposition and AR coating process on the ZnO layer, the SU8 layer is laminated on the ZnO layer (S430).

Subsequently, a ZnO layer is stacked on the SU8 layer (S440).

Subsequently, a p / n- (InxGa1-x) yAl1-yP nanowire layer is formed on the ZnO layer (S450).

Subsequently, the nanowire layer is covered with the SU8 layer by a spin coater method on the nanowire layer, and the upper p-type nanowire portion is formed to be exposed, and a ZnO layer is deposited on the nanowire layer (S460).

Then, Al layer deposition and AR coating process is performed on the ZnO layer (S470).

While the present invention has been particularly shown and described with reference to preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. It will be appreciated by those skilled in the art that numerous changes and modifications may be made without departing from the invention. And all such modifications and changes as fall within the scope of the present invention are therefore to be regarded as being within the scope of the present invention.

Claims (6)

In the method of producing a laminated high efficiency solar cell using a silicon substrate,
(a) forming p / n-GaAs epi on one side of p ⁺ -Si on the n / p-silicon substrate; And
(b) forming a p / n-InGaAs nanowire having a smaller energy band gap than Si on the n ⁺ -Si surface, which is the other side of the n / p-silicon substrate, and performing a p / n-Ge bonding process thereon; Steps to produce a stacked type high efficiency solar cell using a silicon substrate comprising a. The method of claim 1,
After the step (b)
(c) growing a III-V stacked solar cell structure on the n / p-GaAs;
(d) depositing a protective film such as a SiO ₂ layer or a SiNx layer on the grown III-V stacked solar cell; And
(e) forming a highly-concentrated tunnel layer by interfacial diffusion between the Si substrate and III-V through heat treatment; and forming a stacked high efficiency solar cell using a silicon substrate. In the method of producing a laminated high efficiency solar cell using a silicon substrate,
(a) forming p / n-GaAs nanowires on the p + -Si substrate surface;
(b) forming a p / n- (InxGa1-x) yAl1-yP nanowire layer on the p + -Si substrate when the p / n-GaAs thin film is grown, after tunneling growth on the thin film;
(c) after step (a) or step (b), cover the nanowires with a SU8 layer by a spin coater method, and form a top portion of the p-type nanowire so as to expose a portion thereof, and deposit a ZnO layer thereon. Performing; And
(d) performing an Al layer lamination and an AR coating lamination process on the ZnO layer; a method of producing a stacked type high efficiency solar cell using a silicon substrate, the method comprising: In the method of producing a laminated high efficiency solar cell using a silicon substrate,
(a) depositing a ZnO layer on top of the SU8 layer;
(b) covering the nanowires with a SU8 layer by a spin coater method, forming a top p-type nanowire portion to expose the nanowires, and depositing a ZnO layer thereon; And
(c) performing an Al layer lamination and an AR coating lamination process on the ZnO layer. 2. In the method of producing a laminated high efficiency solar cell using a silicon substrate,
(a) stacking a SU8 layer on top of the ZnO layer;
(b) covering the nanowires with a SU8 layer by a spin coater method, forming a top p-type nanowire portion to expose the nanowires, and depositing a ZnO layer thereon; And
(c) performing an Al layer lamination and an AR coating lamination process on the ZnO layer. 2. In the method of producing a laminated high efficiency solar cell using a silicon substrate,
(a) forming a nanowire layer;
(b) forming a SU8 layer and a ZnO layer;
(c) stacking an SU8 layer on the ZnO layer without performing an Al layer lamination and AR coating process on the ZnO layer;
(d) depositing a ZnO layer on top of the SU8 layer of step (c);
(e) forming a p / n- (InxGa1-x) yAl1-yP nanowire layer on the ZnO layer of step (d);
(f) covering the nanowires with a SU8 layer by a spin coater method on the nanowire layer, exposing a top p-type nanowire portion, and depositing a ZnO layer thereon; And
(g) performing an Al layer lamination and an AR coating lamination process on the ZnO layer; a method of producing a stacked type high efficiency solar cell using a silicon substrate, comprising: a.

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