KR101273524B1 - Semiconductor chip package, and Tape carrier package for transferring the same - Google Patents

Semiconductor chip package, and Tape carrier package for transferring the same Download PDF

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Publication number
KR101273524B1
KR101273524B1 KR1020110103904A KR20110103904A KR101273524B1 KR 101273524 B1 KR101273524 B1 KR 101273524B1 KR 1020110103904 A KR1020110103904 A KR 1020110103904A KR 20110103904 A KR20110103904 A KR 20110103904A KR 101273524 B1 KR101273524 B1 KR 101273524B1
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South Korea
Prior art keywords
tape carrier
chip
region
package
chips
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KR1020110103904A
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Korean (ko)
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KR20130039391A (en
Inventor
강석훈
임준성
홍성원
신세철
최영민
전민호
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주식회사 루셈
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Priority to KR1020110103904A priority Critical patent/KR101273524B1/en
Publication of KR20130039391A publication Critical patent/KR20130039391A/en
Application granted granted Critical
Publication of KR101273524B1 publication Critical patent/KR101273524B1/en

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)

Abstract

The tape carrier package is a tape carrier fabricated in a strip shape that can be wound on a reel, and is continuously arranged on the tape carrier, and the arrangement position in the width direction of the tape carrier is alternately adjacent to both sides of the tape carrier so that the tape A plurality of chips are arranged in a zigzag form along the longitudinal direction of the carrier. The solder resist region connecting the chip to the input lead and the output lead comprises a first area extending in the width direction of the tape carrier, including the occupied area of the chip on the tape carrier, and a first region adjacent to each chip. And a second region extending in the longitudinal direction of the tape carrier from the region. At this time, the second regions of the adjacent pair of chips are configured to extend in opposite directions. By increasing the density of the chip package provided in the tape carrier package, it is possible to reduce the consumption of the tape carrier used in the semiconductor packaging process and to reduce the time required for the packaging process.

Description

Semiconductor chip package, and Tape carrier package for transferring the same}

The present invention relates to a semiconductor chip package and a tape carrier package for transporting the same, and more particularly, to a chip package and a tape having a structure capable of increasing the density of the semiconductor chip conveyed by the tape carrier in a packaging process of the semiconductor chip. Relates to a carrier package.

Semiconductor chips are fabricated as wafers and then packaged into individual chips to form chip packages. Before the individual chips, which are diced from the wafer, are finally formed into mountable forms on the substrate, the individual chips are mounted on a tape carrier and subjected to various processes for packaging. 1 and 2 show a semiconductor chip mounted on a tape carrier as described above.

The tape carrier 10 is formed in the shape of a long strip and wound on the reel 40, and sprocket holes for transferring the tape carrier 10 using sprockets (not shown) on both sides of the tape carrier 10. 40 is formed. On one surface of the tape carrier 10, the chip package 20 is sequentially arranged along the longitudinal direction. The chip package 20 is composed of a chip 21, a solder resist area 23, and a lead 25, and is transferred on the tape carrier 10.

If the number of chip packages 20 per unit length can be increased by reducing the distance between the chip packages 20 attached on the tape carrier 10, the consumption of the tape carrier 10 required in the packaging process can be reduced. In addition, the packaging process can be performed more quickly by reducing the conveying length of the tape carrier 10 which must be moved by the sprocket in the packaging process.

However, in the structure of the conventional tape carrier package as shown in FIG. 2, in order to increase the density of the chip package 20, a method of narrowing the distance between the chip 21 and the lead 25 or narrowing the distance between the chip packages 20 is performed. There is nothing but physically limited method. Therefore, there is a need for a method of increasing the intensity of the chip package 20 by narrowing the distance between the chips 21 while maintaining the distance as necessary.

An object of the present invention is to increase the density of the chip package provided in the tape carrier package, to provide a method to reduce the consumption of the tape carrier used in the semiconductor packaging process and to reduce the time required for the packaging process.

In order to achieve the above object, the present invention is a tape carrier fabricated in a band shape that can be wound on a reel; The tape carrier is continuously disposed at predetermined intervals along the longitudinal direction of the tape carrier, and the arrangement position in the width direction of the tape carrier is alternately adjacent to both sides of the tape carrier so that A plurality of chips arranged in a zigzag form along the length direction; An input lead and an output lead connected to each said chip; And a solder resist region for connecting the chip to the input lead and the output lead.

The solder resist region includes an occupied region of the chip on the tape carrier and extends in the width direction of the tape carrier, and the tape carrier from the first region at a portion adjacent to each chip. It comprises a second region extending in the longitudinal direction of the. In this case, the second regions of the adjacent pair of chips extend in opposite directions to each other. One of the input lead and the output lead is formed at the end of the first region and the other is formed at the end of the second region.

On the other hand, according to the present invention, a chip; An input lead and an output lead connected to the chip; And a solder resist region connecting the chip to the input lead and the output lead, wherein the solder resist region comprises a region including the chip and extends to one side of the chip; And a second region extending from the first region at a portion adjacent to the chip, wherein one of the input lead and the output lead is formed at an end of the first region and the other is an end of the second region. Provided is a chip package, characterized in that formed in.

According to the present invention, the chip package included in the tape carrier package may be increased, thereby reducing the consumption of the tape carrier used in the semiconductor packaging process and reducing the time required for the packaging process.

1 is a view showing a general state of a tape carrier package wound on a reel.
FIG. 2 is an enlarged view of the tape carrier package of FIG. 1.
3 shows a part of a tape carrier package according to the invention.

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings. Figure 3 is a view showing a tape carrier package according to the present invention, an enlarged view of a portion of the entire tape carrier package. (In the description of the present invention, the term "tape carrier package" is used to refer to the entirety of the tape carrier 110 and the chip package 120, the chip package 120 is a chip except the tape carrier 110) (121) and the solder resist regions 123 and 124 and the leads 125 and 126 as a whole.

The tape carrier package consists of a tape carrier 110 and a chip package 120. As in the related art of FIG. 2, the tape carrier 110 is manufactured to have a long band shape and wound on a reel, and a plurality of sprocket holes 111 are formed at both sides thereof in a length direction thereof.

The chip package 120 includes a chip 121, solder resist regions 123 and 124, and leads 125 and 126.

The chips 121 are continuously disposed on the tape carrier 110 at predetermined intervals along the longitudinal direction of the tape carrier 110. At this time, each chip 121 is configured such that the arrangement position in the width direction of the tape carrier 110 is alternately adjacent to both sides of the tape carrier 110. That is, in the prior art of FIG. 2, all the chips 21 are arranged to be located at the center of the tape carrier 10, but in the present invention, any one chip 121 is eccentrically to the right on the tape carrier 110. And the next chip 121 is arranged eccentrically to the left on the tape carrier 110, and thus the eccentric arrangement alternates left and right so that each chip 121 is in the longitudinal direction of the tape carrier 110. Along the zigzag shape.

The solder resist areas 123 and 124 serve to connect the chip 121 to the leads 125 and 126, and are composed of a first region 123 and a second region 124. . (Conceptally divided into the first region 123 and the second region 124, but typically it will be composed of one integrated region.)

The first region 123 includes an area occupied by the chip 121 on the tape carrier 110 and is formed to extend in the width direction of the tape carrier 110. (In this embodiment, since the shape of the chip 121 itself has a shape extending in the width direction of the tape carrier 110, it is described that the first region 123 extends in the width direction accordingly. In other words, the first region 123 is formed over almost the entire area of the tape carrier 110 in the width direction.) The second region 124 is the first region at a portion adjacent to each chip 121. It is produced in the form extending in the longitudinal direction of the tape carrier 110 from (123). Accordingly, the solder resist regions 123 and 124 are configured to have an overall "L" shape.

In this case, the second regions 124 of the pair of adjacent chips 121 are configured to extend in opposite directions. That is, as shown in FIG. 3, the second region of the first chip extends downward, the second region of the second chip extends upwards, and the second region of the third chip extends downward again, thereby adjoining When the two chips are viewed as a pair, the second regions face each other.

The leads 125 and 126 are composed of an input lead 125 and an output lead 126. The input lead 125 is formed in the first region 123 and the output lead 126 is formed in the second region 124. At this time, the input lead 125 and the output lead 126 are formed at the ends (the ends in the longitudinal direction of the tape carrier 110) of the first region 123 and the second region 124, respectively. In this case, the input lead 125 is formed in the first region 123 and the output lead 126 is formed in the second region 124. However, this may be configured in reverse. Since the width thereof is narrower than that of the first region 123, a smaller number of the input lead 125 and the output lead 126 may be formed in the second region 124.

According to this configuration, the chip 121 is not placed in the center of the tape carrier 110 but alternately laterally eccentric, and the second region 126 of the solder resist where the output lead 126 is disposed Since the second region 126 is formed to partially extend from the vicinity of the 121, the second region 126 may be configured to protrude in the longitudinal direction only in a portion of the tape carrier 110. Therefore, the second region 126 and the output lead 126 of the two adjacent chips 121 can be placed in the overlapping position when viewed from the side of the tape carrier 110, the chip 121 and each lead While maintaining the distance between the 125 and 126 the same as in the prior art of Figure 2 it is possible to narrow the distance between each chip 121.

Therefore, the density of chips 121 per unit length of the tape carrier 110 can be increased, thereby reducing the consumption of the tape carrier 110.

In addition, since the spacing between the chips 121 is narrower than in the prior art, the sequential transfer of the individual chips 121 during the subsequent packaging process of each chip 121 is reduced, so that the transfer This reduces the time required to reduce the time required for the entire packaging process and increases productivity.

Meanwhile, the final chip package 120 manufactured through the tape carrier package configured as described above has a form in which solder resist regions 123 and 124 are eccentrically laterally, as shown in the individual chip packages 120 of FIG. 3. Will have

110: tape carrier 121: chip
123, 124: solder register area 125, 126: lead

Claims (5)

delete A tape carrier made of a strip shape that can be wound on a reel;
The tape carrier is continuously disposed at predetermined intervals along the longitudinal direction of the tape carrier, and the arrangement position in the width direction of the tape carrier is alternately adjacent to both sides of the tape carrier so that A plurality of chips arranged in a zigzag form along the length direction;
An input lead and an output lead connected to each said chip; And
And a solder resist region connecting the chip to the input lead and the output lead,
The solder resist region is,
A first area extending in the width direction of the tape carrier, the area occupied by the chip on the tape carrier, and
And a second region extending in the longitudinal direction of the tape carrier from the first region at a portion adjacent to each of the chips.
3. The method of claim 2,
And the second regions of the adjacent pair of chips extend in opposite directions to each other.
The method according to claim 2 or 3,
And one of the input lead and the output lead is formed at the end of the first region and the other is formed at the end of the second region.
delete
KR1020110103904A 2011-10-12 2011-10-12 Semiconductor chip package, and Tape carrier package for transferring the same KR101273524B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020110103904A KR101273524B1 (en) 2011-10-12 2011-10-12 Semiconductor chip package, and Tape carrier package for transferring the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020110103904A KR101273524B1 (en) 2011-10-12 2011-10-12 Semiconductor chip package, and Tape carrier package for transferring the same

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Publication Number Publication Date
KR20130039391A KR20130039391A (en) 2013-04-22
KR101273524B1 true KR101273524B1 (en) 2013-06-17

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000323533A (en) * 1999-05-14 2000-11-24 Sharp Corp Tape carrier and manufacturing tape carrier type semiconductor device
JP2003095321A (en) 2001-09-26 2003-04-03 Rohm Co Ltd Carrier tape for electronic component, and taping electronic component
JP2003282649A (en) 2002-03-27 2003-10-03 Shindo Denshi Kogyo Kk Tape carrier and method of manufacturing the same, method of mounting electronic component to tape carrier, and method of manufacturing tape carrier
JP2011155201A (en) * 2010-01-28 2011-08-11 Sharp Corp Tape carrier, tape carrier-type semiconductor device, and method of manufacturing tape carrier-type semiconductor device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000323533A (en) * 1999-05-14 2000-11-24 Sharp Corp Tape carrier and manufacturing tape carrier type semiconductor device
JP2003095321A (en) 2001-09-26 2003-04-03 Rohm Co Ltd Carrier tape for electronic component, and taping electronic component
JP2003282649A (en) 2002-03-27 2003-10-03 Shindo Denshi Kogyo Kk Tape carrier and method of manufacturing the same, method of mounting electronic component to tape carrier, and method of manufacturing tape carrier
JP2011155201A (en) * 2010-01-28 2011-08-11 Sharp Corp Tape carrier, tape carrier-type semiconductor device, and method of manufacturing tape carrier-type semiconductor device

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