KR101271646B1 - Stacked chip package having electromagnetic bandgap pattern, manufacturing method thereof and semiconductor module including the stacked chip package - Google Patents

Abstract

PURPOSE: A stacked chip package having an electromagnetic bandgap pattern, a manufacturing method thereof, and a semiconductor module including the stacked chip package are provided to efficiently block the propagation of noise by controlling a cutoff frequency band. CONSTITUTION: A first semiconductor chip(110) includes a first interconnection layer. The first interconnection layer is formed on the front surface of a first semiconductor die. A second semiconductor chip(130) includes a first and a second penetration silicone via and a second interconnection layer. The second semiconductor chip is laminated on the first semiconductor chip. An electromagnetic bandgap pattern(138) is arranged in a ground pattern, a power source voltage pattern, and a third layer.

Description

Stacked chip package having an electromagnetic bandgap pattern, a method of manufacturing the same, and a semiconductor module including the stacked chip package TECHNICAL FIELD

The present invention relates to a three-dimensional integrated circuit, and more particularly, to a multilayer chip package including a plurality of stacked semiconductor chips and having an electromagnetic bandgap pattern, a method of manufacturing the stacked chip package and the stacked chip package. It relates to a semiconductor module.

The present invention is a part of the national R & D project of the Ministry of Knowledge Economy and the Korea Institute of Industrial Technology Evaluation and Planning, Project No .: KI002134, under the supervision of the Korea Advanced Institute of Science and Technology. Design and integrated technology "and Dongbu Hi-Tech Co., Ltd., the project's main project number: 10039232, Research project name: Industrial convergence source technology development project, research title:" Development of 3D integration element process technology for system semiconductor ".

As miniaturization, weight reduction, and high integration of semiconductor devices are required, three-dimensional integrated circuits such as stacked chip packages using through silicon vias (TSVs) have recently been studied. have. Various methods for blocking the propagation of noise through a power distribution network in a three-dimensional integrated circuit have been studied.

Conventionally, in order to block propagation of noise through a power distribution network in a three-dimensional integrated circuit, a first scheme and a power distribution network including an on-die decoupling capacitor on the three-dimensional integrated circuit are provided. A second method of physically dividing was used. However, since the noise transmitted through the power distribution network has a relatively high frequency (e.g., in the GHz band), the decoupling capacitor should have a relatively large capacitance when using the first scheme. There has been a problem of increasing the size and manufacturing cost of three-dimensional integrated circuits and limiting system design. In addition, in the case of using the second method, it is difficult to adjust the cutoff frequency range of the noise, and the complexity of the system design increases as additional metal wires are required.

One object of the present invention is to provide a stacked chip package having an electromagnetic bandgap pattern to efficiently block propagation of noise in a power distribution network without increasing manufacturing cost and / or size.

Another object of the present invention is to provide a method of manufacturing the stacked chip package.

Still another object of the present invention is to provide a semiconductor module including the stacked chip package.

In order to achieve the above object, a stacked chip package having an electromagnetic bandgap pattern according to an embodiment of the present invention includes a first semiconductor chip and a second semiconductor chip. The first semiconductor chip includes a first semiconductor die and a first wiring layer formed on an entire surface of the first semiconductor die. The second semiconductor chip includes a second semiconductor die, first and second through silicon vias (TSVs) penetrating through the second semiconductor die, and a second formed on the front surface of the second semiconductor die. A wiring layer is provided and laminated | stacked on the said 1st semiconductor chip. The second wiring layer includes a ground pattern disposed in a first layer, a power supply voltage pattern disposed in a second layer, and the electromagnetic bandgap pattern disposed in a third layer between the first layer and the second layer. The ground pattern is electrically connected to the first TSV, the first TSV is electrically connected to the second TSV, and the second TSV is electrically connected to the electromagnetic bandgap pattern to provide a ground voltage to the electromagnetic bandgap pattern. Is supplied.

The ground pattern may be formed in a first mesh shape including a plurality of first row patterns and a plurality of first column patterns, and the power supply voltage pattern may be alternately arranged with the plurality of first row patterns. And a second mesh including a plurality of second row patterns and a plurality of second column patterns that are alternately disposed with the plurality of first column patterns, wherein the electromagnetic bandgap pattern overlaps the power supply voltage pattern. It may be formed in a cross shape so as not to overlap with the ground pattern.

The second wiring layer may further include a first vertical wire electrically connecting the ground pattern and the first TSV and a second vertical wire electrically connecting the electromagnetic bandgap pattern and the second TSV.

The multilayer chip package may further include a first solder bump electrically connected to the first TSV and a second solder bump electrically connected to the second TSV. The first wiring layer may further include a first wiring electrically connecting the first solder bump and the second solder bump.

A capacitance component may be formed based on the power supply voltage pattern and the electromagnetic bandgap pattern, and an inductance component may be formed based on the first TSV and the second TSV. Based on the capacitance component and the inductance component, transmission of noise corresponding to a cutoff frequency band among noises transmitted to the multilayer chip package may be blocked. In this case, as the area of the electromagnetic bandgap pattern increases, the center frequency of the cutoff frequency band may be lowered.

In order to achieve the above object, in the method of manufacturing a stacked chip package having an electromagnetic bandgap pattern according to an embodiment of the present invention, the first semiconductor chip is formed by forming a first wiring layer on the entire surface of the first semiconductor die. And forming first and second through silicon vias (TSVs) passing through the second semiconductor die, the ground pattern disposed in the first layer, the power supply voltage pattern disposed in the second layer, and the first A second wiring layer including the electromagnetic bandgap pattern disposed in a third layer between the first layer and the second layer is formed on an entire surface of the second semiconductor die to provide a second semiconductor chip, and the first semiconductor The second semiconductor chip is stacked on the chip. The ground pattern is electrically connected to the first TSV, the first TSV is electrically connected to the second TSV, and the second TSV is electrically connected to the electromagnetic bandgap pattern to provide a ground voltage to the electromagnetic bandgap pattern. Is supplied.

In order to achieve the above object, the stacked chip package having a plurality of electromagnetic bandgap patterns according to another embodiment of the present invention includes a first semiconductor chip, a second semiconductor chip and a third semiconductor chip. The first semiconductor chip includes a first semiconductor die and a first wiring layer formed on an entire surface of the first semiconductor die. The second semiconductor chip includes a second semiconductor die, first and second through silicon vias (TSVs) penetrating through the second semiconductor die, and a second formed on the front surface of the second semiconductor die. A wiring layer is provided and laminated | stacked on the said 1st semiconductor chip. The third semiconductor chip includes a third semiconductor die, third and fourth TSVs penetrating through the third semiconductor die, and a third wiring layer formed on an entire surface of the third semiconductor die. Stacked on chip. The second wiring layer may include a ground pattern disposed in a first layer, a power supply voltage pattern disposed in a second layer, and first and second electromagnetic band gap patterns disposed in a third layer between the first layer and the second layer. Include them. The ground pattern is electrically connected to the first TSV, the first TSV is electrically connected to the second TSV, and the second TSV is electrically connected to the first electromagnetic bandgap pattern, thereby providing the first electromagnetic bandgap. A ground voltage is supplied to the pattern, the power voltage pattern is electrically connected to the third TSV, the third TSV is electrically connected to the fourth TSV, and the fourth TSV is electrically connected to the second electromagnetic bandgap pattern. The power supply voltage is supplied to the second electromagnetic bandgap pattern.

The ground pattern may be formed in a first mesh shape including a plurality of first row patterns and a plurality of first column patterns, and the power supply voltage pattern may be alternately arranged with the plurality of first row patterns. It may be formed in the form of a second mesh including the second row patterns of the plurality of second column patterns and the plurality of second column patterns that are alternately disposed with the plurality of first column patterns. The first electromagnetic bandgap pattern is formed in a cross shape so as to overlap the power supply voltage pattern and not overlap the ground pattern, and the second electromagnetic bandgap pattern overlaps the ground pattern and does not overlap the power supply voltage pattern. It may be formed in the cross shape.

The multilayer chip package may further include a first solder bump electrically connected to the third TSV and a second solder bump electrically connected to the fourth TSV. The third wiring layer may further include a first wiring electrically connecting the third TSV and the fourth TSV.

The second wiring layer may further include a first vertical wire electrically connecting the power supply voltage pattern and the third solder bump and a second vertical wire electrically connecting the second electromagnetic band gap pattern and the fourth solder bump. It may include.

A first capacitance component is formed based on the power supply voltage pattern and the first electromagnetic bandgap pattern, and a first inductance component is formed based on the first TSV and the second TSV. A second capacitance component may be formed based on the ground pattern and the second electromagnetic bandgap pattern, and a second inductance component may be formed based on the third TSV and the fourth TSV. Based on the first and second capacitance components and the first and second inductance components, transmission of noise corresponding to a cutoff frequency band among noises transmitted to the multilayer chip package may be blocked.

The distance between the power supply voltage pattern and the first electromagnetic bandgap pattern may be different from the distance between the ground pattern and the second electromagnetic bandgap pattern.

In order to achieve the above object, in the method of manufacturing a stacked chip package having a plurality of electromagnetic bandgap patterns according to another embodiment of the present invention, the first semiconductor layer is formed on the front surface of the first semiconductor die. Providing a chip, forming first and second through silicon vias (TSVs) through the second semiconductor die, a ground pattern disposed in the first layer, a power supply voltage pattern disposed in the second layer, and Providing a second semiconductor chip by forming a second wiring layer on the front surface of the second semiconductor die, the second wiring layer including first and second electromagnetic bandgap patterns disposed in a third layer between the first layer and the second layer; And forming third and fourth TSVs penetrating through the third semiconductor die, and forming a third wiring layer on an entire surface of the third semiconductor die to provide a third semiconductor chip. The second semiconductor chip and the third semiconductor chip are stacked on the sieve chip. The ground pattern is electrically connected to the first TSV, the first TSV is electrically connected to the second TSV, and the second TSV is electrically connected to the first electromagnetic bandgap pattern, thereby providing the first electromagnetic bandgap. A ground voltage is supplied to the pattern, the power voltage pattern is electrically connected to the third TSV, the third TSV is electrically connected to the fourth TSV, and the fourth TSV is electrically connected to the second electromagnetic bandgap pattern. The power supply voltage is supplied to the second electromagnetic bandgap pattern.

In order to achieve the above another object, a semiconductor module according to an embodiment of the present invention includes a base chip and a stacked chip package mounted on the base substrate and having an electromagnetic band gap pattern. The stacked chip package includes a first semiconductor chip and a second semiconductor chip. The first semiconductor chip includes a first semiconductor die and a first wiring layer formed on an entire surface of the first semiconductor die. The second semiconductor chip includes a second semiconductor die, first and second through silicon vias (TSVs) penetrating through the second semiconductor die, and a second formed on the front surface of the second semiconductor die. A wiring layer is provided and laminated | stacked on the said 1st semiconductor chip. The second wiring layer includes a ground pattern disposed in a first layer, a power supply voltage pattern disposed in a second layer, and the electromagnetic bandgap pattern disposed in a third layer between the first layer and the second layer. The ground pattern is electrically connected to the first TSV, the first TSV is electrically connected to the second TSV, and the second TSV is electrically connected to the electromagnetic bandgap pattern to provide a ground voltage to the electromagnetic bandgap pattern. Is supplied.

The stacked chip package according to the embodiments of the present invention includes an electromagnetic bandgap pattern formed between the power supply voltage pattern and the ground pattern so as to overlap the power supply voltage pattern, and having a ground voltage applied thereto to operate as an LC resonator. It includes. The LC resonator is implemented by passive elements, which is relatively simple in structure and can be implemented at low cost, and has a relatively high noise blocking level due to the characteristics of the electromagnetic bandgap structure, and can easily adjust the blocking frequency band. Thus, a stacked chip package can effectively block noise propagation without increasing manufacturing cost and / or size.

1 is a cross-sectional view illustrating a stacked chip package according to an exemplary embodiment of the present invention.
FIG. 2 is a diagram for describing a structure of the stacked chip package of FIG. 1.
3 and 4 are diagrams for describing noise blocking characteristics of the stacked chip package of FIG. 1.
5 is a flowchart illustrating a method of manufacturing a stacked chip package according to an embodiment of the present invention.
6 is a cross-sectional view illustrating a stacked chip package according to another exemplary embodiment of the present disclosure.
FIG. 7 is a diagram for describing a structure of the stacked chip package of FIG. 6.
FIG. 8 is a diagram illustrating noise blocking characteristics of the stacked chip package of FIG. 6.
9 is a flowchart illustrating a method of manufacturing a stacked chip package according to another exemplary embodiment of the present invention.
10 and 11 are cross-sectional views illustrating semiconductor modules according to example embodiments.

For the embodiments of the invention disclosed herein, specific structural and functional descriptions are set forth for the purpose of describing an embodiment of the invention only, and it is to be understood that the embodiments of the invention may be practiced in various forms, The present invention should not be construed as limited to the embodiments described in Figs.

As the inventive concept allows for various changes and numerous modifications, particular embodiments will be illustrated in the drawings and described in detail in the text. It is to be understood, however, that the invention is not intended to be limited to the particular forms disclosed, but on the contrary, is intended to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention.

Terms such as first and second may be used to describe various components, but the components should not be limited by the terms. The terms may be used for the purpose of distinguishing one component from another component. For example, without departing from the scope of the present invention, the first component may be referred to as a second component, and similarly, the second component may also be referred to as a first component.

When a component is referred to as being "connected" or "connected" to another component, it may be directly connected to or connected to that other component, but it may be understood that other components may be present in between. Should be. On the other hand, when an element is referred to as being "directly connected" or "directly connected" to another element, it should be understood that there are no other elements in between. Other expressions describing the relationship between components, such as "between" and "immediately between," or "neighboring to," and "directly neighboring to" should be interpreted as well.

The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In the present application, the terms "comprise", "having", and the like are intended to specify the presence of stated features, integers, steps, operations, elements, components, or combinations thereof, , Steps, operations, components, parts, or combinations thereof, as a matter of principle.

Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in commonly used dictionaries should be construed as meaning consistent with meaning in the context of the relevant art and are not to be construed as ideal or overly formal in meaning unless expressly defined in the present application .

On the other hand, when an embodiment is otherwise implemented, a function or operation specified in a specific block may occur out of the order specified in the flowchart. For example, two consecutive blocks may actually be performed substantially simultaneously, and the blocks may be performed upside down depending on the function or operation involved.

1 is a cross-sectional view illustrating a stacked chip package according to an exemplary embodiment of the present invention. FIG. 2 is a diagram for describing a structure of the stacked chip package of FIG. 1. FIG. 2 is a plan view viewed from an upper surface of a second semiconductor chip included in the stacked chip package of FIG. 1, and illustrates only arrangement of a ground pattern, a power supply voltage pattern, and electromagnetic bandgap patterns for convenience.

1 and 2, the stacked chip package 100 including the electromagnetic band gap pattern 138 may include a first semiconductor chip 110 and a second semiconductor chip 130.

The first semiconductor chip 110 includes a first semiconductor die 112 and a first wiring layer 114. For example, the first semiconductor die 112 may be a semiconductor substrate made of silicon, and may be used to implement a semiconductor chip including a plurality of first devices (not shown) through a CMOS process or the like. The plurality of first elements may be active elements such as transistors or diodes, or may be passive elements such as capacitors or inductors. The first wiring layer 114 is formed on the entire surface of the first semiconductor die 112. Although not shown, the first wiring layer 114 may include a plurality of metal wires. The plurality of metal wires may supply a power supply voltage, a ground voltage, and / or other electrical signals to a first semiconductor chip 110 (ie, the plurality of first elements included in the first semiconductor chip 110). have.

The second semiconductor chip 130 includes a second semiconductor die 132, a first through silicon via (TSV) 133a, a second TSV 133b, and a second wiring layer 134.

The second semiconductor die 132 may be, for example, a silicon substrate, and may include a plurality of second devices (not shown). The first and second TSVs 133a and 133b are formed through the second semiconductor die 132. For example, the first and second TSVs 133a and 133b may be formed using a laser. In detail, a plurality of through holes penetrating the second semiconductor die 132 are generated through a laser process, and conductive materials are filled in the plurality of through holes to form first and second TSVs 133a and 133b. Can be. The depth of the TSV is about several μm when the through holes are formed using the chemical etching process. However, when the TSVs 133a and 133b are formed by using the laser process, the TSVs 133a and 133b may be formed. The depth is about 50 to 500 μm, and thus, signal transmission characteristics may be improved as compared with the case of using a chemical etching process.

In an embodiment, the second semiconductor chip 130 may further include a plurality of insulating layers (not shown) formed between the TSVs 133a and 133b and the second semiconductor die 132. In other words, an insulating film (not shown) may be formed around the TSVs 133a and 133b to prevent direct electrical contact with the second semiconductor die 132. An insulating film (not shown) may be formed to prevent direct electrical contact between the material and the second semiconductor die 132. In this case, the conductive material may be filled after the plurality of through holes are formed and the insulating film is formed. In addition, a tantalum layer (not shown) may be formed between the TSVs 133a and 133b and the insulating layer to increase adhesion between the TSVs 133a and 133b and the insulating layer. That is, a tantalum film may be formed on the inner surface of the insulating film to increase the adhesion between the conductive material and the insulating film. In this case, the conductive material may be filled after the plurality of through holes are formed, the insulating film is formed, and the tantalum film is formed. In another embodiment, an insulating layer may not be formed around the TSVs 133a and 133b.

The second wiring layer 134 is formed on the entire surface of the second semiconductor die 132. The second wiring layer 134 includes a ground pattern 136, a power supply voltage pattern 137, and an electromagnetic bandgap pattern 138. The ground pattern 136 may be disposed in the first layer L1 of the second wiring layer 134 and supply the ground voltage to the second semiconductor chip 130. The power supply voltage pattern 137 may be disposed in the second layer L2 of the second wiring layer 134 and supply the power supply voltage to the second semiconductor chip 130. The electromagnetic bandgap pattern 138 is disposed in the third layer L3 between the first layer L1 and the second layer L2. In this case, the second layer L2 may be disposed on the first layer L1, and the third layer L3 may be disposed on the second layer L2. Although not shown, the second wiring layer 134 may further include signal transmission patterns for supplying electrical signals to the second semiconductor chip 130.

The ground voltage is supplied to the electromagnetic bandgap pattern 138. That is, the ground pattern 136 is electrically connected to the first TSV 133a, the first TSV 133a is electrically connected to the second TSV 133b, and the second TSV 133b is an electromagnetic band gap pattern. By being electrically connected to 138, the ground voltage is supplied to the electromagnetic bandgap pattern 138. In order to supply the ground voltage to the electromagnetic bandgap pattern 138 as described above, the multilayer chip package 100 further includes a first solder bump 140a and a second solder bump 140b, and the first wiring layer ( 114 may include a first wiring 116, and the second wiring layer 134 may further include a first vertical wiring 139a and a second vertical wiring 139b. The first vertical wire 139a electrically connects the ground pattern 136 and the first TSV 133a, and the second vertical wire 139b electrically connects the electromagnetic bandgap pattern 138 and the second TSV 133b. Can be connected. The first solder bumps 140a are electrically connected to the first TSVs 133a, the second solder bumps 140b are electrically connected to the second TSVs 133b, and the first wires 116 are first soldered. The bump 140a and the second solder bump 140b may be electrically connected to each other.

Although not illustrated, an insulating material may be coated around the wiring 116 of the first wiring layer 114 and around the patterns 136, 137, 138, 139a, and 139b of the second wiring layer 134. . In addition, although not shown, an underfill resin layer may be formed around the solder bumps 140a and 140b for short-circuit prevention and buffering.

In an embodiment, the ground pattern 136 and the power supply voltage pattern 137 may be formed in a mesh form having a row direction and a column direction, respectively, in a grid form, and an electromagnetic band gap pattern. 138 may be formed in a cross shape. For example, as shown in FIG. 2, the ground pattern 136 is in the form of a first mesh including a plurality of first row patterns 136a and 136b and a plurality of first column patterns 136c and 136d. Can be formed. The power supply voltage pattern 137 may be formed in a second mesh shape including a plurality of second row patterns 137a and 137b and a plurality of second column patterns 137c and 137d. The plurality of second row patterns 137a and 137b may be disposed above the plurality of first row patterns 136a and 136b (that is, the second layer) to intersect with the plurality of first row patterns 136a and 136b. Within L2). The plurality of second column patterns 137c and 137d may be disposed above the plurality of first column patterns 136c and 136d (that is, the second layer) to intersect with the plurality of first column patterns 136c and 136d. Within L2). The electromagnetic bandgap pattern 138 may be formed in a cross shape so as to overlap the power supply voltage pattern 137 and not overlap the ground pattern 136. That is, the electromagnetic bandgap pattern 138 may be formed in the third layer L3 so as to correspond to an area where the second row patterns 137a and 137b and the second column patterns 137c and 137d cross each other. In this case, FIG. 1 may correspond to the cross-sectional view of FIG. 2 cut by A-A '.

The parallel LC resonator may be implemented by the structure as described above with reference to FIGS. 1 and 2. That is, the first and second TSVs 133a and 133b, the ground pattern 136, the power supply voltage pattern 137, and the electromagnetic bandgap pattern 138 may form the LC resonator. Specifically, based on the power supply voltage pattern 137 and the electromagnetic bandgap pattern 138, that is, the area of the power supply voltage pattern 137 to which the power supply voltage is applied, and the electromagnetic bandgap pattern 138 to which the ground voltage is applied. Capacitance components may be formed by the area and the distance between the power supply voltage pattern 137 and the electromagnetic bandgap pattern 138. In addition, an inductance component may be formed based on the first and second TSVs 133a and 133b, that is, as the ground voltage is applied to the first and second TSVs 133a and 133b. . Accordingly, the parallel LC resonator may be implemented based on the capacitance component and the inductance component, and transmission of noise corresponding to a cutoff frequency band among the noises transmitted to the stacked chip package 100 by the parallel LC resonator is blocked. Can be.

In general, in a parallel LC resonator, a bandstop type resonance occurs, and a center frequency of the cutoff frequency band, that is, a resonance frequency, may be determined from Equation 1 below.

[Equation 1]

In Equation 1, f _resonance.p represents the resonance frequency of the parallel LC resonator, and L _p and C _p represent the inductance and capacitance of the parallel LC resonator, respectively. In addition, the capacitance component formed based on the power supply voltage pattern 137 and the electromagnetic bandgap pattern 138 may satisfy Equation 2 below.

&Quot; (2) "

In Equation 2, C _p represents a value of the capacitance component, ε represents a dielectric constant of an insulating material formed between the power supply voltage pattern 137 and the electromagnetic bandgap pattern 138, and A _ebg is The area of the electromagnetic bandgap pattern 138 is represented, and d represents the distance between the power supply voltage pattern 137 and the electromagnetic bandgap pattern 138.

From the above Equations 1 and 2, the capacitance component formed based on the power supply voltage pattern 137 and the electromagnetic bandgap pattern 138 as the area of the electromagnetic bandgap pattern 138 increases. The value of increases and the center frequency of the cutoff frequency band of the parallel LC resonator decreases. Specifically, when the area of the electromagnetic bandgap pattern 138 increases by N ² (N is any real number) times, the center frequency of the cutoff frequency band of the parallel LC resonator may be lowered by N times.

The stacked chip package 100 according to an exemplary embodiment may include an electromagnetic bandgap pattern formed between the power supply voltage pattern 137 and the ground pattern 136 so as to overlap the power supply voltage pattern 137 and to which a ground voltage is applied. 138, wherein the electromagnetic bandgap pattern 138 can operate as an LC resonator with the first and second TSVs 133a and 133b, the ground pattern 136, and the power supply voltage pattern 137. have. Since the LC resonator is implemented as passive elements and does not require an active region of a semiconductor chip, the LC resonator can be implemented in a relatively simple structure and at a relatively low cost. It is possible and has a relatively high noise cutoff level, and the cutoff frequency band can be easily adjusted by adjusting the area of the electromagnetic bandgap pattern 138. Therefore, the stacked chip package 100 may effectively block noise propagation without increasing manufacturing cost and / or size.

3 and 4 are diagrams for describing noise blocking characteristics of the stacked chip package of FIG. 1. 3 illustrates a structure of the stacked chip package of FIG. 1, and FIG. 4 illustrates a noise blocking effect according to a frequency band. In FIG. 4, CASE1 represents the frequency transfer characteristics of a conventional stacked chip package that does not include an electromagnetic bandgap pattern 138, and CASE2 includes an electromagnetic bandgap pattern 138 according to one embodiment of the present invention. Frequency transfer characteristics of the multilayer chip package 100 of FIG. 1 are shown.

Referring to FIG. 3, one of the cell structures 1000 included in the power distribution network structure modeling the stacked chip package 100 of FIG. 1 may include a power supply voltage transfer unit 1370 and an electromagnetic band gap unit 1380. The first ground voltage transmitter 1160, the second ground voltage transmitter 1360, and the TSV units 1330 are included. The power supply voltage transmitter 1370 corresponds to the power supply voltage pattern 137 of FIG. 1, the electromagnetic bandgap unit 1380 corresponds to the electromagnetic bandgap pattern 138 of FIG. 1, and the first ground voltage transmitter 1160. ) Corresponds to the first wiring 116 of FIG. 1, the second ground voltage transmitting unit 1360 corresponds to the ground pattern 136 of FIG. 1, and the TSV units 1330 are formed of the first and first layers of FIG. 1. It may correspond to two TSVs 133a and 133b. For example, one cell structure 1000 may have a cube structure having a width, length, and height of about 900 μm.

Referring to FIG. 4, a simulation result of a power distribution network structure formed by arranging 18 cell structures 1000 of FIG. 3 horizontally and vertically is shown. As shown by CASE1, the cutoff frequency band does not appear in the graph of the frequency transfer characteristic of the conventional multilayer chip package, and the conventional multilayer chip package does not effectively block noise. On the other hand, as shown by CASE2, the cutoff frequency band SBW1 is clearly shown in the graph of the frequency transfer characteristic of the stacked chip package 100 of FIG. 1, and the stacked chip package 100 of FIG. You can check the block. For example, the stacked chip package 100 of FIG. 1 may block noise from about 6.2 GHz to about 14.1 GHz, and a width of the cutoff frequency band SBW1 may be about 7.9 GHz.

5 is a flowchart illustrating a method of manufacturing a stacked chip package according to an embodiment of the present invention.

1, 2 and 5, in the method of manufacturing a stacked chip package having an electromagnetic bandgap pattern according to an embodiment of the present invention, the first wiring layer 114 is formed on the entire surface of the first semiconductor die 112. To form the first semiconductor chip 110 (step S110), and form the first and second TSVs 133a and 133b penetrating through the second semiconductor die 132 (step S120). The ground pattern 136 disposed in the layer L1, the power voltage pattern 137 disposed in the second layer L2, and the third layer L3 between the first layer L1 and the second layer L2. A second wiring layer 134 including an electromagnetic bandgap pattern 138 disposed therein is formed on the entire surface of the second semiconductor die 132 to provide a second semiconductor chip 130 (step S130). By stacking the second semiconductor chip 130 on the semiconductor chip 110, the stacked chip package 100 is manufactured. The ground pattern 136 is electrically connected to the first TSV 133a, the first TSV 133a is electrically connected to the second TSV 133b, and the second TSV 133b is connected to the electromagnetic bandgap pattern 138. The ground voltage is electrically connected to the electromagnetic bandgap pattern 138.

According to an embodiment, the plurality of patterns 136, 137, and 138 and the plurality of TSVs 133a and 133b may be formed in a different order according to the manufacturing process of the interposer. For example, when a via-via process is applied, a plurality of TSVs 133a and 133b may be formed first, and then a plurality of metal lines 136, 137 and 138 may be formed. In another example, when applying a via last process, the plurality of metal wires 136, 137, and 138 may be formed first, and then the plurality of TSVs 133a and 133b may be formed.

6 is a cross-sectional view illustrating a stacked chip package according to another exemplary embodiment of the present disclosure. FIG. 7 is a diagram for describing a structure of the stacked chip package of FIG. 6. FIG. 7 is a plan view viewed from an upper surface of the second semiconductor chip included in the stacked chip package of FIG. 6, and illustrates only the arrangement of the ground pattern, the power voltage pattern, and the electromagnetic bandgap patterns for convenience.

6 and 7, the stacked chip package 200 including the plurality of electromagnetic band gap patterns 238a and 238b may include a first semiconductor chip 210, a second semiconductor chip 230, and a third semiconductor chip. 250. The first and second semiconductor chips 210 and 230 have a structure similar to that of the first and second semiconductor chips 110 and 130 of FIG. 1, and overlapping description thereof will be omitted.

The first semiconductor chip 210 includes a first semiconductor die 212 and a first wiring layer 214 formed on an entire surface of the first semiconductor die 212. Although not shown, the first semiconductor die 212 may include a plurality of first elements, and the first wiring layer 214 may supply power voltages, ground voltages, and / or other electrical signals to the first semiconductor chip 210. It may include a plurality of metal wires for supplying them.

The second semiconductor chip 230 includes a second semiconductor die 232, a first TSV 233a, a second TSV 233b, and a second wiring layer 234. The second semiconductor die 232 may include a plurality of second devices (not shown). The first and second TSVs 233a and 233b are formed through the second semiconductor die 232. The second wiring layer 234 is formed on the entire surface of the second semiconductor die 232. The second wiring layer 234 includes a ground pattern 236 disposed in the first layer L1, a power supply voltage pattern 237 disposed in the second layer L2 on the first layer L1, and a first layer ( First and second electromagnetic bandgap patterns 238a and 238b disposed in the third layer L3 between L1 and the second layer L2.

The third semiconductor chip 250 includes a third semiconductor die 252, a third TSV 253a, a fourth TSV 253b, and a third wiring layer 254. The third and fourth TSVs 253a and 253b are formed through the third semiconductor die 252. The third wiring layer 254 is formed on the entire surface of the third semiconductor die 252. Although not shown, the third semiconductor die 252 may include a plurality of third elements, and the third wiring layer 254 may be configured to supply the power voltage, the ground voltage, and / or the third semiconductor chip 250 to the third semiconductor chip 250. It may include a plurality of metal wires for supplying external electrical signals.

The ground voltage is supplied to the first electromagnetic band gap pattern 238a, and the power supply voltage is supplied to the second electromagnetic band gap pattern 238b. That is, the ground pattern 236 is electrically connected to the first TSV 233a, the first TSV 233a is electrically connected to the second TSV 233b, and the second TSV 233b is the first electromagnetic band gap pattern. The ground voltage is supplied to the first electromagnetic bandgap pattern 238a by being electrically connected to 238a. In addition, the power supply voltage pattern 237 is electrically connected to the third TSV 253a, the third TSV 253a is electrically connected to the fourth TSV 253b, and the fourth TSV 253b is the second electromagnetic band gap. The power supply voltage is supplied to the second electromagnetic band gap pattern 238b by being electrically connected to the pattern 238b.

In order to supply the ground voltage and the power voltage to the electromagnetic bandgap patterns 238a and 238b as described above, the multilayer chip package 100 further includes solder bumps 240a, 240b, 260a, and 260b. The first wiring layer 214 includes the first wiring 216, the second wiring layer 234 further includes vertical wirings 239a, 239b, 239c, and 239d, and the third wiring layer 254 includes the second wiring. It may further include (256). The first vertical wire 239a electrically connects the ground pattern 236 and the first TSV 233a, and the second vertical wire 239b connects the first electromagnetic bandgap pattern 238a and the second TSV 233b. Are electrically connected to each other, the first solder bumps 240a are electrically connected to the first TSVs 233a, and the second solder bumps 240b are electrically connected to the second TSVs 233b, 216 may electrically connect the first solder bumps 240a and the second solder bumps 240b. The third solder bump 260a is electrically connected to the third TSV 253a, the fourth solder bump 260b is electrically connected to the fourth TSV 253b, and the second wiring 256 is connected to the third TSV. 253a and the fourth TSV 253b may be electrically connected to each other. The third vertical wire 239c electrically connects the power voltage pattern 237 and the third solder bump 260a, and the fourth vertical wire 239d connects the second electromagnetic bandgap pattern 238b and the fourth solder bump. 260b can be electrically connected.

In one embodiment, as shown in FIG. 7, the ground pattern 236 is in the form of a first mesh including a plurality of first row patterns 236a and 236b and a plurality of first column patterns 236c and 236d. The power supply voltage pattern 237 may be formed in a second mesh shape including a plurality of second row patterns 237a and 237b and a plurality of second column patterns 237c and 237d. . The plurality of second row patterns 237a and 237b are disposed in the second layer L2 to cross the plurality of first row patterns 236a and 236b, and the plurality of second column patterns 237c and 237d. May be disposed in the second layer L2 to cross the plurality of first column patterns 236c and 236d. The first electromagnetic bandgap pattern 238a may be formed in a cross shape to overlap the power supply voltage pattern 237 and not overlap the ground pattern 236. The second electromagnetic bandgap pattern 238b may be formed in a cross shape to overlap the ground pattern 236 and not overlap the power supply voltage pattern 237. In this case, FIG. 6 may correspond to the cross-sectional view of FIG. 6 cut by BB ′.

Parallel LC resonators may be implemented by the same structure as described above with reference to FIGS. 6 and 7. Specifically, the first capacitance component is formed based on the power supply voltage pattern 237 and the first electromagnetic bandgap pattern 238a, and the first inductance component is based on the first and second TSVs 233a and 233b. Can be formed. In addition, a second capacitance component may be formed based on the ground pattern 236 and the second electromagnetic bandgap pattern 238b, and a second inductance component may be formed based on the third and fourth TSVs 253a and 253b. have. That is, two parallel LC resonators may be implemented in the first and second capacitance components and the first and second inductance components, and the two parallel LC resonators may be transferred to the stacked chip package 200. The transmission of noise corresponding to the cutoff frequency band among the noises can be efficiently cut off. In this case, as the area of the electromagnetic bandgap patterns 238a and 238b increases, the center frequency of the cutoff frequency band may decrease, and the distance between the power supply voltage pattern 237 and the first electromagnetic bandgap pattern 238a ( d1) may be different from the distance d2 between the ground pattern 236 and the second electromagnetic bandgap pattern 238b.

FIG. 8 is a diagram illustrating noise blocking characteristics of the stacked chip package of FIG. 6.

Referring to FIG. 8, a simulation result of a structure formed by arranging one cell structure included in a power distribution network structure modeling a stacked chip package (200 of FIG. 6) by 18 in a horizontal and vertical direction, respectively, is illustrated. In the graph of the frequency transfer characteristic of the stacked chip package 200 of FIG. 6, the cutoff frequency band SBW2 is clearly shown, and the stacked chip package 600 of FIG. 6 may block noise more efficiently. For example, the stacked chip package 200 of FIG. 6 may block noise from about 5.9 GHz, and the width of the cutoff frequency band SBW2 may be about 14.1 GHz.

9 is a flowchart illustrating a method of manufacturing a stacked chip package according to another exemplary embodiment of the present invention.

6, 7 and 9, in a method of manufacturing a stacked chip package having a plurality of electromagnetic bandgap patterns according to another exemplary embodiment of the present invention, a first wiring layer (on the front surface of the first semiconductor die 212) may be formed. 214 to form a first semiconductor chip 210 (step S210), and form first and second TSVs 233a and 233b that penetrate the second semiconductor die 232 (step S220), The ground pattern 236 disposed in the first layer L1, the power voltage pattern 237 disposed in the second layer L2, and the third layer between the first layer L1 and the second layer L2 ( A second wiring layer 234 including first and second electromagnetic bandgap patterns 238a and 238b disposed in L3) is formed on the entire surface of the second semiconductor die 232 to form the second semiconductor chip 230. Provide (step S230), form third and fourth TSVs 253a, 253b penetrating the third semiconductor die 252 (step S240), and form a first surface on the front surface of the third semiconductor die 252. Wiring 254 to form a first semiconductor chip 250 (step S250), and by laminating the second semiconductor chip 230 and the third semiconductor chip 250 on the first semiconductor chip 210, The chip package 200 is manufactured. The first electromagnetic bandgap pattern 238a is supplied with a ground voltage through the ground pattern 236, the first TSV 233a and the second TSV 233b, and the second electromagnetic bandgap pattern 238b is a power supply voltage pattern. 237, a power supply voltage is supplied through the third TSV 253a and the fourth TSV 253b.

10 and 11 are cross-sectional views illustrating semiconductor modules according to example embodiments.

Referring to FIG. 10, the semiconductor module 300 includes a base substrate 301 and a stacked chip package mounted on the base substrate 301. For example, the base substrate 301 may be a PCB substrate. The stacked chip package includes a first semiconductor chip 110 and a second semiconductor chip 130.

The first semiconductor chip 110 is substantially the same as the first semiconductor chip 110 of FIG. 1 except that the first semiconductor chip 110 further includes a plurality of TSVs 113 formed through the first semiconductor die 112. It has a structure, and since the second semiconductor chip 130 has a structure substantially the same as the second semiconductor chip 130 included in FIG. 1, redundant description thereof will be omitted. The semiconductor module 300 may further include solder bumps 310 electrically connecting the stacked chip package and the base substrate 301.

Referring to FIG. 11, the semiconductor module 400 includes a base substrate 401 and a stacked chip package mounted on the base substrate 401. The stacked chip package includes a first semiconductor chip 210, a second semiconductor chip 230, and a third semiconductor chip 250.

The first semiconductor chip 210 is substantially the same as the first semiconductor chip 210 of FIG. 6 except that the first semiconductor chip 210 further includes a plurality of TSVs 213 formed through the first semiconductor die 212. The second and third semiconductor chips 230 and 250 have a structure substantially the same as that of the second and third semiconductor chips 230 and 250 included in FIG. 6. The semiconductor module 400 may further include solder bumps 410 electrically connecting the stacked chip package and the base substrate 401.

The semiconductor modules 300 and 400 according to embodiments of the present invention include stacked chip packages having electromagnetic bandgap patterns 138, 238a, and 238b that operate as LC resonators, thereby increasing manufacturing costs and / or sizes. Noise can be effectively blocked without In addition, by including a plurality of TSVs 113 and 213 penetrating through the first semiconductor die 112 and 212, a length of a signal transmission path of the multilayer chip package and external devices included in the semiconductor module 300 and 400 may be provided. It can reduce the and improve the operating characteristics of the laminated chip package.

The stacked chip package according to the embodiments of the present invention may be applied to various semiconductor modules and electronic systems including the same. In particular, a computer, a digital camera, a 3D camera, a mobile phone, a PDA, a scanner, a car navigation system, a video phone, a surveillance system It can be usefully used for an auto focus system, a tracking system, a motion detection system, an image stabilization system, and the like.

While the present invention has been described with reference to the preferred embodiments thereof, it will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit and scope of the invention as defined in the appended claims. It will be understood.

Claims (15)

A laminated chip package having an electromagnetic bandgap pattern,
A first semiconductor chip having a first semiconductor die and a first wiring layer formed on an entire surface of the first semiconductor die; And
A second semiconductor die, first and second through silicon vias (TSVs) penetrating through the second semiconductor die, and a second wiring layer formed on an entire surface of the second semiconductor die; A second semiconductor chip stacked on the first semiconductor chip,
The second wiring layer includes a ground pattern disposed in a first layer, a power supply voltage pattern disposed in a second layer, and the electromagnetic bandgap pattern disposed in a third layer between the first layer and the second layer,
The ground pattern is electrically connected to the first TSV, the first TSV is electrically connected to the second TSV, and the second TSV is electrically connected to the electromagnetic bandgap pattern to provide a ground voltage to the electromagnetic bandgap pattern. This is supplied laminated chip package. The method of claim 1, wherein the ground pattern is formed in a first mesh shape including a plurality of first row patterns and a plurality of first column patterns, and the power voltage pattern is formed in the plurality of first row patterns. And a second mesh including a plurality of second row patterns intersected with each other and a plurality of second column patterns interposed with the plurality of first column patterns, wherein the electromagnetic bandgap pattern is formed in the power source. The stacked chip package of claim 1, wherein the stacked chip package is formed in a cross shape so as to overlap the voltage pattern and not overlap the ground pattern. The method of claim 2, wherein the second wiring layer,
A first vertical wire electrically connecting the ground pattern and the first TSV; And
And a second vertical interconnection electrically connecting the electromagnetic bandgap pattern and the second TSV. The method of claim 3, further comprising a first solder bump electrically connected to the first TSV and a second solder bump electrically connected to the second TSV.
The first wiring layer may further include a first wiring electrically connecting the first solder bumps and the second solder bumps. The method of claim 2, wherein a capacitance component is formed based on the power supply voltage pattern and the electromagnetic bandgap pattern, and an inductance component is formed based on the first TSV and the second TSV. The transfer of the noise corresponding to the cut-off frequency band of the noise transmitted to the multilayer chip package based on the capacitance component and the inductance component is cut off. The multilayer chip package of claim 5, wherein the center frequency of the cutoff frequency band decreases as the area of the electromagnetic bandgap pattern increases. In the manufacturing method of a laminated chip package having an electromagnetic bandgap pattern,
Forming a first wiring layer on a front surface of the first semiconductor die to provide a first semiconductor chip;
Forming first and second through silicon vias (TSVs) through the second semiconductor die;
A second wiring layer including a ground pattern disposed in a first layer, a power supply voltage pattern disposed in a second layer, and the electromagnetic bandgap pattern disposed in a third layer between the first layer and the second layer; Forming on a front surface of a second semiconductor die to provide a second semiconductor chip; And
Stacking the second semiconductor chip on the first semiconductor chip;
The ground pattern is electrically connected to the first TSV, the first TSV is electrically connected to the second TSV, and the second TSV is electrically connected to the electromagnetic bandgap pattern to provide a ground voltage to the electromagnetic bandgap pattern. The manufacturing method of the laminated chip package supplied with this. A stacked chip package having a plurality of electromagnetic bandgap patterns,
A first semiconductor chip having a first semiconductor die and a first wiring layer formed on an entire surface of the first semiconductor die;
A second semiconductor die, first and second through silicon vias (TSVs) penetrating through the second semiconductor die, and a second wiring layer formed on an entire surface of the second semiconductor die; A second semiconductor chip stacked on the first semiconductor chip; And
A third semiconductor die, third and fourth TSVs penetrating through the third semiconductor die, and a third wiring layer formed on an entire surface of the third semiconductor die, and stacked on the second semiconductor chip. 3 contains a semiconductor chip,
The second wiring layer may include a ground pattern disposed in a first layer, a power supply voltage pattern disposed in a second layer, and first and second electromagnetic band gap patterns disposed in a third layer between the first layer and the second layer. Including the
The ground pattern is electrically connected to the first TSV, the first TSV is electrically connected to the second TSV, and the second TSV is electrically connected to the first electromagnetic bandgap pattern, thereby providing the first electromagnetic bandgap. A ground voltage is supplied to the pattern, the power voltage pattern is electrically connected to the third TSV, the third TSV is electrically connected to the fourth TSV, and the fourth TSV is electrically connected to the second electromagnetic bandgap pattern. The stacked chip package is connected to the power supply voltage is supplied to the second electromagnetic bandgap pattern. The method of claim 8, wherein the ground pattern is formed in a first mesh shape including a plurality of first row patterns and a plurality of first column patterns, and the power supply voltage pattern is in the plurality of first row patterns. And a second mesh including a plurality of second row patterns that are alternately disposed with each other and a plurality of second column patterns that are alternately disposed with the plurality of first column patterns.
The first electromagnetic bandgap pattern is formed in a cross shape to overlap the power supply voltage pattern and not overlap the ground pattern, and the second electromagnetic bandgap pattern overlaps the ground pattern and does not overlap the power supply voltage pattern. Stacked chip package, characterized in that formed in the cross shape. The method of claim 9, further comprising a first solder bump electrically connected to the third TSV and a second solder bump electrically connected to the fourth TSV.
The third wiring layer further comprises a first wiring electrically connecting the third TSV and the fourth TSV. The method of claim 10, wherein the second wiring layer,
A first vertical wire electrically connecting the power supply voltage pattern and the third solder bump; And
And a second vertical interconnection electrically connecting the second electromagnetic bandgap pattern and the fourth solder bumps. The method of claim 9, wherein a first capacitance component is formed based on the power supply voltage pattern and the first electromagnetic bandgap pattern, and a first inductance based on the first TSV and the second TSV. A component is formed, a second capacitance component is formed based on the ground pattern and the second electromagnetic bandgap pattern, and a second inductance component is formed based on the third TSV and the fourth TSV,
Based on the first and second capacitance components and the first and second inductance components, transmission of noise corresponding to a cutoff frequency band among noises transmitted to the multilayer chip package is cut off. . The multilayer chip package of claim 9, wherein a distance between the power supply voltage pattern and the first electromagnetic bandgap pattern is different from a distance between the ground pattern and the second electromagnetic bandgap pattern. In the manufacturing method of a laminated chip package having a plurality of electromagnetic bandgap patterns,
Forming a first wiring layer on a front surface of the first semiconductor die to provide a first semiconductor chip;
Forming first and second through silicon vias (TSVs) through the second semiconductor die; And
A second pattern including a ground pattern disposed in a first layer, a power supply voltage pattern disposed in a second layer, and first and second electromagnetic bandgap patterns disposed in a third layer between the first layer and the second layer. Forming a wiring layer on the entire surface of the second semiconductor die to provide a second semiconductor chip;
Forming third and fourth TSVs through the third semiconductor die;
Forming a third wiring layer on an entire surface of the third semiconductor die to provide a third semiconductor chip; And
Stacking the second semiconductor chip and the third semiconductor chip on the first semiconductor chip;
The ground pattern is electrically connected to the first TSV, the first TSV is electrically connected to the second TSV, and the second TSV is electrically connected to the first electromagnetic bandgap pattern, thereby providing the first electromagnetic bandgap. A ground voltage is supplied to the pattern, the power voltage pattern is electrically connected to the third TSV, the third TSV is electrically connected to the fourth TSV, and the fourth TSV is electrically connected to the second electromagnetic bandgap pattern. And a power supply voltage supplied to the second electromagnetic bandgap pattern. A base substrate; And
A stacked chip package mounted on the base substrate and having an electromagnetic bandgap pattern;
The laminated chip package,
A first semiconductor chip having a first semiconductor die and a first wiring layer formed on an entire surface of the first semiconductor die; And
A second semiconductor die, first and second through silicon vias (TSVs) penetrating through the second semiconductor die, and a second wiring layer formed on an entire surface of the second semiconductor die; A second semiconductor chip stacked on the first semiconductor chip,
The second wiring layer includes a ground pattern disposed in a first layer, a power supply voltage pattern disposed in a second layer, and the electromagnetic bandgap pattern disposed in a third layer between the first layer and the second layer,
The ground pattern is electrically connected to the first TSV, the first TSV is electrically connected to the second TSV, and the second TSV is electrically connected to the electromagnetic bandgap pattern to provide a ground voltage to the electromagnetic bandgap pattern. This semiconductor module is supplied.

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